Semiconductor structure and manufacturing method thereof

Abstract

The present invention discloses a semiconductor structure and a method for manufacturing the same, comprising a substrate having a plurality of grooves and active areas, a plurality of bit lines arranged at equal intervals along a first direction on the memory cell area and extending in a second direction orthogonal to the first direction, wherein the bit line is electrically connected to an active area in the substrate via one of the grooves, and a dummy bit line located at the outermost side of the bit lines in the first direction and extending in the second direction, wherein the width of the dummy bit line in the first direction is greater than the width of the bit lines in the first direction, and the bottom of the dummy bit line is not in the same horizontal plane, and the dummy bit line has the same composition and layer structure as the bit lines.

Description

Technical Field

[0001] The embodiments disclosed in the present invention relate to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure with bit lines of different widths and a manufacturing method thereof. Background Art

[0002] A memory device is an integrated circuit typically used in computer systems to store data. It is fabricated as an array of one or more individual memory cells. Memory devices are written to and read from using bit lines (also known as digit lines, data lines, or read lines) and word lines (also known as access lines). Bit lines are electrically connected to memory cells along the vertical columns of the matrix, while word lines are electrically connected to memory cells along the horizontal columns of the matrix. Each memory cell can be individually addressed using a combination of a bit line and a word line.

[0003] Memory devices can be volatile, semi-volatile, or non-volatile. In the absence of power, non-volatile memory devices can store data for a long time, while the data stored in volatile memory devices will dissipate, so they need to be constantly refreshed / rewritten to maintain their data storage. Memory devices use components such as capacitors to store charges, and read the charge of the capacitor to determine which storage state the memory cell is in, such as the "0" or "1" storage state, so as to achieve the purpose of data storage and reading. Memory devices also have electronic components such as transistors to control the switching of the gate and the storage and release of charge. There will be a peripheral circuit area around the memory cell array area of ​​the memory device, and the bit lines and word lines will extend from the memory array area to the peripheral circuit area, and in this area they will be electrically connected to the external circuit via other interconnect structures such as wires and contacts.

[0004] When manufacturing memory devices or other circuits, continuously miniaturizing and increasing the density of components to achieve higher storage capacity per unit area has always been a constant goal in the industry. However, as memory devices continue to shrink, their manufacturing processes also encounter numerous challenges that need to be overcome, such as microloading effects caused by varying pattern densities, and insufficient layout space due to overly close spacing of components. The present invention is motivated by the need to overcome some of these challenges encountered in circuit manufacturing. Summary of the Invention

[0005] The present invention proposes a novel semiconductor structure and a manufacturing method thereof, wherein the outermost dummy bit lines have a larger width and different partition wall types, thereby solving the problem of device micro-loading effect.

[0006] One aspect of the present invention is to provide a semiconductor structure, characterized in that it includes a substrate on which a memory cell area is defined, and the substrate further has a plurality of grooves, a plurality of bit lines arranged at equal intervals along a first direction on the memory cell area and extending in a second direction orthogonal to the first direction, and the bit line is electrically connected to an active area in the substrate through one of the grooves, and a dummy bit line is located at an outermost side of the bit lines in the first direction and extends in the second direction, wherein the width of the dummy bit line in the first direction is greater than the width of the bit line in the first direction, and the bottom of the dummy bit line is not in the same horizontal plane, the dummy bit line has the same composition and layer structure as the bit lines, and a portion of the dummy bit line is located in one of the grooves and electrically connected to an active area in the substrate.

[0007] Another aspect of the present invention is to provide a method for fabricating a semiconductor structure, characterized by providing a substrate having a memory cell region defined thereon and further having a plurality of recesses, forming a bit line material layer on the substrate, and forming a plurality of bit line shielding patterns on the bit line material layer, wherein the bit line shielding patterns are arranged at equal intervals along a first direction on the memory cell region and extend in a second direction orthogonal to the first direction, and forming a photoresist on the bit line shielding patterns, wherein the photoresist covers an area outside the memory cell region and the bit line shielding patterns located outermost in the first direction. However, the other bit line shielding patterns are exposed, and the bit line material layer is etched using the photoresist and the bit line shielding patterns as etching masks, thereby forming a plurality of bit lines and a dummy bit line located at the outermost sides of the bit lines in the first direction, wherein the bit lines and the dummy bit line extend in the second direction, and the bit line is electrically connected to an active area via the groove, the width of the dummy bit line in the first direction is greater than the width of the bit line in the first direction, and the dummy bit line has the same composition and layer structure as the bit lines, and a portion of the dummy bit line is located in the groove and electrically connected to an active area.

[0008] These and other objects of the present invention will become more readily apparent to the reader after reading the following detailed description of the preferred embodiment which is illustrated in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] This specification includes accompanying drawings, which form a part of this specification and are intended to provide a further understanding of embodiments of the present invention. These drawings depict some embodiments of the present invention and, together with the description herein, illustrate the principles thereof. In these drawings:

[0010] Figure 1A 、 Figure 2A as well as Figure 3Ais a cross-sectional schematic diagram of a manufacturing process of a semiconductor structure according to a preferred embodiment of the present invention;

[0011] Figure 1B 、 Figure 2B as well as Figure 3B Respectively Figure 1A 、 Figure 2A as well as Figure 3A Schematic diagram of the cross section made by the midline A-A';

[0012] Figure 4 is a schematic cross-sectional view of a semiconductor structure according to a preferred embodiment of the present invention;

[0013] Figure 5 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

[0014] Figure 6 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention;

[0015] Figure 7 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention;

[0016] Figure 8 is a schematic cross-sectional view of a semiconductor structure according to a preferred embodiment of the present invention;

[0017] Figure 9 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention;

[0018] Figure 10 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention; and

[0019] Figure 11 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

[0020] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0021] The description of the accompanying drawings is as follows:

[0022] 100 semiconductor substrate

[0023] 100a storage unit area

[0024] 100b active area

[0025] 100c active area

[0026] 102 device isolation layer

[0027] 103 grooves

[0028] 104 insulation layer

[0029] 105 Grooves

[0030] 106 contact layer

[0031] 108 Barrier Layer

[0032] 110 Metal Layer

[0033] 112 hard mask layer

[0034] 114-bit line shield pattern

[0035] 116 Photoresist

[0036] 118 bit line spacers

[0037] 119 bit line spacers

[0038] 120 Next door

[0039] 122 Next door

[0040] 124 Spacer

[0041] 126 Spacer

[0042] 128 spacer layers

[0043] 130 groove

[0044] 131 contact area

[0045] 132 polysilicon layer

[0046] 134 Silicide Layer

[0047] 136 Barrier Layer

[0048] 138 Metal Layer

[0049] BL bit line

[0050] DBL dummy bit line

[0051] D1 First direction

[0052] D2 Second direction

[0053] SC storage node contact structure

[0054] W1, W2, W3, W4 width DETAILED DESCRIPTION

[0055] In the illustrations in this manual, Figure 1A 、 Figure 2A as well as Figure 3A A plan view showing a process flow of manufacturing a semiconductor structure according to a preferred embodiment of the present invention is shown. Figure 1B 、 Figure 2B as well as Figure 3B They are respectively along Figure 1A 、 Figure 2A as well as Figure 3A The cross-sectional view taken along the line AA′ illustrates the relative positions of the components of the semiconductor structure of the present invention in a direction perpendicular to the substrate and their connection relationships.

[0056] First, please refer to Figure 1A and Figure 1B . The semiconductor structure of the present invention is fabricated on a semiconductor substrate 100, such as a silicon substrate, a germanium substrate and / or a silicon-germanium substrate. A memory cell region 100a is defined on the semiconductor substrate 100, which is used to set up memory cells (cells) of a semiconductor memory device. A plurality of memory cells can be arranged in an array in the memory cell region 100a and can store charges to generate distinct storage states, thereby achieving a storage effect. The memory cell region 100a may be surrounded by a peripheral region (not shown) for setting up peripheral circuits of the memory device, such as column decoders, row decoders, sense amplifiers, or I / O control modules. A plurality of active regions 100b are defined in the memory cell region 100a of the semiconductor substrate 100, and each active region 100b is separated and defined by a surrounding device isolation layer 102, such as a shallow trench isolation structure (STI). During the process, a photolithography process can be performed on the semiconductor substrate 100 to form individually separated active regions 100b. Isolation materials, such as silicon oxide, are then filled into the trenches between the active regions 100b to form a device isolation layer 102. An insulating layer 104 is formed on the surface of the semiconductor substrate 100 to isolate the underlying active regions 100b from the components above. It can also serve as a gate dielectric layer for the gate elements in the peripheral region. The insulating layer 104 can be formed from a single insulating layer or multiple insulating layers, such as a silicon nitride layer, a silicon nitride layer, and / or a silicon oxynitride layer. Recesses 103 are formed in portions of the active regions 100b, exposing portions of the active regions 100b from the insulating layer 104. It should be noted that in practice, the active regions 100b can be strip-shaped in a plan view, with their long axes extending in the same direction, and can be evenly arranged in a staggered arrangement in a plan view. Since the active region 100b is not the focus of the present invention, for the sake of simplicity and to avoid blurring the focus of the present invention, Figure 1A Only the memory cell region 100 a and the bit line shielding pattern 114 thereon are shown.

[0057] Re-reference Figure 1A and Figure 1B . A contact layer 106, a barrier layer 108, a metal layer 110 and a hard mask layer 112 are sequentially formed on the memory cell area 100a of the semiconductor substrate 100, which can define these layer structures on the memory cell area 100a through an anisotropic photolithography process. The process may also simultaneously define the gate components located in the peripheral area. Preferably, the material of the contact layer 106 can be doped polysilicon, the material of the barrier layer 108 can be metal nitride, such as titanium nitride, tantalum nitride and / or tungsten nitride, the material of the metal layer 110 can be a low-resistance metal, such as tungsten, aluminum, titanium or tantalum, and the material of the hard mask layer 112 can be silicon nitride or silicon oxynitride. Part of the contact layer 106 will be formed in the groove 103 and electrically connected to the exposed active area 100b. From Figure 1A As can be seen in FIG, a plurality of annular bit line shielding patterns 114 are formed on the semiconductor substrate 100. These annular bit line shielding patterns 114 are arranged at intervals in a first direction D1 and extend in a second direction D2 perpendicular to the first direction D1 and across the memory cell region 100a. Both ends of these annular patterns are located outside the memory cell region 100a. Figure 1B From a cross-sectional perspective, the bit line shielding pattern 114 passing through the memory cell region 100a is located on the hard mask layer 112, and is preferably aligned with the recess 103 and the device isolation layer 102 in the lower portion. The material of the bit line shielding pattern 114 can be a material having etching selectivity with the lower hard mask layer 112, such as silicon oxide, which can be formed by a double patterning method. For example, the steps of forming the annular patterns may include: (1) forming a plurality of sacrificial patterns on the bit line material layer, the sacrificial patterns being arranged at equal intervals along the first direction D1 on the memory cell region 100a and extending in the second direction D2; (2) forming spacers on the sidewalls of the sacrificial patterns; and (3) removing the sacrificial patterns, so that the spacers form the annular bit line shielding patterns.

[0058] Please also refer to Figure 2A and Figure 2B After the above layer structure and the bit line shielding pattern 114 are formed, a photoresist 116 for trimming is formed on the bit line shielding pattern 114. Figure 2A As shown, the photoresist 116 covers the area outside the memory cell region 100a, including the two ends of the annular patterns in the second direction D2, and covers the bit line shield pattern 114 located on the outermost side of the memory cell region 100a in the first direction D1, while leaving the remaining bit line shield pattern 114 located on the memory cell region 100a exposed. Thus, it can be seen that part of the layer structure in the memory cell region 100a is also covered by the photoresist 116, and the annular patterns exposed from the photoresist 116 become the plurality of bit line shield patterns 114 extending in the second direction D2.

[0059] Please also refer to Figure 3A and Figure 3B After the photoresist 116 is formed, an etching process is performed using the photoresist 116 and the bit line shielding pattern 114 as a mask to remove the exposed layer structure, which includes the contact layer 106, the barrier layer 108, the metal layer 110 and the hard mask layer 112, thereby forming the bit line BL and the dummy bit line DBL structure on the memory cell area 100a. Figure 3A As can be seen in FIG, the bit lines BL and the dummy bit lines DBL are arranged at equal intervals in the first direction D1 and extend in the second direction D2 through the memory cell area 100a. The two dummy bit lines DBL are located at the outermost side in the first direction D1. Figure 3B As can be seen in the figure, the dummy bit line DBL has the same composition and layer structure as the bit line BL. The resulting bit line BL is electrically connected to the underlying active area 100b via its contact layer 106. The contact layer 106 of the dummy bit line DBL located in the recess 103 forms a small trench 105 with the sidewall of the recess 103. A portion of the dummy bit line DBL located on the outermost side of the memory cell region 100a is located within the recess 103 and electrically connected to the underlying active area 100b. Due to the aforementioned trimming process, the width W1 of the dummy bit line DBL in the first direction D1 is greater than the width W2 of the bit line BL in the first direction D1. Forming the wider dummy bit line DBL on the outermost side of the memory cell region 100a helps alleviate the problem of deformation or collapse of the outermost bit line structure due to microloading in conventional techniques. Furthermore, forming the dummy bit line DBL simultaneously on the recess surface and the substrate surface at different levels also makes the outermost dummy bit line DBL more stable and less prone to collapse.

[0060] Please refer to Figure 4 After the bit line BL and the dummy bit line DBL are formed, a bit line spacer 118 is formed in the trench 105. The bit line spacer 118 can be formed of an insulating material having an etching selectivity relative to the insulating layer 104, such as silicon oxide, silicon nitride, silicon oxynitride, or a multi-layer structure composed of a combination thereof. After the bit line spacer 118 is formed, spacers 120 and 122 are formed on both sides of the bit line BL and the dummy bit line DBL, which can be formed through a deposition process and an anisotropic etching process. Figure 4As can be seen in the figure, the width W4 of the spacers 122 located outside the dummy bit line DBL in the first direction D1 is greater than the width W3 of the spacers 120 located inside the dummy bit line DBL and the spacers 120 on both sides of the bit line BL in the first direction D1. The spacers 120 located inside the dummy bit line DBL are located on the bit line spacer 118, and some residual deposited layer may remain on the surface of the insulating layer 104, connecting adjacent spacers 120. The material of the spacers 120 and 122 can be silicon oxide, silicon nitride, or a combination thereof.

[0061] Please refer to Figure 5 , is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. In addition to the above-mentioned partition wall configuration, the present invention may also have other partition wall configurations. Figure 5 As shown, in this embodiment, the trench 105 is not filled with the bitline spacer 118. The spacer 120 located inside the dummy bitline DBL and on both sides of the bitline BL may also be a multi-layer structure, including two conformal spacer layers 124 and 126, which are distributed along the sidewalls inside the dummy bitline DBL and on both sides of the bitline BL, the trench 105, and the surface of the insulating layer 104. The spacer 122 located outside the dummy bitline DBL is a single-layer structure. In other embodiments, the spacer layer 126 may completely fill the trench 105. The material of the spacer layers 124 and 126 may be silicon oxide or silicon nitride, respectively. In this embodiment, the spacer walls 122 on both sides of the dummy bitline DBL are not at the same height as the bottom surfaces of the spacer layers 124 and 126, and the width of the spacer walls 122 in the first direction D1 is also greater than the width of the spacer layers 124 and 126.

[0062] Please refer to Figure 6 , is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. In addition to the above two aspects, the present invention may also have other partition wall aspects. Figure 6 In the embodiment, the original trench 105 is not filled with the bitline spacer 118. Instead, a spacer layer 128 is formed inside the dummy bitline DBL and on both sides of the bitline BL. The original trench 105 is then etched using an anisotropic etching process, transforming it into a trench 130 that is deeper than the original recess 103. This approach has the advantage of further improving the isolation between the dummy bitline DBL and the adjacent bitline BL.

[0063] Please refer to Figure 7, which is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention. After the bitline spacers 118 and spacers 120 are formed, a storage node contact structure SC can be formed on the active region 100c between the bitlines BL. This step may include first forming a spacer structure (not shown) between the bitlines BL, then performing an anisotropic etching process using photoresist, these spacers, and the bitlines BL (including the spacers 120 on both sides thereof) as an etch mask to remove the insulating layer 104 between the spacer structure and the bitlines BL, exposing the underlying active region 100c, which serves as the contact region 131 for forming the storage node. This etching step may remove portions of the bitline spacers 118 and active region 100c. It should be noted that areas outside the memory cell region 100a (e.g., areas outside the dummy bitlines DBL) are protected by the photoresist and will not be etched. After the contact region 131 is formed, a storage node contact structure SC is formed on the contact region 131. As shown in the figure, the structure may include, in sequence, a polysilicon layer 132, a silicide layer 134, a barrier layer 136, and a metal layer 138. The polysilicon layer 132 may be doped polysilicon and directly contacts the exposed contact region 131 on the substrate. The silicide layer 134 may include titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, and / or molybdenum silicide. The metal layer 138 may be a metal such as tungsten, aluminum, titanium, or tantalum. The barrier layer 136 may include a nitride of a metal such as tungsten, aluminum, titanium, or tantalum. After the storage node contact structure SC is formed, a contact isolation structure is formed above the storage node contact structure SC to connect to charge storage components such as capacitors. However, these components are not the focus of this invention and, for the sake of simplicity, will not be shown in subsequent figures.

[0064] Please refer to Figure 8 , is a cross-sectional schematic diagram of a semiconductor structure according to a preferred embodiment of the present invention. The structure of this embodiment is similar to Figure 7 Similar, but different Figure 8 It is a continuation Figure 6The structure forms a storage node contact structure SC on the active region 100c between the bit lines BL. As can be seen from the figure, the depth of the trench 130 inside the dummy bit line DBL is lower than the depth of the recess 103 where the dummy bit line DBL is located, and lower than the depth of the trench 105 where the bit line BL is located. Bit line spacers 118 and 119 are formed in both trench 130 and trench 105. It should be noted that in this embodiment, because trench 130 is lower, the top surface of the bit line spacer 118 in trench 130 is lower than the top surface of the bit line spacer 119 in trench 105. The bit line spacers 118 and 119 can be formed of an insulating material having an etching selectivity with respect to the insulating layer 104, such as silicon oxide, silicon nitride, silicon oxynitride, or a multi-layer structure composed of a combination thereof. After the bit line spacers 118 and 119 are formed, another spacer 120 is formed on both sides of the bit line BL and the dummy bit line DBL. The material of the spacer 120 can be silicon oxide, silicon nitride, or a multi-layer structure composed of a combination thereof. Because the top surface of the bit line spacer 118 is relatively low, the bottom surfaces of the spacers 120 and 122 on both sides of the dummy bit line are not at the same height. Because a spacer layer 128 is also formed on the inner side wall of the dummy bit line DBL and the surface of the groove 130, the spacer layer 128 and the spacer 120 are a multi-layer spacer structure as a whole, while the spacer 122 located outside the dummy bit line DBL is a single-layer structure. Afterwards, the following steps are performed: Figure 7 The storage node contact structure SC process described above forms the storage node contact structure SC on the active region 100c between the bit line BL and the dummy bit line DBL. The advantage of this embodiment is that the deeper trench 130 can further improve the isolation between the dummy bit line DBL and the adjacent bit line BL.

[0065] Please refer to Figure 9 , which is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. The structure of this embodiment is similar to Figure 8 Similar, but different Figure 9 The bit line spacer 118 in the trench 130 does not completely fill the trench 130, but is conformally formed in the trench 130, with a portion of the spacer 120 extending into the bit line spacer 118. Similarly, in this embodiment, the highest top surface of the bit line spacer 118 in the trench 130 is lower than the top surface of the bit line spacer 119 in the trench 105.

[0066] Please refer to Figure 10 , which is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. The structure of this embodiment is similar to Figure 8 Similar, but different Figure 10 No bit line spacer 118 is formed in the trench 130. The spacer 120 formed subsequently directly fills the entire trench 130 along the sidewall of the dummy bit line DBL. Bit line spacers 119 are formed in the trenches 105 on both sides of the bit line BL.

[0067] Finally, please refer to Figure 11 , which is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. The structure of this embodiment is similar to Figure 10 Similar, but different Figure 11 The spacer layer 128 originally formed in parallel on the surface of the trench 130 does not completely cover the surface of the trench 130. Due to anisotropic etching, a portion of the spacer layer 128 located at the bottom of the trench 130 is removed, exposing the active area 100b. As a result, the subsequently formed spacer 120 directly fills the entire trench 130 along the sidewalls of the dummy bit line DBL and directly contacts the exposed active area 100b.

[0068] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that Include: A substrate having a memory cell region defined thereon and further comprising a plurality of recesses and active regions; A plurality of bit lines are arranged at equal intervals along a first direction on the memory cell region and extend in a second direction orthogonal to the first direction; and a dummy bit line located at an outermost side of the bit lines in the first direction and extending toward the second direction; The width of the dummy bit line in the first direction is greater than the width of the bit lines in the first direction, and the bottoms of the dummy bit line are not on the same horizontal plane; These bit lines have the same composition and layer structure as the dummy bit line, which includes a contact layer, a conductive layer and a hard mask layer in sequence from the substrate upward. The contact layer of the bit line is located in one of the grooves and is electrically connected to one of the active areas through the groove and forms a first trench with the sidewall of the groove. The contact layer of a portion of the dummy bit line is located in one of the grooves and is electrically connected to one of the active areas and forms a second trench with the sidewall of the groove, wherein the depth of the second trench is lower than the depth of the first trench.

2. The semiconductor structure according to claim 1, wherein The depth of the first trench is the same as the depth of the groove.

3. The semiconductor structure according to claim 1, wherein: A conformal spacer layer is formed on the sidewalls on both sides of the bit lines, the inner sidewall of the dummy bit line, the surface of the first trench and the surface of the second trench, and further includes spacers formed on the sidewalls on both sides of the bit lines and the dummy bit line.

4. The semiconductor structure according to claim 3, wherein: The spacer on the inner sidewall of the dummy bit line passes through the spacer layer and directly contacts the active region of the substrate below.

5. The semiconductor structure according to claim 1, wherein The first trench is filled with a first bit line spacer, the second trench is filled with a second bit line spacer, and further includes spacers formed on the sidewalls of the bit lines, the sidewalls of the dummy bit line, the first bit line spacer, and the second bit line spacer.

6. The semiconductor structure according to claim 5, wherein: A top surface of the second bit line spacer is lower than a top surface of the first bit line spacer.

7. The semiconductor structure according to claim 5, wherein: The second bit line spacer is conformally formed on the surface of the second trench, and a portion of the spacer wall extends into the second bit line spacer.

8. The semiconductor structure according to claim 5, wherein: The width of the partition wall located outside the dummy bit line in the first direction is greater than the width of the partition wall located inside the dummy bit line in the first direction and greater than the width of the partition walls of the bit lines in the first direction.

9. The semiconductor structure according to claim 5, wherein: The bottom surfaces of the partition walls on both sides of the dummy bit line are not at the same height.

10. The semiconductor structure according to claim 5, wherein: The partition wall located outside the dummy bit line is a single-layer partition wall structure, and the partition wall located inside the dummy bit line is a multi-layer partition wall structure.

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