Integrated chip and method for forming an integrated chip

Abstract

The present disclosure relates to an integrated chip including a substrate. A photodetector is disposed within the substrate. A trench isolation structure extends into the substrate on opposite sides of the photodetector. The trench isolation structure separates the photodetector from an adjacent photodetector. A first passivation layer is located between a sidewall of the substrate and a sidewall of the trench isolation structure. The first passivation layer includes hydrogenated amorphous silicon.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to an integrated chip and a method for forming an integrated chip. BACKGROUND

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras and cell phones. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have begun to be widely used, largely replacing charge-coupled device (CCD) image sensors. CMOS image sensors are favored over CCD image sensors due to low power consumption, small size, fast data processing, direct output of data, and low manufacturing cost. Some types of CMOS image sensors include frontside illuminated (FSI) image sensors and backside illuminated (BSI) image sensors. SUMMARY

[0003] In some embodiments, the present disclosure relates to an integrated chip comprising a substrate, a photodetector, a trench isolation structure, and a first passivation layer. The photodetector is disposed within the substrate. The trench isolation structure extends into the substrate on opposite sides of the photodetector. The trench isolation structure separates the photodetector from an adjacent photodetector. The first passivation layer is between a sidewall of the substrate and a sidewall of the trench isolation structure. The first passivation layer comprises hydrogenated amorphous silicon.

[0004] In other embodiments, the present disclosure relates to an integrated chip comprising a substrate, a first semiconductor well, a trench isolation structure, and a passivation structure. The first semiconductor well is within the substrate. The first semiconductor well forms a photodetector within the substrate. The trench isolation structure extends into the first semiconductor well on opposite sides of the photodetector. The trench isolation structure separates the photodetector from an adjacent photodetector. The passivation structure is between the first semiconductor well and the trench isolation structure. The first semiconductor well is on a sidewall of the passivation structure. The passivation structure is on a sidewall of the trench isolation structure. The passivation structure comprises hydrogenated amorphous silicon.

[0005] In yet other embodiments, the present disclosure is directed to a method for forming an integrated chip. The method includes forming a photodetector in a substrate. The substrate is patterned to form a trench in the substrate. The trench is formed by sidewalls of the substrate, and the trench encloses the photodetector. A first passivation layer is deposited on the sidewalls of the substrate forming the trench. The first passivation layer includes hydrogenated amorphous silicon. A dielectric layer is deposited over the first passivation layer and in a remaining portion of the trench to form a trench isolation structure over the first passivation layer and around the photodetector. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is to be noted, however, that the various features illustrated in the drawings are not necessarily drawn to scale. Rather, the dimensions of the various features can be arbitrarily expanded or reduced for the clarity of discussion.

[0007] Figure 1A Cross-sectional views of some embodiments of an image sensor including passivation structures extending along a substrate on opposite sides of a photodetector are shown.

[0008] Figure 1B Cross-sectional views of some embodiments of an image sensor of Figure 1A wherein a first semiconductor well and a second semiconductor well are within a substrate.

[0009] Figure 2 Top views of some embodiments of an image sensor of Figure 1B

[0010] Figure 3 Cross-sectional views of some embodiments of an image sensor of Figure 1B wherein a passivation structure includes a first passivation layer.

[0011] Figure 4 Cross-sectional views of some embodiments of an image sensor of Figure 1B wherein a passivation structure includes a first passivation layer and a second passivation layer.

[0012] Figure 5 Cross-sectional views of some embodiments of an image sensor of Figure 1B wherein a passivation structure includes a first passivation layer, a second passivation layer, and a third passivation layer.

[0013] Figure 6 Band diagrams of some embodiments showing an interface between a substrate and a passivation structure are shown.

[0014] Figure 7 Cross-sectional views of some embodiments of an image sensor of Figure 1B wherein a passivation structure extends over a photodetector.

[0015] Figure 8 Cross-sectional views of some embodiments of an image sensor of​Figure 1B Cross-sectional view of some embodiments of an image sensor of FIG. 1, where the passivation structure extends into the second semiconductor well of the substrate.

[0016] Figure 9 Cross-sectional view of some embodiments of an image sensor of FIG. 1, where the dielectric layer extends over the photodetector. Figure 1B Cross-sectional view of some embodiments of an image sensor of FIG. 1, where the second semiconductor well extends through the substrate along the sidewall of the passivation structure.

[0017] Figure 10 Cross-sectional view of some embodiments of a method for forming an image sensor of FIG. 1, the image sensor including a passivation structure extending along the substrate on opposite sides of a photodetector. Figure 1B Cross-sectional view of some alternative embodiments of a method for forming an image sensor of FIG. 1, the image sensor including a passivation structure extending along the substrate on opposite sides of a photodetector.

[0018] Figures 11 to 21 Flowchart illustrating some embodiments of a method for forming an image sensor of FIG. 1, the image sensor including a passivation structure extending along the substrate on opposite sides of a photodetector.

[0019] Figures 22 to 27 Flowchart illustrating some alternative embodiments of a method for forming an image sensor of FIG. 1, the image sensor including a passivation structure extending along the substrate on opposite sides of a photodetector.

[0020] Figure 28 Flowchart illustrating some embodiments of a method for forming an image sensor of FIG. 1, the image sensor including a passivation structure extending along the substrate on opposite sides of a photodetector.

[0021] BRIEF DESCRIPTION OF THE DRAWINGS

[0022] 100a, 100b, 300, 400, 500, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700a, 1700b, 1700c, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700: cross-sectional view;

[0023] 101: substrate;

[0024] 101b: backside;

[0025] 101f: frontside;

[0026] 101s, 122s: sidewall;

[0027] 101u: upper surface;

[0028] 102: pixel;

[0029] 102n: neighboring pixel;

[0030] 103: interface;

[0031] 104a: first region;

[0032] 104b: second region;

[0033] 106: photodetector;

[0034] 106n: neighboring photodetector;

[0035] 108: first semiconductor well;

[0036] 110: second semiconductor well;

[0037] 110t: top portion;

[0038] 112: transfer gate;

[0039] 114: interconnect structure;

[0040] 116: dielectric structure;

[0041] 118: carrier wafer;

[0042] 120: passivation structure;

[0043] 120s: opposing sidewall;

[0044] 122: trench isolation structure;

[0045] 122x: lower surface;

[0046] 124: color filter;

[0047] 126: lens;

[0048] 200: top view;

[0049] 302: first passivation layer;

[0050] second passivation layer: 402;

[0051] third passivation layer: 502;

[0052] 600: band diagram;

[0053] 902: dielectric layer;

[0054] 1202, 1602, 2302: photoresist mask;

[0055] 1604, 2304: trench;

[0056] 2800: method;

[0057] 2802, 2804, 2806, 2806a, 2806b, 2806c, 2808: step;

[0058] A-A': line. DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, a first feature is formed over or on a second feature can include embodiments in which the first feature is formed directly on the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature is not formed directly on the second feature. Also, the present disclosure can repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0060] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0061] Some image sensors include a plurality of pixels along a substrate that are separated by deep trench isolation (DTI) structures. For example, an image sensor includes pixels along a substrate. A pixel includes a photodetector in the substrate. The photodetector is separated from an adjacent photodetector of an adjacent pixel by a DTI structure that extends into the substrate on an opposite side of the photodetector. A sidewall of the DTI structure extends along a sidewall of the substrate and faces the photodetector.

[0062] In some cases, photo-generated electron and hole recombination along the surface of the substrate (e.g., sidewalls, upper surfaces, lower surfaces, etc.) can be high due to some defects (e.g., etch damage, dangling bonds, interface traps, etc.) that can exist along the surface. In some cases, when photo-generated electrons and holes recombine along the surface of the substrate (e.g., near the sidewalls of the substrate that extend along the DTI), the performance of the image sensor (e.g., white pixel performance) can decrease. Accordingly, some image sensors include an aluminum oxide passivation layer along the substrate to passivate the substrate. For example, some image sensors include an aluminum oxide passivation layer along the sidewalls of the substrate to passivate the sidewalls of the substrate. In some image sensors, the aluminum oxide passivation layer is disposed on the sidewalls of the substrate and separates the sidewalls of the substrate from the sidewalls of the DTI. Because aluminum oxide has a negative fixed charge, the aluminum oxide passivation layer forms an electron barrier along the sidewalls of the substrate. The electron barrier can repel photo-generated electrons from the sidewalls and, thus, can reduce recombination along the sidewalls of the substrate. Accordingly, the performance of the image sensor can be improved.

[0063] However, one challenge with these image sensors is that the aluminum oxide passivation layer can not provide sufficient passivation along the sidewalls of the substrate. For example, if the substrate has an n-type doping along the interface between the substrate and the aluminum oxide passivation layer, the height of the electron barrier created by the aluminum oxide passivation layer at the interface can decrease. Accordingly, the ability of the aluminum oxide passivation layer to prevent photo-generated electrons from recombining near the interface can decrease. Thus, the performance of the image sensor can decrease. In some cases, some image sensors can include a p-type semiconductor well that extends along the aluminum oxide passivation layer between the passivation layer and the n-type substrate to increase the height of the electron barrier forced by the aluminum oxide passivation layer at the interface with the p-type well. However, the p-type well can decrease the full well capacity (FWC) of the photodetector. Accordingly, the performance of the image sensor can decrease.

[0064] Another challenge with image sensors is that the aluminum oxide passivation layer can utilize high temperature annealing in a hydrogen gas environment to provide hydrogen ions to the sidewalls of the substrate to passivate dangling bonds that exist along the sidewalls of the substrate and / or to passivate damage caused to the substrate by etching the substrate to form the openings of the DTI. However, for some image sensor fabrication processes, it can not be feasible to subject the image sensor to such high temperatures. For example, in some cases, as the pixel size of the image sensor decreases, the maximum temperature that the image sensor can be subjected to during fabrication can also decrease. Accordingly, for some image sensor fabrication processes, a high temperature anneal for the aluminum oxide passivation layer to passivate dangling bonds and / or damage along the substrate can not be feasible.

[0065] Various embodiments of the present disclosure relate to an image sensor including a substrate and one or more passivation layers along the substrate for improving passivation of the substrate. The image sensor includes a photodetector disposed within the substrate. A trench isolation structure extends into the substrate on opposite sides of the photodetector. The trench isolation structure separates the photodetector from an adjacent photodetector. Sidewalls of the trench isolation structure extend along sidewalls of the substrate. A first passivation layer is between the sidewalls of the substrate and the sidewalls of the trench isolation structure. The first passivation layer includes hydrogenated amorphous silicon. The dopant concentration and the hydrogen concentration of the hydrogenated amorphous silicon can be controlled when depositing the first passivation layer.

[0066] Because the dopant concentration of the hydrogenated amorphous silicon can be controlled, the height of the electronic barrier generated by the first passivation layer along the sidewalls of the substrate can be controlled (e.g., increased). Thus, recombination of photo-generated electrons and holes along the sidewalls can be reduced, and thus the performance of the image sensor (e.g., white pixel performance) can be improved.

[0067] Furthermore, because the hydrogen concentration of the hydrogenated amorphous silicon can be controlled, the first passivation layer can be able to provide more hydrogen ions to the sidewalls of the substrate to passivate defects (e.g., dangling bonds, interface traps, etch damage, etc.) along the sidewalls of the substrate. Thus, the performance of the image sensor can be further improved. Furthermore, because the hydrogen concentration of the hydrogenated amorphous silicon can be controlled, high-temperature annealing can not be needed to provide hydrogen ions to the sidewalls of the substrate to passivate defects along the sidewalls of the substrate. Thus, some image sensors for which the first passivation layer has limited thermal requirements for its fabrication process can have improved viability.

[0068] Figure 1A A cross-sectional view 100a showing some embodiments of an image sensor including a passivation structure 120 extending along the substrate 101 on opposite sides of the photodetector 106.

[0069] The image sensor includes a pixel 102 along the substrate 101. The pixel 102 includes a photodetector 106 disposed within the substrate 101. An interconnect structure 114 is within a dielectric structure 116 along a front side 101f of the substrate 101. A color filter 124 and a lens 126 (e.g., a microlens) extend along a back side 101b of the substrate 101 opposite the front side 101f. Photons can enter the pixel 102 through the lens 126 and the color filter 124.

[0070] A trench isolation structure 122 extends into the substrate 101 from the back side 101b of the substrate 101. The trench isolation structure 122 is on opposite sides of the photodetector 106 and separates the photodetector 106 from an adjacent photodetector 106n of an adjacent pixel 102n along a boundary of the pixel 102. The trench isolation structure 122 can optically isolate the pixel 102 from the adjacent pixel 102n. Sidewalls 122s of the trench isolation structure 122 extend along sidewalls 101s of the substrate 101.

[0071] The passivation structure 120 extends between and separates the trench isolation structure 122 and the substrate 101. For example, the passivation structure 120 extends between a sidewall 122s of the trench isolation structure 122 and a sidewall 101s of the substrate 101. In some embodiments, the passivation structure 120 is on the sidewall 122s of the trench isolation structure 122 and on the sidewall 101s of the substrate 101. In some embodiments, the passivation structure 120 also extends between a lower surface 122x of the trench isolation structure 122 and an upper surface 101u of the substrate 101. The passivation structure 120 abuts the substrate 101 along the interface 103. The passivation structure passivates the substrate 101 along the interface 103. For example, the passivation structure 120 passivates the sidewall 101s of the substrate 101. The passivation structure 120 includes one or more passivation layers. At least one of the one or more passivation layers of the passivation structure 120 includes hydrogenated amorphous silicon.

[0072] The hydrogenated amorphous silicon is doped. For example, the hydrogenated amorphous silicon has a p-type doping and the substrate 101 has an n-type doping. Thus, the hydrogenated amorphous silicon forms an electron barrier along the interface 103 between the passivation structure 120 and the substrate 101 to passivate the substrate 101. For example, the electron barrier can repel photo-generated electrons from the interface 103. Thus, recombination of photo-generated electrons and holes along the interface 103 can be reduced, and thus performance of the image sensor (e.g., white pixel performance) can be improved. Furthermore, the dopant concentration of the hydrogenated amorphous silicon can be controlled when forming the passivation structure 120. Because the dopant concentration of the hydrogenated amorphous silicon can be controlled, the height of the electron barrier created by the passivation structure 120 along the interface 103 can be controlled (e.g., increased). Thus, passivation of the substrate can be further improved, and thus performance of the image sensor can be further improved.

[0073] Additionally, hydrogen ions from the hydrogenated amorphous silicon can passivate defects (e.g., interface traps, dangling bonds, etch damage, etc.) along the interface 103 to further passivate the substrate 101. Thus, recombination of photo-generated electrons and holes along the interface 103 can be further reduced, and thus performance of the image sensor (e.g., white pixel performance) can be further improved. Furthermore, the hydrogen concentration of the hydrogenated amorphous silicon can be controlled when forming the passivation structure 120. Because the hydrogen concentration of the hydrogenated amorphous silicon can be controlled, the passivation structure 120 can be able to provide more hydrogen ions to the interface 103 to passivate any defects that can exist along the interface 103. Thus, performance of the image sensor can be further improved.

[0074] Furthermore, because the hydrogen concentration of the hydrogenated amorphous silicon can be controlled, hydrogen ions can not be provided to the interface 103 with high temperature annealing to passivate the substrate 101. Thus, the passivation structure 120 can have improved viability for some image sensor technologies that require a manufacturing process with limited thermal exposure.

[0075] In some embodiments, the substrate 101 comprises crystalline silicon or some other suitable semiconductor material. In some embodiments, the substrate 101 has an n-type doping, and one or more of the one or more passivation layers of the passivation structure 120 has a p-type doping. In some other embodiments, the substrate 101 has a p-type doping, and one or more of the one or more passivation layers of the passivation structure 120 has a heavily doped p-type doping (e.g., p+ doping).

[0076] In some embodiments, the trench isolation structure 122 comprises silicon dioxide, silicon nitride, or the like. Although the trench isolation structure 122 is shown in Figure 1A as not extending completely through the substrate 101, it should be appreciated that, in some alternative embodiments (not shown), the trench isolation structure 122 can instead extend through the substrate 101 (e.g., from the backside 101b to the frontside 101f) to the dielectric structure 116.

[0077] In some embodiments, the photodetector 106 can be or comprise, for example, a photodiode, a breakdown photodiode, a single-photon avalanche diode (SPAD), or some other suitable photodetector.

[0078] In some embodiments, the interconnect structure 114 can comprise, for example, metals or vias, and metal or conductive lines, bond pads, some other suitable interconnects, some capacitor devices, some logic devices, or the like. In some embodiments, the dielectric structure 116 can comprise, for example, one or more dielectric layers, one or more etch stop layers, or the like.

[0079] Although the image sensor shown in Figure 1A is backside illuminated (BSI), it should be appreciated that, in some alternative embodiments (not shown), the image sensor can instead be frontside illuminated (FSI). In some embodiments, the image sensor can be included in an integrated chip.

[0080] Figure 1B A cross-sectional view 100b of some embodiments of the image sensor of Figure 1A is shown, in which the first semiconductor well 108 and the second semiconductor well 110 are within the substrate 101. Figure 1B The cross-sectional view 100b of can be taken, for example, along the line A-A' of Figure 2 .

[0081] A first semiconductor well 108 of substrate 101 is disposed between a first region 104a and a second region 104b of substrate 101. The first semiconductor well 108 extends continuously between opposing sidewalls 120s of passivation structure 120. For example, the first semiconductor well 108 extends continuously from the first sidewall of passivation structure to the second sidewall opposite to the first sidewall of passivation structure 120. In some embodiments, the sidewalls 101s of substrate 101 (e.g., the sidewalls of the first semiconductor well 108 and the sidewalls of the second region 104b of substrate 101) are on the sidewalls 120s of passivation structure 120.

[0082] A second semiconductor well 110 of substrate 101 is disposed directly below trench isolation structure 122 and passivation structure 120. The second semiconductor well 110 is disposed along the boundary of pixel 102 and electrically isolates pixel 102 from adjacent pixels 102n. In some embodiments, the top of the second semiconductor well 110 is adjacent to the bottom of the first semiconductor well 108. In some embodiments, the passivation structure 120 is on top of the second semiconductor well 110. In some other embodiments (not shown), a first region 104a of substrate 101 may extend between the passivation structure 120 and the top of the second semiconductor well 110. In some embodiments, the second semiconductor well 110 extends along the front side 101f of substrate 101 (e.g., along dielectric structure 116).

[0083] A first region 104a of substrate 101 is directly below the first semiconductor well 108 and extends between a first segment and a second segment of the second semiconductor well 110. A second region 104b of substrate 101 is directly above the first semiconductor well 108 and extends between the sidewalls 120s of passivation structure 120. For example, the second region 104b extends continuously from the first sidewall of the passivation structure to the second sidewall opposite to the first sidewall of the passivation structure 120.

[0084] The first semiconductor well 108 and the second semiconductor well 110 are doped regions of the substrate 101 (e.g., doped regions of a crystalline silicon substrate). For example, the first semiconductor well 108 may have a first doping type (e.g., n-type), the second semiconductor well 110 may have a second doping type opposite to the first doping type (e.g., p-type), the first region 104a of the substrate 101 may have a second doping type (e.g., p-type), and the second region 104b of the substrate 101 may have a second doping type (e.g., p-type), or vice versa. In some embodiments, in addition to controlling the dopant concentration of the hydrogenated amorphous silicon of the passivation structure 120, the dopant concentration of the first semiconductor well 108 may also be controlled. Therefore, the height of the electronic barrier formed at the interface between the passivation structure 120 and the first semiconductor well 108 can be further increased, and thus the performance of the image sensor can be further improved.

[0085] In some embodiments, the first semiconductor well 108, the first region 104a of the substrate 101, and the second region 104b of the substrate 101 form a photodetector 106. For example, the first semiconductor well 108 and the second region 104b of the substrate 101 may form a photodiode (e.g., a pn junction) along the back side 101b of the substrate 101. Alternatively, the first semiconductor well 108 and the first region 104a of the substrate 101 may form a photodiode (e.g., a pn junction) along the front side 101f of the substrate 101.

[0086] In some embodiments, the transfer gate 112 extends from the front side 101f of the substrate 101 into the substrate 101. For example, the transfer gate 112 extends from within the dielectric structure 116 through a first region 104a of the substrate 101 and into a first semiconductor well 108. The transfer gate 112 is coupled to the interconnect structure 114. Although Figure 1B The transfer gate 112 is shown extending vertically into the substrate 101; however, it should be understood that in some alternative embodiments, the transfer gate may not extend into the substrate 101 and may instead extend along the front side 101f of the substrate within the dielectric structure 116. In some embodiments, the carrier wafer 118 may be disposed below the interconnect structure 114.

[0087] Figure 2 Show Figure 1B Top view 200 of some embodiments of the image sensor.

[0088] The trench isolation structure 122 surrounds the photodetector 106 along the boundary of pixel 102. The trench isolation structure 122 may also surround multiple other pixels and may have a grid-like top layout. A passivation structure 120 liner the trench isolation structure 122 and separates the trench isolation structure 122 from the substrate 101 (e.g., the second region 104b of the substrate 101 and / or the first semiconductor well 108 of the substrate 101). Although the second semiconductor well (e.g., Figure 1B 110) is not shown in Figure 2 However, in some embodiments, the second semiconductor well may surround pixel 102 along the boundary of pixel 102. Furthermore, in some embodiments, the second semiconductor well may also surround multiple other pixels and may also have a grid-like layout (e.g., a grid-like layout similar to trench isolation structure 122).

[0089] Figure 3 Show Figure 1B A cross-sectional view 300 of some embodiments of the image sensor, wherein the passivation structure 120 includes a first passivation layer 302.

[0090] The first passivation layer 302 is located between the sidewall of the substrate 101 and the sidewall of the trench isolation structure 122. In some embodiments, the first passivation layer 302 is on the sidewall of the substrate 101 (e.g., the side of the first semiconductor well 108 and the side of the second region 104b of the substrate 101) (e.g., in contact with the sidewall of the substrate 101). In other words, the first semiconductor well 108 and the second region 104b of the substrate 101 are on the sidewall of the first passivation layer 302. In some embodiments, the first passivation layer 302 is on the sidewall of the trench isolation structure 122. In some embodiments, the first passivation layer 302 is on the upper surface of the substrate 101 (e.g., the top of the second semiconductor well 110) and on the lower surface of the trench isolation structure 122.

[0091] The first passivation layer comprises hydrogenated amorphous silicon. In some embodiments, the first passivation layer 302 is p-type doped. For example, in some embodiments where the first semiconductor well 108 is n-type doped, the first passivation layer 302 is p-type doped. Furthermore, in some embodiments where the first semiconductor well 108 is p-type doped, the first passivation layer 302 is heavily doped with p-type dopant (e.g., p+ dopant). In other words, in embodiments where both the first semiconductor well 108 and the first passivation layer 302 are p-type doped, the p-type dopant concentration of the first passivation layer 302 is greater than the p-type dopant concentration of the first semiconductor well 108.

[0092] The dopant concentration (e.g., p-type dopant concentration) of the hydrogenated amorphous silicon in the first passivation layer 302 can be controlled. In some embodiments, the dopant concentration of the hydrogenated amorphous silicon in the first passivation layer 302 is between 10... 14per cubic centimeter and 10 21 Between per cubic centimeter. In some embodiments, the hydrogenated amorphous silicon of the first passivation layer 302 may be doped with boron, aluminum, gallium, some other suitable dopant, or a combination thereof.

[0093] Furthermore, the hydrogen concentration of the hydrogenated amorphous silicon in the first passivation layer 302 can be controlled. In some embodiments, the hydrogen concentration of the hydrogenated amorphous silicon in the first passivation layer 302 is between 4% and 35%. In some embodiments, the thickness of the first passivation layer 302 can be from 1 angstrom to 50 nanometers, from 5 nanometers to 50 nanometers, or some other suitable thickness.

[0094] Figure 4 Show Figure 1B A cross-sectional view 400 of some embodiments of the image sensor, wherein the passivation structure 120 includes a first passivation layer 302 and a second passivation layer 402.

[0095] The second passivation layer 402 is above the first passivation layer 302. The second passivation layer 402 is between the first passivation layer 302 and the trench isolation structure 122, and the first passivation layer 302 is between the second passivation layer 402 and the first semiconductor well 108 of the substrate 101. In some embodiments, the second passivation layer 402 is on the sidewall of the first passivation layer 302, on the upper surface of the first passivation layer 302, on the lower surface of the trench isolation structure 122, and on the sidewall of the trench isolation structure 122.

[0096] In some embodiments, the first passivation layer 302 comprises undoped hydrogenated amorphous silicon (e.g., intrinsic hydrogenated amorphous silicon), and the second passivation layer 402 comprises p-type hydrogenated amorphous silicon. In some embodiments where the first semiconductor well 108 has p-type doping, the first passivation layer 302 is undoped, and the second passivation layer has heavily doped p-type doping (e.g., p+ doping). In other words, in embodiments where the first semiconductor well 108 has p-type doping, the p-type dopant concentration of the second passivation layer 402 is greater than the p-type dopant concentration of the first semiconductor well 108.

[0097] In some cases, the first passivation layer 302 is undoped because intrinsic hydrogenated amorphous silicon can passivate the substrate 101 better than doped intrinsic hydrogenated amorphous silicon. For example, in some cases, intrinsic hydrogenated amorphous silicon can reduce interface defects along the substrate 101 to a greater extent than doped hydrogenated amorphous silicon.

[0098] The dopant concentration (e.g., p-type dopant concentration) of the hydrogenated amorphous silicon in the second passivation layer 402 can be controlled. In some embodiments, the dopant concentration of the hydrogenated amorphous silicon in the second passivation layer 402 is 10. 14per cubic centimeter and 10 21 Between per cubic centimeter. In some embodiments, the hydrogenated amorphous silicon of the second passivation layer 402 may be doped with boron, aluminum, gallium, some other suitable dopant, or a combination thereof.

[0099] Furthermore, the hydrogen concentration of the hydrogenated amorphous silicon in the second passivation layer 402 can be controlled. In some embodiments, the hydrogen concentration of the hydrogenated amorphous silicon in the second passivation layer 402 is between 4% and 35%. In some embodiments, the hydrogen concentration of the second passivation layer 402 may differ from the hydrogen concentration of the first passivation layer 302. In some embodiments, the thickness of the second passivation layer 402 may be from 1 angstrom to 50 nanometers, from 5 nanometers to 50 nanometers, or some other suitable thickness.

[0100] In some alternative embodiments, the first passivation layer 302 comprises p-type hydrogenated amorphous silicon and the second passivation layer 402 comprises aluminum oxide. In some cases, because aluminum oxide has a relatively high density, it may help prevent hydrogen from escaping from the first passivation layer 302, thereby improving the passivation capability of the first passivation layer 302. Furthermore, in some cases, because aluminum oxide has a fixed negative charge, it can further increase the height of the electronic barrier along the interface between the substrate 101 and the passivation structure 120, thereby improving the passivation of the substrate 101. In some embodiments, a native oxide layer (not shown) comprising silicon dioxide may be present between the hydrogenated amorphous silicon of the first passivation layer 302 and the aluminum oxide of the second passivation layer 402.

[0101] Figure 5 Show Figure 1B A cross-sectional view 500 of some embodiments of the image sensor, wherein the passivation structure 120 includes a first passivation layer 302, a second passivation layer 402 and a third passivation layer 502.

[0102] The third passivation layer 502 is above the second passivation layer 402. The third passivation layer 502 is between the second passivation layer 402 and the trench isolation structure 122, the second passivation layer 402 is between the first passivation layer 302 and the third passivation layer 502, and the first passivation layer 302 is between the second passivation layer 402 and the first semiconductor well 108 of the substrate 101. In some embodiments, the third passivation layer 502 is on the sidewall of the second passivation layer 402, on the upper surface of the second passivation layer 402, on the lower surface of the trench isolation structure 122, and on the sidewall of the trench isolation structure 122.

[0103] The first passivation layer 302 and the second passivation layer 402 both comprise hydrogenated amorphous silicon, and the third passivation layer 502 comprises aluminum oxide. As previously discussed, the inclusion of aluminum oxide in the passivation structure 120 improves the passivation of the substrate 101. In some embodiments, the first passivation layer 302 is undoped (e.g., intrinsic hydrogenated amorphous silicon), and the second passivation layer 402 is p-type doped. In some embodiments, a native oxide layer (not shown) comprising silicon dioxide may be present between the hydrogenated amorphous silicon of the second passivation layer 402 and the aluminum oxide of the third passivation layer 502. In some embodiments, the thickness of the third passivation layer 502 may be from 1 angstrom to 50 nanometers, from 5 nanometers to 50 nanometers, or some other suitable thickness.

[0104] Figure 6 The substrate is shown (e.g., Figure 1A 101 or Figure 1B 108) and passivation structure (e.g., Figure 1A or Figure 1B The interface between 120 and (e.g., Figure 1A Band diagram 600 of some embodiments of (103).

[0105] The passivation structure comprises p-type hydrogenated amorphous silicon and intrinsic hydrogenated amorphous silicon, with the substrate comprising n-type crystalline silicon. The passivation structure forms an electronic barrier at the interface with the substrate. The barrier height is proportional to the dopant concentration of the p-type hydrogenated amorphous silicon in the passivation structure. The electronic barrier corresponds to a built-in electric field that repels photogenerated electrons from the interface. Therefore, recombination of photogenerated electrons and holes along the interface is reduced, thus improving the performance of the image sensor.

[0106] In addition, such as by Figure 6 As illustrated, hydrogen ions from the passivation structure can passivate interface defects or defects near the interface that may exist along the interface. Therefore, the passivation of the interface can be improved, and thus the performance of the image sensor can be improved.

[0107] Figure 7 Show Figure 1B A cross-sectional view 700 of some embodiments of the image sensor shows a passivation structure 120 extending above a photodetector 106.

[0108] A passivation structure 120 (e.g., a first passivation layer 302 of the passivation structure 120) extends on and along the back side 101b of the substrate 101 above the photodetector 106. Therefore, the passivation structure 120 passivates the back side 101b of the substrate 101, thereby improving the performance of the image sensor. In some embodiments, the thickness of the passivation structure 120 along the back side 101b of the substrate 101 may be lower. For example, the thickness of the passivation structure 120 along the back side 101b of the substrate 101 may be lower than the thickness along the sidewall of the first semiconductor well 108 of the substrate 101. Therefore, the passivation structure 120 passivates the back side 101b of the substrate 101 without reflecting incident photons away from the substrate 101 (i.e., without negatively impacting the performance of the image sensor).

[0109] In some embodiments, due to the planarization process performed on the passivation structure 120 (e.g., as by... Figure 20 As shown, the entire passivation structure 120 is not removed from the back side 101b of the substrate 101, which extends along the back side 101b of the substrate 101 and above the photodetector 106.

[0110] Figure 8 Show Figure 1B A cross-sectional view 800 of some embodiments of the image sensor shows a passivation structure 120 extending into a second semiconductor well 110 of a substrate 101.

[0111] The bottom surface 120b of the passivation structure 120 (e.g., the bottom surface of the first passivation layer 302 of the passivation structure 120) is below the top 110t of the second semiconductor well 110, and the second semiconductor well 110 extends along the sidewall of the passivation structure 120. In some embodiments, due to the formation of trenches in the substrate 101 extending into the second semiconductor well 110 (e.g., Figure 16 1604 or Figure 23 The 2304) is etched and, due to the subsequent formation of a passivation structure 120 in the trench, the passivation structure 120 extends into the second semiconductor well 110.

[0112] Figure 9 Show Figure 1B A cross-sectional view 900 of some embodiments of the image sensor, wherein a dielectric layer 902 extends above a photodetector 106.

[0113] The dielectric layer 902 extends on and along the back side 101b of the substrate 101 above the photodetector 106. The dielectric layer 902 extends continuously between the sidewalls of the passivation structure 120. In some embodiments, the dielectric layer 902 may comprise, for example, silicon dioxide, silicon nitride, or some other suitable dielectric. In some embodiments, due to a planarization process performed on the dielectric layer 902 (e.g., as by…), Figure 26 (As shown) The entire dielectric layer 902 is not removed from the back side 101b of the substrate 101, which extends along the back side 101b of the substrate 101 above the photodetector 106.

[0114] Figure 10 Show Figure 1B A cross-sectional view 1000 of some embodiments of the image sensor shows a second semiconductor well 110 extending along the sidewall of the passivation structure 120 through the substrate 101.

[0115] The second semiconductor well 110 of substrate 101 separates the passivation structure 120 from the first semiconductor well 108. In some embodiments where the second semiconductor well 110 has p-type doping, the passivation layer of the passivation structure 120 (e.g., Figure 3 The first passivation layer 302 or Figure 4 or Figure 5 The second passivation layer in the second semiconductor well 120 has heavily doped p-type dopant (e.g., p+ dopant). In other words, in an embodiment where the second semiconductor well 108 has p-type dopant, the p-type dopant concentration of the passivation layer of the passivation structure 120 is greater than that of the second semiconductor well 110.

[0116] Figures 11 to 21 Cross-sectional views 1100 to 2100 illustrate some embodiments of a method for forming an image sensor, the image sensor including a passivation structure extending along a substrate on opposite sides of a photodetector. Although relative to the method description... Figures 11 to 21 However, it should be understood that Figures 11 to 21 The structures disclosed herein are not limited to this method, but can instead be used as independent structures separate from the method.

[0117] like Figure 11As illustrated in cross-sectional view 1100, a first semiconductor well 108 is formed within a substrate 101. In some embodiments, forming the first semiconductor well 108 in the substrate 101 forms a photodetector 106 in the substrate 101. In some embodiments, the first semiconductor well 108 may be formed, for example, by performing a first ion implantation process or some other suitable process along the front side 101f of the substrate 101. In some embodiments, the number of masks used to form the image sensor can be reduced by performing a blanket implantation process in situ without a mask (e.g., a photoresist mask).

[0118] As in Figure 12 As illustrated in cross-sectional view 1200, a photoresist mask 1202 is formed over the front side 101f of substrate 101. A second semiconductor well 110 is then formed within substrate 101 along the front side 101f of substrate 101 based on the photoresist mask 1202. In some embodiments, the second semiconductor well 110 may be formed, for example, by performing a second ion implantation process or some other suitable process along the front side 101f of substrate 101. In some embodiments, the photoresist mask 1202 may be removed after the formation of the second semiconductor well 110.

[0119] like Figure 13 As illustrated in cross-sectional view 1300, a transfer gate 112 is formed along and / or within a substrate 101. Furthermore, a dielectric structure 116 is formed over the substrate 101, and an interconnect structure 114 is formed within the dielectric structure 116. Additionally, a carrier wafer 118 is bonded over the substrate 101. In some embodiments, the transfer gate 112 is formed by patterning the substrate 101 and subsequently depositing a conductive material over the substrate 101. In some other embodiments, the transfer gate 112 is formed by depositing a conductive material over the substrate 101 and subsequently patterning the conductive material. In some embodiments, the dielectric structure 116 is formed by depositing one or more dielectric layers and one or more etch-stop layers over the substrate 101. In some embodiments, the interconnect structure is formed by patterning the dielectric structure 116 and subsequently depositing one or more conductive materials over the dielectric structure 116.

[0120] like Figure 14 As shown in the cross-sectional view 1400, the substrate 101 is rotated such that the back side 101b is above the front side 101f.

[0121] like Figure 15As illustrated in cross-sectional view 1500, the back side 101b of substrate 101 is thinned. For example, the thickness of substrate 101 is reduced by removing a portion of substrate 101 from the back side 101b of substrate 101. In some embodiments, substrate 101 is thinned by etching processes, planarization processes (e.g., chemical mechanical planarization (CMP) processes), polishing processes, some other suitable processes, or any combination thereof.

[0122] As in Figure 16 As illustrated in cross-sectional view 1600, a photoresist mask 1602 is formed over the back side 101b of substrate 101. Substrate 101 is then patterned according to the photoresist mask 1602 to form a trench 1604 in substrate 101. For example, a second region 104b of substrate 101 and a first semiconductor well 108 of substrate 101 are patterned according to the photoresist mask 1602. Trench 1604 is formed by the sidewalls of substrate 101 (e.g., the sides of the second region 104b and the sides of the first semiconductor well 108) and the upper surface of substrate 101 (e.g., the top of the second semiconductor well 110). Trench 1604 separates photodetector 106 from adjacent photodetectors 106n. In some embodiments, patterning may include, for example, a dry etching process or some other suitable process. For example, patterning may include reactive ion etching (RIE), ion beam etching (IBE), or some other suitable process. In some embodiments, the photoresist mask 1602 may be removed after patterning. In some embodiments, patterning may extend into the second semiconductor well 110, and thus the trench 1604 extends into the second semiconductor well 110 below the top of the second semiconductor well (e.g., as shown in the image). Figure 8 as shown in).

[0123] Figure 17A , Figure 17B as well as Figure 17C Cross-sectional views 1700a, 1700b, and 1700c respectively illustrate some embodiments of a method for forming a passivation structure 120 over a substrate and in a trench 1604 (e.g., along the sidewalls and upper surface of the substrate 101 forming the trench 1604). For example, Figure 17A Cross-sectional view 1700a shows a first embodiment of the method for forming the passivation structure 120. Figure 17B Cross-sectional Figure 1700b illustrates a second embodiment of the method for forming the passivation structure 120, and Figure 17C Cross-sectional view 1700c shows a third embodiment of the method for forming the passivation structure 120.

[0124] As in Figure 17A As illustrated in cross-sectional view 1700a, a first passivation layer 302 is conventionally formed over the substrate and in the trench 1604. In some embodiments, forming the first passivation layer 302 includes depositing p-type hydrogenated amorphous silicon or some other suitable material on the substrate 101 using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), and plasma-enhanced ALD (PEALD).

[0125] As in Figure 17B As shown in cross-sectional view 1700b, a first passivation layer 302 is conformally formed over the substrate 101 and the trench 1604, and a second passivation layer 402 is conformally formed over the first passivation layer 302. In some embodiments, forming the first passivation layer 302 includes depositing intrinsic hydrogenated amorphous silicon, p-type hydrogenated amorphous silicon, or some other suitable material over the substrate 101 using CVD, ALD, PECVD, PEALD, or other processes. In some embodiments, forming the second passivation layer 402 includes depositing p-type hydrogenated amorphous silicon, alumina, or some other suitable material over the substrate 101 using CVD, ALD, PECVD, PEALD, or other processes.

[0126] As in Figure 17C As illustrated in cross-sectional view 1700c, a first passivation layer 302 is conformally formed over the substrate 101 and the trench 1604, a second passivation layer 402 is conformally formed over the first passivation layer 302, and a third passivation layer 502 is conformally formed over the second passivation layer 402. In some embodiments, forming the first passivation layer 302 includes depositing intrinsic hydrogenated amorphous silicon or some other suitable material over the substrate 101 using CVD, ALD, PECVD, PEALD, or similar processes. In some embodiments, forming the second passivation layer 402 includes depositing p-type hydrogenated amorphous silicon or some other suitable material over the substrate 101 using CVD, ALD, PECVD, PEALD, or similar processes. In some embodiments, forming the third passivation layer 502 includes depositing alumina or some other suitable material over the substrate 101 using CVD, ALD, PECVD, PEALD, or similar processes.

[0127] exist Figure 17A , Figure 17B as well as Figure 17CIn the embodiments shown, the dopant concentration of the p-type hydrogenated amorphous silicon can be controlled by adjusting the amount of boron, aluminum, gallium, or some other suitable dopant gas used during the deposition of the p-type hydrogenated amorphous silicon. The dopant concentration of the p-type hydrogenated amorphous silicon layer can be approximately 10. 14 per cubic centimeter to 10 21 per cubic centimeter. Furthermore, in Figure 17A , Figure 17B as well as Figure 17C In some embodiments, the hydrogen concentration of the hydrogenated amorphous silicon can be controlled by controlling the amount of hydrogen used during the deposition of the hydrogenated amorphous silicon. In some embodiments, the hydrogen concentration can be further controlled by controlling the temperature of the CVD process, by controlling the plasma power of the PECVD process, and / or by controlling the plasma power of the PEALD process. For example, if a CVD process is used, lowering the CVD process temperature can increase the hydrogen concentration of the hydrogenated amorphous silicon layer. If a PECVD or PEALD process is used, increasing the plasma power of the PECVD or PEALD process can increase the hydrogen concentration of the hydrogenated amorphous silicon layer. The hydrogen concentration of the hydrogenated amorphous silicon layer can be from about 4% to 35%.

[0128] As in Figure 18 As illustrated in cross-sectional view 1800, the passivation structure 120 is annealed. For example, the passivation structure 120 may be heated at a temperature below about 250 degrees Celsius (e.g., in a boiler). Annealing the passivation structure 120 increases the number of hydrogen ions provided to the interface to passivate the interface. For example, annealing the passivation structure 120 may release hydrogen ions from the passivation structure 120, and the released hydrogen ions may passivate defects along the interface (e.g., hydrogen ions may fill interface traps along the interface, thereby passivating the interface).

[0129] As in Figure 19 As shown in the cross-sectional view of Figure 1900, above the substrate 101 and the trench (e.g., Figures 17A to 17C A trench isolation structure 122 is formed in the remaining portion of the substrate 101. In some embodiments, forming the trench isolation structure 122 includes depositing one or more dielectric layers over the substrate 101 and in the remaining portion of the trench using a CVD process, a PECVD process, or some other suitable deposition process. For example, the one or more dielectric layers may include silicon dioxide, silicon nitride, or some other suitable dielectric material.

[0130] although Figure 18 The annealing process is shown to be performed after the formation of the passivation structure 120 and before the formation of the trench isolation structure 122, but it should be understood that in some alternative embodiments, the annealing process may optionally be performed after the formation of the trench isolation structure 122.

[0131] likeFigure 20 As illustrated in cross-sectional view 2000, a portion of the trench isolation structure 122 and a portion of the passivation structure 120 are removed from above the substrate 101 (e.g., from the back side 101b of the substrate 101). Therefore, after removal, the back side 101b of the substrate 101 is not covered. In some embodiments, the portion of the trench isolation structure 122 and the portion of the passivation structure 120 are removed from above the substrate 101 by performing a planarization process (e.g., CMP process), an etching process, some other suitable process, or any combination of the foregoing processes on the trench isolation structure 122 and the passivation structure 120.

[0132] In some embodiments, the passivation structure 120 may not be completely removed from the back side 101b of the substrate 101 so that the passivation structure 120 remains on the back side 101b of the substrate 101 after planarization processes, etching processes, etc. (e.g., as shown in the figure). Figure 7 as shown in).

[0133] As in Figure 21 As shown in the cross-sectional view 2100, a color filter 124 and a lens 126 are formed above the back side 101b of the substrate 101.

[0134] Figures 22 to 27 Cross-sectional views 2200 to 2700 illustrate some alternative embodiments of a method for forming an image sensor, the image sensor including a passivation structure extending along a substrate on opposite sides of a photodetector. Although relative to the method description... Figures 22 to 27 However, it should be understood that Figures 22 to 27 The structures disclosed herein are not limited to this method, but can instead be used as independent structures separate from the method.

[0135] In some embodiments of the method, a first semiconductor well 108 is formed within the substrate 101 (e.g., as per [reference]). Figure 11 As described). A second semiconductor well 110 is formed within the substrate 101 (e.g., as described in relation to...). Figure 12 (As described). A transfer gate 112 is formed along and / or within the substrate 101, a dielectric structure 116 is formed over the substrate 101, an interconnect structure 114 is formed within the dielectric structure 116, and a carrier wafer 118 is bonded over the substrate 101 (e.g., as described). Figure 13 As described). Rotating substrate 101 (e.g., as per [reference]) Figure 14 As described). The back side 101b of the thinned substrate 101 (e.g., as described regarding Figure 15 (As described).

[0136] like Figure 22As shown in cross-sectional view 2200, dielectric layer 902 is formed over substrate 101 along the back side 101b of substrate 101. In some embodiments, dielectric layer 902 is formed by depositing silicon dioxide, silicon nitride, or some other suitable material over substrate 101 using a CVD process, a PECVD process, or some other suitable process.

[0137] As in Figure 23 As illustrated in cross-sectional view 2300, a photoresist mask 2302 is formed over substrate 101. The dielectric layer 902 and substrate 101 (e.g., the second region 104b of substrate 101 and the first semiconductor well 108 of substrate 101) are then patterned according to the photoresist mask 2302 to form trenches 2304 in the dielectric layer 902 and substrate 101. In some embodiments, patterning may include, for example, a dry etching process or some other suitable process. For example, patterning may include a reactive ion etching (RIE) process, an ion beam etching (IBE) process, or some other suitable process. In some embodiments, the photoresist mask 2302 may be removed after patterning.

[0138] like Figure 24 As illustrated in cross-sectional view 2400, a passivation structure 120 is formed on the sidewalls and upper surface of the substrate 101 forming the trench 2304 (e.g., on the sidewalls of the first semiconductor well 108 and on the top of the second semiconductor well 110 of the substrate 101), but not on the dielectric layer 902. For example, the passivation structure 120 is formed by an epitaxial growth deposition process, wherein the passivation structure 120 grows on the sidewalls and upper surface of the substrate 101 forming the trench 2304, but not on the top surface of the dielectric layer 902. In some embodiments, the passivation structure 120 is also grown on the sidewalls of the dielectric layer 902 forming the trench 2304.

[0139] In some embodiments, a first passivation layer of p-type hydrogenated amorphous silicon (e.g., Figure 3 302) is grown on the sidewalls and upper surface of the substrate forming trench 2304. In some alternative embodiments, a first passivation layer of intrinsic hydrogenated amorphous silicon (e.g., Figure 4 302) is grown on the sidewalls and upper surface of the substrate forming trench 2304, and includes a second passivation layer of p-type hydrogenated amorphous silicon (e.g., Figure 4 The 402) is grown on the first passivation layer (e.g., on the sidewalls and upper surface of the first passivation layer). In some alternative embodiments, the first passivation layer includes intrinsically hydrogenated amorphous silicon (e.g., Figure 5 302) is grown on the sidewalls and top surface of the substrate forming trench 2304, including a second passivation layer of p-type hydrogenated amorphous silicon (e.g., Figure 5402) is grown on the first passivation layer (e.g., on the sidewalls and upper surface of the first passivation layer), and a third passivation layer comprising aluminum oxide (e.g., Figure 5 The 502) is grown on the second passivation layer (e.g., on the sidewalls and upper surface of the second passivation layer). In some embodiments, the annealing process is performed after the passivation structure 120 is formed (e.g., as per [reference to...]). Figure 18 (As described).

[0140] like Figure 25 , Figure 26 as well as Figure 27 As shown in cross-sectional views 2500, 2600, and 2700, a trench isolation structure 122 is formed in the remaining portion of the trench 2304 (e.g., as per [reference to...]). Figure 19 (As described). Subsequently, a portion of the trench isolation structure 122 and dielectric layer 902 are removed from above the substrate 101 (e.g., as described in relation to Figure 20 (As described). Subsequently, a color filter 124 and a lens 126 are formed over the substrate 101 (e.g., as described in relation to...). Figure 21 As described. In some embodiments, the dielectric layer 902 is not completely removed from the back side 101b of the substrate 101 so that some of the dielectric layer 902 remains above the substrate 101 after the removal process (e.g., as described). Figure 9 as shown in).

[0141] Figure 28 Flowcharts illustrating some embodiments of a method 2800 for forming an image sensor, the image sensor including a passivated structure extending along a substrate on opposite sides of a photodetector. While method 2800 is shown and described below as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events, in addition to those shown and / or described herein. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed as one or more separate actions and / or stages.

[0142] At position 2802, a photodetector is formed in the substrate. Figure 11 Cross-sectional view 1100 is shown for some embodiments corresponding to box 2802.

[0143] At 2804, the substrate is patterned to form a trench in the substrate that surrounds the photodetector. Figure 16 and Figure 23 Cross-sectional views 1600 and 2300 are shown for some embodiments corresponding to box 2804.

[0144] At 2806, a passivation structure is formed along the trench. For example, at 2806a, a first passivation layer comprising hydrogenated amorphous silicon is deposited on the sidewalls and top surface of the substrate forming the trench. At 2806b, a second passivation layer comprising hydrogenated amorphous silicon is deposited over the first passivation layer. At 2806c, a third passivation layer comprising aluminum oxide is deposited over the second passivation layer. Figure 17A , Figure 17B , Figure 17C as well as Figure 24 Cross-sectional views 1700a, 1700b, 1700c, and 2400 are shown corresponding to some embodiments of blocks 2806, 2806a, 2806b, and 2806c. In some instances, low-temperature annealing (e.g., 250 degrees Celsius or lower) is performed after the passivation structure is formed.

[0145] At 2808, one or more dielectric layers are deposited over the passivation structure to form a trench isolation structure over the passivation structure of the remaining portion of the trench. Figure 19 and Figure 25 Cross-sectional views 1900 and 2500 are shown for some embodiments corresponding to box 2808.

[0146] Therefore, this disclosure relates to image sensors and methods for forming image sensors, said image sensors including a substrate and one or more passivation layers along the substrate to improve the passivation of the substrate.

[0147] Therefore, in some embodiments, this disclosure relates to an integrated chip including a substrate, a photodetector, a trench isolation structure, and a first passivation layer. The photodetector is disposed within the substrate. The trench isolation structure extends into the substrate on opposite sides of the photodetector. The trench isolation structure separates the photodetector from adjacent photodetectors. The first passivation layer is located between a sidewall of the substrate and a sidewall of the trench isolation structure. The first passivation layer comprises hydrogenated amorphous silicon. In one embodiment, the first passivation layer is located on the sidewall of the substrate and on the sidewall of the trench isolation structure. In another embodiment, the first passivation layer is located on the sidewall of the substrate, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the integrated chip further comprises: a second passivation layer located on the first passivation layer and on the sidewall of the trench isolation structure, wherein the second passivation layer comprises p-type doped hydrogenated amorphous silicon. In one embodiment, the first passivation layer is located on the sidewall of the substrate, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the integrated chip further comprises: a second passivation layer located on the first passivation layer, wherein the second passivation layer comprises p-type doped hydrogenated amorphous silicon; and a third passivation layer located on the second passivation layer and on the sidewall of the trench isolation structure, wherein the third passivation layer comprises aluminum oxide. In one embodiment, the hydrogenated amorphous silicon is p-type doped, and the substrate is n-type doped along the sidewall of the substrate. In one embodiment, the hydrogenated amorphous silicon is p-type doped, and the substrate is p-type doped along the sidewall of the substrate, wherein the p-type dopant concentration of the hydrogenated amorphous silicon is greater than the p-type dopant concentration of the substrate. In one embodiment, the substrate includes a first semiconductor well having a first doping type and a second semiconductor well having a second doping type opposite to the first doping type, wherein the first semiconductor well extends from a first sidewall of the first passivation layer to a second sidewall of the first passivation layer opposite to the first sidewall, and wherein the bottom surface of the first passivation layer is located on top of the second semiconductor well. In one embodiment, the substrate includes crystalline silicon, wherein the hydrogen concentration of the hydrogenated amorphous silicon is between 4% and 35%, and wherein the p-type dopant concentration of the hydrogenated amorphous silicon is between 10%. 14 per cubic centimeter and 10 21 Between per cubic centimeter.

[0148] In other embodiments, this disclosure relates to an integrated chip including a substrate, a first semiconductor well, a trench isolation structure, and a passivation structure. The first semiconductor well is located within the substrate. A photodetector is formed within the first semiconductor well within the substrate. A trench isolation structure extends into the first semiconductor well on the opposite side of the photodetector. The trench isolation structure separates the photodetector from adjacent photodetectors. A passivation structure is located between the first semiconductor well and the trench isolation structure. The first semiconductor well is located on a sidewall of the passivation structure. The passivation structure comprises hydrogenated amorphous silicon. In one embodiment, the passivation structure comprises a first passivation layer including the hydrogenated amorphous silicon, wherein the hydrogenated amorphous silicon is p-type doped, wherein the first semiconductor well is located on a sidewall of the first passivation layer, and wherein the first passivation layer is located on the sidewall of the trench isolation structure. In one embodiment, the passivation structure comprises a first passivation layer and a second passivation layer above the first passivation layer, wherein the first semiconductor well is located on a sidewall of the first passivation layer, wherein the first passivation layer comprises intrinsic hydrogenated amorphous silicon, and wherein the second passivation layer is located on the sidewall of the trench isolation structure and comprises p-type hydrogenated amorphous silicon. In another embodiment, the passivation structure comprises a first passivation layer, a second passivation layer above the first passivation layer, and a third passivation layer above the second passivation layer, wherein the first semiconductor well is located on a sidewall of the first passivation layer, wherein the first passivation layer comprises intrinsic hydrogenated amorphous silicon, wherein the second passivation layer comprises p-type hydrogenated amorphous silicon, and wherein the third passivation layer is located on the sidewall of the trench isolation structure and comprises aluminum oxide. In one embodiment, the passivation structure comprises a first passivation layer and a second passivation layer above the first passivation layer, wherein a first semiconductor well is located on a sidewall of the first passivation layer, wherein the first passivation layer comprises p-type hydrogenated amorphous silicon, and wherein the second passivation layer is located on the sidewall of the trench isolation structure and comprises aluminum oxide. In one embodiment, the first semiconductor well has a first doping type, and wherein the integrated chip further comprises: a second semiconductor well located within the substrate, the second semiconductor well having a second doping type opposite to the first doping type, wherein the second semiconductor well is located directly below the trench isolation structure, and wherein the passivation structure extends between the trench isolation structure and the second semiconductor well. In one embodiment, the bottom surface of the passivation structure is located below the top of the second semiconductor well, wherein the second semiconductor well extends along the sidewall of the passivation structure, and wherein the top of the second semiconductor well is located below the top surface of the passivation structure.

[0149] In other embodiments, this disclosure relates to a method for forming an integrated chip. The method includes forming a photodetector in a substrate. The substrate is patterned to form trenches in the substrate. The trenches are formed by sidewalls of the substrate and surround the photodetector. A first passivation layer is deposited on the sidewalls of the substrate forming the trenches. The first passivation layer comprises hydrogenated amorphous silicon. A dielectric layer is deposited over the first passivation layer and in the remainder of the trenches to form a trench isolation structure over the first passivation layer and surrounding the photodetector. In one embodiment, the hydrogenated amorphous silicon of the first passivation layer is undoped, and the method further includes depositing a second passivation layer over the first passivation layer, the second passivation layer comprising p-type doped hydrogenated amorphous silicon. In one embodiment, the method for forming an integrated chip further includes depositing a third passivation layer over the second passivation layer, the third passivation layer comprising aluminum oxide. In one embodiment, the method for forming an integrated chip further includes annealing the first passivation layer at a temperature below 250 degrees Celsius. In one embodiment, the first passivation layer is deposited such that the first passivation layer is disposed along the back side of the substrate, wherein the dielectric layer is deposited such that the dielectric layer is disposed along the back side of the substrate, and wherein the method further includes performing a planarization process on the dielectric layer and the first passivation layer to remove the dielectric layer and the first passivation layer from the back side of the substrate.

[0150] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: Substrate; A photodetector is disposed within the substrate; A trench isolation structure extends into the substrate on opposite sides of the photodetector, wherein the trench isolation structure separates the photodetector from adjacent photodetectors; as well as A first passivation layer is located between the sidewall of the substrate and the sidewall of the trench isolation structure, wherein the first passivation layer comprises hydrogenated amorphous silicon.

2. The integrated chip of claim 1, wherein the first passivation layer is located on the sidewall of the substrate and on the sidewall of the trench isolation structure.

3. The integrated chip of claim 1, wherein the first passivation layer is located on the sidewall of the substrate, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the integrated chip further comprises: A second passivation layer is located on the first passivation layer and on the sidewall of the trench isolation structure, wherein the second passivation layer comprises hydrogenated amorphous silicon with p-type doping.

4. The integrated chip of claim 1, wherein the first passivation layer is located on the sidewall of the substrate, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the integrated chip further comprises: A second passivation layer is located on the first passivation layer, wherein the second passivation layer comprises hydrogenated amorphous silicon with p-type doping; as well as A third passivation layer is located on the second passivation layer and on the sidewall of the trench isolation structure, wherein the third passivation layer comprises aluminum oxide.

5. The integrated chip of claim 1, wherein the hydrogenated amorphous silicon has p-type doping and the substrate has n-type doping along the sidewalls of the substrate.

6. The integrated chip of claim 1, wherein the substrate has p-type doping along the sidewall of the substrate, and wherein the p-type dopant concentration of the hydrogenated amorphous silicon is greater than the p-type dopant concentration of the substrate.

7. The integrated chip of claim 1, wherein the substrate includes a first semiconductor well having a first doping type and a second semiconductor well having a second doping type opposite to the first doping type, wherein the first semiconductor well extends from a first sidewall of the first passivation layer to a second sidewall of the first passivation layer opposite to the first sidewall, and wherein the bottom surface of the first passivation layer is located on top of the second semiconductor well.

8. The integrated chip of claim 1, wherein the substrate comprises crystalline silicon, wherein the hydrogen concentration of the hydrogenated amorphous silicon is between 4% and 35%, and wherein the p-type dopant concentration of the hydrogenated amorphous silicon is between 10%. 14 cm -3 With 10 21 cm -3 between.

9. An integrated chip, comprising: Substrate; A first semiconductor well is located within the substrate, wherein the first semiconductor well forms a photodetector within the substrate; A trench isolation structure extends into the first semiconductor well on the opposite side of the photodetector, wherein the trench isolation structure separates the photodetector from adjacent photodetectors; as well as A passivation structure is located between the first semiconductor well and the trench isolation structure, wherein the first semiconductor well is located on the sidewall of the passivation structure, wherein the passivation structure is located on the sidewall of the trench isolation structure, and wherein the passivation structure comprises hydrogenated amorphous silicon.

10. The integrated chip of claim 9, wherein the passivation structure comprises a first passivation layer including the hydrogenated amorphous silicon, wherein the hydrogenated amorphous silicon is p-type doped, wherein the first semiconductor well is located on the sidewall of the first passivation layer, and wherein the first passivation layer is located on the sidewall of the trench isolation structure.

11. The integrated chip of claim 9, wherein the passivation structure comprises a first passivation layer and a second passivation layer above the first passivation layer, wherein the first semiconductor well is located on the sidewall of the first passivation layer, wherein the first passivation layer comprises intrinsic hydrogenated amorphous silicon, and wherein the second passivation layer is located on the sidewall of the trench isolation structure and comprises p-type hydrogenated amorphous silicon.

12. The integrated chip of claim 9, wherein the passivation structure comprises a first passivation layer, a second passivation layer above the first passivation layer, and a third passivation layer above the second passivation layer, wherein the first semiconductor well is located on the sidewall of the first passivation layer, wherein the first passivation layer comprises intrinsic hydrogenated amorphous silicon, wherein the second passivation layer comprises p-type hydrogenated amorphous silicon, and wherein the third passivation layer is located on the sidewall of the trench isolation structure and comprises aluminum oxide.

13. The integrated chip of claim 9, wherein the passivation structure comprises a first passivation layer and a second passivation layer above the first passivation layer, wherein the first semiconductor well is located on the sidewall of the first passivation layer, wherein the first passivation layer comprises p-type hydrogenated amorphous silicon, and wherein the second passivation layer is located on the sidewall of the trench isolation structure and comprises aluminum oxide.

14. The integrated chip of claim 9, wherein the first semiconductor well has a first doping type, and wherein the integrated chip further comprises: A second semiconductor well is located within the substrate, the second semiconductor well having a second doping type opposite to the first doping type, wherein the second semiconductor well is located directly below the trench isolation structure, and wherein the passivation structure extends between the trench isolation structure and the second semiconductor well.

15. The integrated chip of claim 14, wherein the bottom surface of the passivation structure is located below the top of the second semiconductor well, wherein the second semiconductor well extends along the sidewall of the passivation structure, and wherein the top of the second semiconductor well is located below the top surface of the passivation structure.

16. A method for forming an integrated chip, the method comprising: A photodetector is formed in the substrate; The substrate is patterned to form trenches in the substrate, wherein the trenches are formed by the sidewalls of the substrate and wherein the trenches surround the photodetector; A first passivation layer is deposited on the sidewall of the substrate forming the trench, the first passivation layer comprising hydrogenated amorphous silicon; as well as A dielectric layer is deposited over the first passivation layer and in the remaining portion of the trench to form a trench isolation structure over the first passivation layer and surrounding the photodetector.

17. The method for forming an integrated chip according to claim 16, wherein the hydrogenated amorphous silicon of the first passivation layer is undoped, and wherein the method further comprises: A second passivation layer is deposited above the first passivation layer, the second passivation layer comprising hydrogenated amorphous silicon with p-type doping.

18. The method for forming an integrated chip according to claim 17, further comprising: A third passivation layer, comprising aluminum oxide, is deposited over the second passivation layer.

19. The method for forming an integrated chip according to claim 17, further comprising: The first passivation layer is annealed at a temperature below 250 degrees Celsius.

20. The method for forming an integrated chip according to claim 17, wherein the first passivation layer is deposited such that the first passivation layer is disposed along the back side of the substrate, wherein the dielectric layer is deposited such that the dielectric layer is disposed along the back side of the substrate, and wherein the method further comprises: A planarization process is performed on the dielectric layer and the first passivation layer to remove the dielectric layer and the first passivation layer from the back side along the substrate.

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