IGBT semiconductor structure

Abstract

The IGBT semiconductor structure (10) has p + Substrate (24), n ‑ Layer (28), at least one of the n ‑ The p region (32) adjacent to layer (28) and at least one n region adjacent to said p region (32) + Region (34), which comprises a GaAs compound or is composed of a GaAs compound, a dielectric layer (20), and three interconnecting portions (14, 16, 18), wherein the p region (32) and the n region are connected. ‑ Layer (28) forms the first pn junction (36), and the n + Region (34) and at least one p region (32) form a second pn junction (38), the dielectric layer (20) covers the first pn junction (36) and the second pn junction (38), the second connection connection (16) is formed on the field plate on the dielectric layer (20), and in the p + Substrate (24) and the n ‑ A doped intermediate layer (26) is disposed between layers (28), the intermediate layer having a layer thickness (D3) of 1 micrometer to 50 micrometers and a density of 10 μm. 12 -10 17 cm ‑3 The dopant concentration, wherein the intermediate layer (26) is at least with the p + The substrate (24) material is locked together.

Description

[0001] This is a divisional application of patent application with application date of December 28, 2017, application number 201711458322.0, and invention title "IGBT semiconductor structure". TECHNICAL FIELD

[0002] The present invention relates to an IGBT semiconductor structure having a p + substrate, an n - layer, a p region, an n + region, a dielectric layer and three connecting contact portions. BACKGROUND

[0003] IGBTs in different embodiments are known from Jesef Lutz et al., Semiconductor Power Devices, Springer edition 2011, ISBN 978-3-642-11124-2, chapter X, pages 322, 323 and 330. Such power devices are manufactured on the basis of silicon or silicon carbide.

[0004] A high-voltage-resistant semiconductor diode p + -n-n + and a high-voltage-resistant p-n-i-p transistor on the basis of GaAs are known from German Ashkinazi, GaAs Power Devices, ISBN 965-7094-19-4, chapter V, page 97 or chapter 7.8, page 225.

[0005] The deposition of an oxide layer on GaAs, for example by means of an atomic layer deposition (ALD) process, is described in the article by M. Xu et al., New Insight into Fermi-Level Unpinning on GaAs: Impact of Different Surface Orientations, Electron Device Meeting (IEDM), IEEE, 2009, pages 865-868, and in the article by G. K. Dalapati et al., Impact of Buffer Layer on Atomic Layer Deposited TiAlO Alloy Dielectric Quality for Epitaxial-GaAs / Ge Device Application, IEEE Transactions on Electron Devices, volume 60, No. 1, 2013.

[0006] In the described background, the task of the present invention is to specify a device which extends the state of the art.

[0007] The task is solved by an IGBT semiconductor structure having the features according to the invention. Advantageous configurations of the invention are preferred embodiments. SUMMARY

[0008] According to the subject matter of the invention, an IGBT semiconductor structure is proposed which has an upper side and a lower side.

[0009] The IGBT semiconductor structure has a p + substrate which is constructed at the lower side of the IGBT semiconductor structure. + The IGBT semiconductor structure has an n - layer which is supported on the p

[0010] The n - layer has an adjoining p region and at least one n + region which adjoins the p region.

[0011] The IGBT semiconductor structure has a dielectric layer which is preferably composed of a deposited oxide, a first connection access which is conductively connected with the lower side of the IGBT semiconductor structure, a second connection access and a third connection access.

[0012] The p + substrate has a dopant concentration of 5*10 18 - 5*10 20 cm -3 and a layer thickness of 50-500 micrometers.

[0013] The n - layer has a dopant concentration of 10 12 - 10 17 cm -3 and a layer thickness of 10-300 micrometers.

[0014] The at least one p region has a dopant concentration of 10 14 - 10 18 cm -3 and the at least one n + region has a dopant concentration of at least 10 19 cm -3 , wherein the at least one p region forms a first pn junction with the n - layer.

[0015] The n + region forms a second pn junction with the p region.

[0016] The p + substrate, the n -layer, p region and n + The layers, the p region and the n

[0017] The first, the second and the third connection contact each comprise or each consist of a metal or a metal compound, wherein the second connection contact is configured as a field plate on the dielectric layer.

[0018] The third connection contact is electrically conductively connected with at least one p region and at least one n + region.

[0019] Preferably, the connection contacts are each arranged at a surface of the semiconductor structure.

[0020] The dielectric layer covers at least the first pn junction and the second pn junction and is electrically conductively connected with the n - layer, the p region and the n + region material-lockingly.

[0021] Between the p + substrate and the n - layer, a doped intermediate layer is additionally arranged, which has a layer thickness of 1 micrometer to 50 micrometers and a dopant concentration of 10 12 -10 17 cm-2. -3 Preferably, the intermediate layer is electrically conductively connected with the p + substrate material-lockingly.

[0022] It is noted that the second connection contact is denoted as gate. The first connection contact is typically denoted as collector or anode, and the third connection contact is denoted as emitter or cathode.

[0023] It is understood that layers are formed on the connection contacts. The connection contacts are each electrically conductive and have metallic properties and comprise or preferably consist of a semiconducting layer or a metal layer which is electrically conductive in a metallic manner or a combination of both. The connection contacts form a low-ohmic electrical contact to the directly adjoining doped semiconducting layer.

[0024] It is further understood that the connection contacts are preferably connected with contact fingers, so-called pins, by means of bonding wires.

[0025] It is further understood that the intermediate layer has at least one different dopant concentration compared to the adjoining layers.

[0026] An advantage is that the carriers of the GaAs semiconductor structure have a smaller effective mass than silicon. Higher temperatures can also be achieved at the pn junction than with silicon without damaging the device. As a result, higher switching frequencies and lower losses can be achieved with GaAs semiconductor structures than with comparable silicon semiconductor structures.

[0027] A further advantage is that the III-IV IGBT semiconductor structure can be more cost-advantageous than comparable semiconductor structures made of silicon carbide.

[0028] A further advantage of the III-V-IGBT semiconductor structure according to the application is a high heat resistance up to 300°C. In other words, the III-V semiconductor diode can also be used in warmer environments.

[0029] In a first embodiment, the intermediate layer is configured to be p-type doped and comprises zinc and / or silicon as a dopant according to an alternative expansion. The dopant concentration of the intermediate layer is preferably less than p + the dopant concentration of the substrate. Particularly preferably, the dopant concentration is smaller in the range between a factor of 2 and a factor of five orders of magnitude.

[0030] In another embodiment, the intermediate layer is configured to be n-type doped and preferably comprises silicon and / or tin as a dopant. The dopant concentration of the intermediate layer is preferably less than n + the dopant concentration of the substrate. Particularly preferably, the dopant concentration is smaller by a factor of 100 than n - the dopant concentration of the layer.

[0031] According to another embodiment, the IGBT semiconductor structure has a buffer layer which is n-type doped, wherein the buffer layer is arranged between the intermediate layer and the n - layer, has a dopant concentration of 10 12 - 10 16 cm -3 and a layer thickness of 1 to 50 micrometers and comprises or consists of a GaAs compound.

[0032] In another embodiment, the IGBT semiconductor structure forms a trench IGBT semiconductor structure, wherein the dielectric layer extends perpendicular to the upper side of the IGBT semiconductor structure.

[0033] The p + substrate preferably comprises zinc. The n - layer and / or the n + region preferably comprises silicon and / or chromium and / or palladium and / or tin, wherein the IGBT semiconductor structure is particularly preferably configured monolithically.

[0034] According to another embodiment, the total height of the IGBT semiconductor structure is at most 150-500 micrometers, and / or the edge length or diameter of the IGBT semiconductor structure is between 1 millimeter and 15 millimeters.

[0035] In another embodiment, the p-region and / or the n-region are configured round at the upper side of the IGBT semiconductor structure or are configured exactly as a half circle arranged at the end face of the structure, respectively.

[0036] According to an extension, the dielectric layer comprises a deposited oxide and has a layer thickness of 10 nanometers to 1 micrometer.

[0037] In another embodiment, the stack-like layer structure has an n - layer formed between the p + substrate and the n + substrate.

[0038] It should be noted that the expression "semiconductor junction" is used synonymously with the expression "wafer junction".

[0039] In another embodiment, the layer structure consisting of the p + substrate forms a first partial stack, and the layer structure consisting of the n + layer, the n - layer and, if necessary, the buffer layer forms a second partial stack.

[0040] In an extension, the stack-like layer structure comprises an intermediate layer arranged between the p + substrate and the n - layer. Here, the first partial stack comprises the intermediate layer. The semiconductor junction is arranged between the intermediate layer and the n - layer or between the intermediate layer and the buffer layer.

[0041] In an extension, the first partial stack and the second partial stack are each configured monolithically.

[0042] In an application extension, the first partial stack is formed, in which, proceeding from the p + substrate, the intermediate layer is produced by means of an epitaxy method. Preferably, the intermediate layer configured as a p - layer has a doping of less than 10 13 cm -3 - that is to say, the intermediate layer is intrinsically doped - or a doping of 10 13 cm -3 to 10 15 cm -3 In an embodiment, the p + substrate is thinned to a thickness of between 200 micrometers and 500 micrometers by means of a grinding process before or after the junction.

[0043] In another embodiment, a second stack is formed, wherein, from n - Starting from layer n - Substrate and second stack—that is, with n + Layers are connected via a wafer bonding process. In one implementation, n + The layer structure is n + Substrate.

[0044] In another process step, n - The substrate is thinned to the desired thickness.

[0045] In one extended scheme, when thinning n - substrate or n - A buffer layer is created by extension after the layer.

[0046] Preferably, n - substrate or n - The thickness of the layer is between 50 micrometers and 250 micrometers. Preferably, n - The substrate is doped at 10 13 cm -3 Up to 10 15 cm -3 Within the range between. The advantage of wafer bonding is that n - The thickness of the layer can be easily manufactured. This eliminates the need for a long deposition process during epitaxy. Wafer bonding also reduces the number of stacking errors.

[0047] In an alternative implementation, n - The substrate has a density greater than 10 10 cm -3 And less than 10 13 cm -3 The doping is extremely small, n. - The substrate can also be understood as an intrinsic layer.

[0048] In one extended scheme, n is made possible by means of a semiconductor bonding process step. - The surface of the substrate or buffer layer is directly attached to the first stack. Next, n... - The back side of the substrate is thinned to n - The desired thickness of the layer. When thinning n... - substrate or n - After layering, epitaxy or highly doped implantation is used to generate cells with 10... 18 cm -3 Up to 5*10 15 cm -3 doped n in the range between + layer.

[0049] Understandable, n- The thinning of the substrate is preferably carried out by means of a CMP step, that is to say by means of chemical-mechanical grinding. BRIEF DESCRIPTION OF DRAWINGS

[0050] The application is explained further below with reference to the drawings. Identical parts are provided with the same reference symbols here. The embodiments shown are strongly diagrammatic, that is to say that the distances and the lateral and longitudinal extensions are not to scale and, as far as not stated otherwise, also do not have a derivable geometrical relationship to one another. Shown here are:

[0051] Figure 1 schematic view of an IGBT according to a first embodiment of the application;

[0052] Figure 2 schematic top view of an IGBT according to a first embodiment of the application;

[0053] Figure 3 schematic view of an IGBT according to a second embodiment of the application;

[0054] Figure 4 schematic view of an IGBT according to a third embodiment of the application;

[0055] Figure 5 schematic top view of an IGBT according to a third embodiment of the application;

[0056] Figure 6 schematic view of an IGBT according to a fourth embodiment of the application. DETAILED DESCRIPTION

[0057] Figure 1 The drawing shows a sectional view of a first embodiment of an IGBT semiconductor structure 10 with three connection contacts 14, 16, 18 and one dielectric layer 20. The IGBT semiconductor 10, also designated below as semiconductor structure 10, is configured in a stack with an upper side 12 and a lower side 22 and has a so-called non-punch-through design and a total height H1 in the embodiment shown.

[0058] The first connection contact 14 is configured as a metal layer, wherein the metal layer is connected to the lower side 22 of the semiconductor structure 10 in a material-locking manner.

[0059] The lowermost layer of the IGBT semiconductor structure forms a p + substrate 24. The p + substrate forms the lower side 22 of the semiconductor structure 10 and has a layer thickness D1. The p +A thin, weakly n-doped or weakly p-doped intermediate layer 26 having a thickness D3 and an n - layer 28 is present on the substrate in the mentioned order.

[0060] In the embodiment shown, the n - layer 28 forms at least a portion of the upper side 12 of the semiconductor structure 10. Another portion of the upper side 12 of the semiconductor structure 10 is formed by a p-region 32, wherein the p-region 32 extends from the upper side 12 of the IGBT semiconductor structure 10 into the n - layer up to a depth T1.

[0061] Another portion of the upper side 12 of the semiconductor structure 10 is formed by an n + region 34, wherein the n + region extends from the upper side 12 of the semiconductor structure 10 into the p-region up to a depth T2, and T2 is smaller than T1.

[0062] Thus, at the upper side 12 of the semiconductor structure 10, a first pn-junction 36 between the p-region and the n - layer and a second pn-junction 38 between the n + region and the p-region are adjoiningly configured, wherein the dielectric layer 20 at least covers the first pn-junction 36 and the second pn-junction 38 and is materially bonded with the upper side 12 of the semiconductor structure 10, in particular with the n + region, the p-region and the n - layer, and has a layer thickness D5.

[0063] The second connection access 16 is configured as a field plate on a surface of the dielectric layer 20 facing away from the semiconductor structure 10.

[0064] The third connection access 18 is likewise configured as a metal layer, wherein the metal layer is materially bonded with the portion of the upper side 12 of the semiconductor structure 10 formed by the p-region and the n + region.

[0065] The n + region 34, the p-region 32 and the n - layer 28 form, together with the dielectric layer 16 and the three connection accesses 14, 16, 18, a MOS transistor, i.e. a bipolar component, whereas the p-substrate 24, the intermediate layer 26 and the n - layer 28 behave as a pin diode.

[0066] In Figure 2 the attached figures, a top view on the upper side 12 of the IGBT semiconductor structure 10 is shown. Not only the p-region 32 but also the n +The region 34 is configured circularly. The IGBT semiconductor structure 10 has a rectangular upper side 12 with a first edge length K1 and a second edge length K2.

[0067] In Figure 3 the drawing another embodiment of an IGBT semiconductor structure 10 is shown. In the following only the differences with respect to Figure 1 the drawing are explained. The semiconductor structure 10 is configured as a so-called punch-through IGBT, wherein between the intermediate layer 26 and the n-layer 28 a buffer layer 40 with a layer thickness D4 of weak n-type or weak p-type doping is arranged.

[0068] In Figure 4 the drawing another embodiment of an IGBT semiconductor structure 10 is shown. In the following only the differences with respect to Figure 1 and 3 the drawings are explained. The semiconductor structure 10 is configured as a so-called trench IGBT.

[0069] The p-region 32 and the n + region 34 are each configured as a layer on the n - layer or the p-region 32, wherein the semiconductor structure 10 has from the upper side 12 through the layered n-region and the layered p-region up to a channel (Grabe) 42, which reaches into the n - layer, i.e. a so-called trench.

[0070] The first pn-junction 36 and the second pn-junction 38 extend perpendicular to a side face 44 of the channel 42. The side face 44 as well as a bottom 46 of the channel are covered with the dielectric layer 20. The second connection contact 16, which is configured as a field plate, extends accordingly on the dielectric layer 20. The third connection contact 18 is arranged at a side face 50 of the semiconductor structure 10, which is opposite to the side face 44 of the channel 42, and is in electrically conductive connection with the layered n + region 34 as well as with the layered p-region 32.

[0071] In an alternative embodiment, in Figure 6 the third connection contact 18 is arranged at the side face 12. In other words, the second pn-junction 38 is also configured at the surface in the embodiment shown in Figure 1 .

[0072] In Figure 5 the drawing a schematic top view on a trench IGBT according to Figure 4 is shown. The channel 42 has an elongated, circular shape and the IGBT semiconductor structure 10 has a diameter Al.

[0073] In Figure 6Another embodiment of an IGBT semiconductor structure 10 is shown in the accompanying drawings. The following only sets forth the differences with respect to the Figure 4 embodiment of the accompanying drawings. Again, the semiconductor structure 10 forming a trench IGBT has a buffer layer 40 between the intermediate layer 26 and the n - layer 28.

Claims

1. An IGBT semiconductor structure (10) having an upper side (12) and a lower side (22), the IGBT semiconductor structure having: - p + a substrate (24), said p + substrate is configured at the lower side (22) of the IGBT semiconductor structure (10), and said p + substrate has a doping concentration of 5*10 18 - 5*10 20 cm -3 dopant concentration, a layer thickness (D1) of 50-500 micrometers and consisting of a GaAs compound, - n - layer (28), the n - layer has a 10 12 -10 17 cm -3 dopant concentration, a layer thickness (D2) of 10-300 microns and is composed of a GaAs compound, - at least one p-region (32) which adjoins the n - layer (28) and has a dopant concentration of 10 14 - 10 18 cm -3 and consists of a GaAs compound, - at least one n + region (34), said at least one n + region adjoins the p region (32) and has a dopant concentration of at least 10 19 cm -3 and consists of a GaAs compound, a dielectric layer (20), a first connection access (14) which is in electrically conductive connection with the lower side (22) of the IGBT semiconductor structure (10) and which comprises or consists of a metal or a metal compound, a second connection access (16) and a third connection access (18) which each comprise or consist of a metal or a metal compound, wherein - said at least one p-region (32) forms a first pn-junction (36) with said n - layer (28), - said at least one n + The region (34) forms a second pn junction (38) with said at least one p region (32), - the dielectric layer (20) covers at least the first pn junction (36) and the second pn junction (38) and is materially connected with the n - layer (28), the p region (32) and the n + region (34), the IGBT semiconductor structure (10) comprises a trench, wherein the dielectric layer (20) extends perpendicular to the upper side (12) of the IGBT semiconductor structure (10), the second connection access (16) is configured as a field plate on the dielectric layer (20), and - the third connection contact (18) is arranged at a side (50) of the semiconductor structure (10) opposite to a side (44) of the trench and is in electrically conductive connection with the at least one p-region (32) and at least one n-region (34), + ​ In the p + A doped intermediate layer (26) is arranged between the n - layer (28) having a layer thickness (D3) of 1 to 50 micrometers and a dopant concentration of 10 12 -10 17 cm -3 -2, wherein the intermediate layer (26) is at least materially bonded to the p + substrate (24).

2. The IGBT semiconductor structure (10) according to claim 1, characterized in that the intermediate layer (26) is configured as p-type doped.

3. The IGBT semiconductor structure (10) according to claim 2, characterized in that The dopant concentration of the intermediate layer (26) is configured to be less than the p + The dopant concentration of the substrate (24), or the dopant concentration of the intermediate layer (26), is the p + 1 / 10000 to 1 / 2 of the dopant concentration of the substrate.

4. The IGBT semiconductor structure (10) according to claim 2 or 3, characterized in that The intermediate layer (26) comprises zinc and / or silicon.

5. The IGBT semiconductor structure (10) according to claim 1, characterized in that The intermediate layer (26) is configured as n-type doped.

6. The IGBT semiconductor structure (10) according to claim 5, characterized in that The intermediate layer (26) comprises silicon and / or tin.

7. The IGBT semiconductor structure (10) according to claim 5 or 6, characterized in that The dopant concentration of the intermediate layer (26) is less than the dopant concentration of the n - layer (28) and at least 1 / 100 of the dopant concentration of the n - layer (28).

8. The IGBT semiconductor structure (10) according to any one of claims 1 to 7, characterized in that The IGBT semiconductor structure (10) has an n-doped buffer layer (40), wherein the buffer layer (40) is arranged between the intermediate layer (26) and the n - layer (28), the buffer layer (40) has a dopant concentration of 10 12 -10 17 cm -3 and a layer thickness (D4) of 1 to 50 micrometers and comprises or consists of a GaAs compound.

9. The IGBT semiconductor structure (10) according to any one of claims 1 to 8, characterized in that The p + The substrate (24) comprises zinc.

10. The IGBT semiconductor structure (10) according to any one of claims 1 to 9, characterized in that The n - The layer (28) and / or the n + The region (34) comprises silicon and / or chromium and / or palladium and / or tin.

11. The IGBT semiconductor structure (10) according to any one of claims 1 to 10, characterized in that The IGBT semiconductor structure (10) is configured monolithically.

12. The IGBT semiconductor structure (10) according to any one of claims 1 to 11, characterized in that The total height (H1) of the IGBT semiconductor structure (10) is at most 150-500 micrometers.

13. The IGBT semiconductor structure (10) according to any one of claims 1 to 12, characterized in that The p region (32) and / or the n + The p region (32) and / or the n region (34) are configured elliptically or circularly at the upper side (12) of the IGBT semiconductor structure (10).

14. The IGBT semiconductor structure (10) according to any one of claims 1 to 13, characterized in that The IGBT semiconductor structure (10) has an edge length (K1, K2) of 1 millimeter to 15 millimeters or a diameter (A1) of 1 millimeter to 15 millimeters.

15. The IGBT semiconductor structure (10) according to any one of claims 1 to 14, characterized in that The dielectric layer (20) comprises a deposited oxide and has a layer thickness (D5) of 10 nanometers to 1 micrometer.

16. The IGBT semiconductor structure (10) according to any one of claims 1 to 15, characterized in that The p-region (32) and the n + region (34) are respectively configured as planar layers on the n - layer (28) or the p-region (32), wherein the trench extends from the upper side (12) through the n + region (34) and the p-region (32) to the n - layer (28).

Images