Infrared device and method for manufacturing infrared device

Abstract

The present invention provides an infrared device and a method for manufacturing the infrared device. The infrared device comprises a first terrace portion, the first terrace portion comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer as an active layer, and a third semiconductor layer of a second conductivity type, wherein the side surface of the first terrace portion comprises a first side surface located on a side close to a lower surface of the first terrace portion, a second side surface located above the first side surface, and a third side surface located above the second side surface, a first angle formed by the first side surface and one surface of a substrate is greater than 0.6° and less than 45°, a second angle formed by the second side surface and one surface of the substrate is greater than 45° and less than 90°, a third angle formed by the third side surface and one surface of the substrate is greater than 0.6° and less than 45°, W3 / W2 is greater than 0.15, and W1 / W2 is greater than 0.2 and less than 3.0.

Description

Technical Field

[0001] The present disclosure relates to an infrared device and a method for manufacturing a light-receiving element of the infrared device. Background Art

[0002] As infrared devices, infrared receiving elements that output signals corresponding to received infrared rays and infrared emitting elements that emit infrared rays in response to input power are known. In a quantum type infrared receiving element, infrared rays are detected by using a photocurrent generated by a semiconductor having a pn junction or a pin junction absorbing infrared rays. Infrared receiving elements are also called infrared sensors. In addition, quantum type infrared receiving elements are used in human sensing sensors and non-contact temperature sensors that detect infrared rays emitted from the human body. In an infrared emitting element, infrared rays are emitted by applying a voltage in the positive direction. Infrared emitting elements are also called infrared light emitting diodes or infrared LEDs (light emitting diodes). These elements can be used, for example, in NDIR (non dispersive infrared) type gas sensors (for example, Patent Document 1). NDIR type gas sensors can measure gas concentrations using an infrared receiving element that receives infrared rays in an absorption wavelength band corresponding to the gas to be detected and an infrared emitting element that emits infrared rays in the absorption wavelength band.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2004-271518 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] In recent years, infrared devices are becoming more and more popular, and their applications are also diverse. In the field of sensing technology in particular, in order to further improve the accuracy of sensors, it is necessary to improve the performance of infrared light-receiving elements and infrared light-emitting elements. Some quantum infrared light-receiving elements and infrared light-emitting elements have a pin diode structure composed of compound semiconductors using materials such as Al, P, Ga, As, In, and Sb. In this case, photoelectric conversion is performed in the i layer, that is, the active layer, so in order to improve the photoelectric conversion efficiency, it is effective to increase the volume of the active layer.

[0008] On the other hand, when the thickness of the i-layer is increased in order to increase the volume of the active layer, there arises a problem in processing that the coverage of the insulating layer and the electrode portion is deteriorated.

[0009] In addition, when a compound semiconductor layer is provided on a substrate and a diode shape is formed by wet etching, an etched hole called an etching pit is generated on the surface starting from the lattice defect introduced between the substrate and the semiconductor layer. In addition, when the wet etching method is used, etching progresses isotropically, so a gently inclined shape is formed on the etching side surface, and the volume of the active layer becomes smaller.

[0010] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide an infrared device having improved photoelectric conversion efficiency and a method for manufacturing the infrared light receiving element.

[0011] Solutions for solving problems

[0012] An infrared device according to one embodiment comprises a first terrace portion, wherein the first terrace portion comprises: a first semiconductor layer of a first conductivity type provided on one surface side of a substrate; a second semiconductor layer which is an active layer stacked on the first semiconductor layer; and a third semiconductor layer of a second conductivity type stacked on the second semiconductor layer, wherein the side surface of the first terrace portion comprises: a first side surface located at a position close to a lower surface of the first terrace portion; a second side surface located at a position higher than the first side surface; and a third side surface located at a position higher than the second side surface, the first side surface and one side of the substrate being in contact with each other. A first angle formed by the second side surface and one surface of the substrate is greater than 0.6° and less than 45°, a second angle formed by the second side surface and one surface of the substrate is greater than 45° and less than 90°, a third angle formed by the third side surface and one surface of the substrate is greater than 0.6° and less than 45°, and when the length of the first side surface in a direction parallel to the surface of the substrate is set to W1, the length of the second side surface in a direction parallel to the surface of the substrate is set to W2, and the length of the third side surface in a direction parallel to the surface of the substrate is set to W3, W3 / W2 is greater than 0.15, and W1 / W2 is greater than 0.2 and less than 3.0.

[0013] A method for manufacturing an infrared device involved in one embodiment includes: a process of forming a first semiconductor layer of a first conductivity type on one surface side of a substrate; a process of forming a second semiconductor layer as an active layer on the first semiconductor layer; a process of forming a third semiconductor layer of a second conductivity type on the second semiconductor layer; a first etching process of performing dry etching with an inter-electrode voltage of 330V or more to form a first terrace portion including an upper portion of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; and a second etching process of performing dry etching with an inter-electrode voltage of less than 330V.

[0014] Effects of the Invention

[0015] According to the infrared device of the embodiment of the present disclosure, it is possible to provide an infrared device having improved photoelectric conversion efficiency and a method for manufacturing the infrared light receiving element. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a cross-sectional view showing a structural example of an infrared device according to an embodiment.

[0017] Figure 2 It is a cross-sectional view schematically showing a configuration example of a first stage portion and a second stage portion of an infrared device according to an embodiment.

[0018] Figure 3A It is a cross-sectional view showing a method of manufacturing an infrared device.

[0019] Figure 3B It is a cross-sectional view showing a method of manufacturing an infrared device.

[0020] Figure 3C It is a cross-sectional view showing a method of manufacturing an infrared device.

[0021] Figure 3D It is a cross-sectional view showing a method of manufacturing an infrared device.

[0022] Figure 4 This is a diagram illustrating a cross section of an infrared device produced by the method of Comparative Example 1.

[0023] Figure 5 It is shown Figure 4 A diagram of the differential values ​​of the shape of the first face of an infrared device.

[0024] Figure 6 This is a diagram illustrating a cross section of an infrared device manufactured by the method of Example 1.

[0025] Figure 7 It is shown Figure 6 A diagram of the differential values ​​of the shape of the first face of an infrared device.

[0026] Figure 8 This is a graph obtained by plotting W3 / W2 against V2.

[0027] Fig.9A This is a diagram comparing the shapes of the first stage face under various conditions of V2.

[0028] Fig. 9B This is a diagram comparing the shapes of the first stage face under various conditions of V2.

[0029] Description of Reference Numerals

[0030] 1: substrate; 1a: surface; 10: first table portion; 11: first semiconductor layer; 12: second semiconductor layer; 13: third semiconductor layer; 20: second table portion; 31: anti-etching pattern; 35: first contact hole; 36: second contact hole; 41: first electrode portion; 42: second electrode portion; 43: wiring portion; 50: passivation film; 100: infrared light receiving element; 101a: first flat portion; 101b: first side surface; 102a: second flat portion; 102b: second side surface; 103b: third side surface. DETAILED DESCRIPTION

[0031] Hereinafter, an infrared light receiving element 100 involved in one embodiment of the present disclosure will be described using the accompanying drawings. Here, the infrared light emitting element 200 can be formed by the same structure as the infrared light receiving element 100 described below. That is, the structure of the infrared light receiving element 100 described in the present embodiment can be directly set as the structure of the infrared light emitting element 200. In other words, in the present embodiment, the infrared light receiving element 100 is representatively used to illustrate the structure of these infrared devices. In addition, the infrared light emitting element 200 can be manufactured by the same method as the manufacturing method of the infrared light receiving element 100 described later. That is, the manufacturing method of the infrared light receiving element 100 described later can be directly set as the manufacturing method of the infrared light emitting element 200, and the manufacturing method of the infrared device is described together.

[0032] In the figures described below, the same reference numerals are used for corresponding parts, and the description in the following description is appropriately omitted for the repeated parts. In addition, this embodiment illustrates the structure for concretizing the technical idea of ​​the present disclosure, and the material, shape, structure, configuration, size, etc. of each part are not specified as follows. The technical idea of ​​the present disclosure can be added with various changes within the scope of the technology specified by the claims recorded in the claims.

[0033] <Infrared light receiving element>

[0034] (1) Structure

[0035] Figure 1 1 is a cross-sectional view showing a structural example of an infrared light receiving element 100 according to an embodiment of the present disclosure (hereinafter referred to as the present embodiment). Figure 1As shown, the infrared light receiving element 100 comprises: a first terrace portion 10, which is arranged on a side of one surface (hereinafter referred to as the surface) 1a of the substrate 1; a second terrace portion 20, which is arranged on the side of the surface 1a of the substrate 1 and below the first terrace portion 10; an insulating film 30, which continuously covers the first terrace portion 10 and the second terrace portion 20; a first electrode portion 41, which is bonded to the upper surface of the second terrace portion 20 through a first contact hole 35 provided in the insulating film 30; a second electrode portion 42, which is bonded to the upper surface of the first terrace portion 10 through a second contact hole 36 provided in the insulating film 30; and a wiring portion 43, which is formed integrally with the first electrode portion 41 and the second electrode portion 42. Here, in Figure 1 1 shows a state where a passivation film 50 covering the infrared light receiving element 100 is provided on the surface 1a side of the substrate 1. The passivation film 50 is an insulating protective film. Here, the boundary surface between the first terrace portion 10 and the second terrace portion 20 is sometimes referred to as the lower surface of the first terrace portion 10. Figure 1 , the lower surface of the first stage portion 10 is shown by a dotted line.

[0036] Figure 2 1 is a cross-sectional view schematically showing a structural example of the first terrace portion 10 and the second terrace portion 20 of the infrared light receiving element 100. The first terrace portion 10 includes: an upper portion 111 of a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 stacked on the first semiconductor layer 11, and a third semiconductor layer 13 of a second conductivity type stacked on the second semiconductor layer 12. Here, the second semiconductor layer 12 is an active layer for photoelectric conversion. The first semiconductor layer 11 and the third semiconductor layer 13 are a combination of a p-type semiconductor layer and an n-type semiconductor layer. The order of stacking the p-type semiconductor layer and the n-type semiconductor layer is not particularly limited. Here, the phrase "stacked on the first semiconductor layer 11" related to the second semiconductor layer 12 means that the second semiconductor layer 12 is formed on the first semiconductor layer 11, but the situation where there are other layers between the first semiconductor layer 11 and the second semiconductor layer 12 is also included in the expression. When expressing the relationship between other layers, the same meaning is also obtained when the phrase "on" is used. For example, another semiconductor layer 132 may be included between the third semiconductor layer 13 and the second semiconductor layer 12. In addition, the second mesa portion 20 includes the lower portion 112 of the first semiconductor layer 11.

[0037] The materials of the first semiconductor layer 11, the second semiconductor layer 12 and the third semiconductor layer 13 are not limited. The first semiconductor layer 11, the second semiconductor layer 12 and the third semiconductor layer 13 may include materials such as Al, P, Ga, As, In, Sb, etc. In addition, the ratio of each element can be appropriately adjusted.

[0038] The first mesa portion 10 of the infrared receiving element 100 includes, in order from the substrate 1 side toward the upper direction, a first flat portion 101a, a first side surface 101b, a second side surface 102b, a third side surface 103b, and a second flat portion 102a.

[0039] The angle formed between the first flat portion 101 a and the surface 1 a of the substrate 1 is greater than or equal to 0° and less than 0.6°. The extension line of the first flat portion 101 a is the boundary between the upper portion 111 and the lower portion 112 of the first semiconductor layer 11 .

[0040] From the viewpoint of coverage of the insulating film 30 and the first electrode portion 41 , it is preferable that no corrosion hole having a diameter of 1 μm or more exists on the first flat portion 101 a .

[0041] When the angle between the first side surface 101b and the surface 1a of the substrate 1 is set to a first angle θ1, the first angle θ1 is greater than or equal to 0.6° and less than 45°. The first side surface 101b is formed only by a portion of the side surface of the upper portion 111 of the first semiconductor layer 11. The first side surface 101b is located on the side close to the lower surface of the first mesa portion 10.

[0042] When the angle formed by the second side surface 102b and the surface 1a of the substrate 1 is set to the second angle θ2, the second angle θ2 is greater than or equal to 45° and less than or equal to 90°. The second side surface 102b is composed of another part of the side surface of the upper part 111 of the first semiconductor layer 11, the entire side surface of the second semiconductor layer 12, and a part of the side surface of the third semiconductor layer 13. In other words, the second semiconductor layer 12 as an active layer is in a shape that is completely surrounded by the second side surface 102b.

[0043] When the angle between the third side surface 103 b and the surface 1 a of the substrate 1 is defined as a third angle θ3, the third angle θ3 is greater than or equal to 0.6° and less than 45°. The third side surface 103 b is formed only by another portion of the side surface of the third semiconductor layer 13 .

[0044] The angle formed between the second flat portion 102 a and the surface 1 a of the substrate 1 is not less than 0° and less than 0.6°. The second flat portion 102 a is the uppermost portion of the first terrace portion 10 .

[0045] Thus, the first terrace portion 10 has an inclined shape having at least two flat portions and three steps.

[0046] The length of the second side surface 102b in the direction parallel to the surface 1a of the substrate 1 is set to W2, and the length of the third side surface 103b in the direction parallel to the surface 1a of the substrate 1 is set to W3. Here, in order to increase the volume of the second semiconductor layer 12 as the active layer to improve the light receiving efficiency, it is sufficient to increase θ2 and reduce W2. In addition, in the manufacturing process of the infrared light receiving element 100, in order to improve the coverage of the insulating film 30 and the wiring part 43 on the upper part of the first terrace part 10, it is sufficient to reduce θ3 and increase W3. Therefore, if W3 / W2 is increased, the light receiving efficiency and the coverage of the insulating film 30 and the wiring part 43 can be improved at the same time. W3 / W2 of the infrared light receiving element 100 involved in this embodiment is 0.15 or more. There is no particular restriction on the upper limit value, but from the viewpoint of the manufacturing process, it can be less than 1.0 or less than 0.65.

[0047] The length of the first side surface 101b in a direction parallel to the surface 1a of the substrate 1 is set to W1. Here, if W1 increases, the distance between the first contact hole 35 formed on the first flat portion 101a and the second semiconductor layer 12 as the active layer is separated, the proportion of the volume of the active layer occupied by the infrared light receiving element 100 is reduced, and the light receiving efficiency is reduced. Here, if W1 / W2 is reduced, the proportion of the volume of the active layer occupied by the infrared light receiving element 100 can be increased to improve the light receiving efficiency. On the other hand, if W1 / W2 is extremely reduced, the coverage of the insulating film 30 deteriorates, so it is preferred that W1 / W2 is greater than 0.1. The infrared light receiving element 100 involved in this embodiment has W1 / W2 of greater than 0.2 and less than 3.0. Here, the description of the above light receiving efficiency is the same as the description of the light emitting efficiency of the infrared light emitting element 200 having the same structure as the infrared light receiving element 100.

[0048] If θ2 is increased and W2 is decreased, the light receiving efficiency is improved. On the other hand, if θ2 is increased, the coverage of the insulating film 30 and the wiring portion 43 of the second side surface 102b is reduced. Therefore, it is preferred that θ2 is greater than 45° and less than 75°. The θ2 of the infrared light receiving element 100 involved in this embodiment can be greater than 45° and less than 75°.

[0049] The shape of the second stage portion 20 provided below the first stage portion 10 is not particularly limited. Any shape may be used from the second stage portion 20 to the substrate 1 .

[0050] (2) Manufacturing method

[0051] Next, explain Figure 2 A method for manufacturing the infrared receiving element 100 is shown.

[0052] Figure 3A , Figure 3B as well as Figure 3C It is a cross-sectional view showing the method of manufacturing the infrared receiving element 100 according to the present embodiment in order of steps.

[0053] (2.1) Semiconductor stacking process

[0054] like Figure 3A As shown, first, a first semiconductor layer 11 of a first conductivity type is formed on the surface side of a substrate 1. Next, an intrinsic second semiconductor layer 12 is formed on the first semiconductor layer 11. Then, a third semiconductor layer 13 of a second conductivity type is formed on the second semiconductor layer 12. That is, the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 are formed in this order on the substrate 1. The formation of the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 is continuously performed, for example, in a chamber of an epitaxial growth device while maintaining a predetermined vacuum degree.

[0055] (2.2) First surface forming process

[0056] Then, if Figure 3B As shown, a resist pattern 31 is formed on the third semiconductor layer 13 using photolithography. A hard mask such as SiO2 may be formed on the third semiconductor layer 13 before a masking step for forming a mask for the resist pattern 31, so that the resist pattern 31 does not directly contact the third semiconductor layer 13.

[0057] Next, using the resist pattern 31 as a mask, the third semiconductor layer 13, the second semiconductor layer 12, and the upper portion 111 of the first semiconductor layer 11 are sequentially subjected to dry etching. In the dry etching process, a first etching step in which the inter-electrode voltage in the dry etching device is set to 330V or more and a second etching step in which the inter-electrode voltage is set to 120V or more and less than 330V are successively performed. Figure 3C As shown, the first mesa portion 10 is formed. Then, the voltage between electrodes in the etching device in the first etching step is represented as V1, and the voltage between electrodes in the etching device in the second etching step is represented as V2.

[0058] In the process of forming the first terrace portion 10, as an etching gas for etching the third semiconductor layer 13, the second semiconductor layer 12, and the upper portion 111 of the first semiconductor layer 11, any one of a halogen gas and a gas containing a halogen in combination (hereinafter referred to as a halogen-based gas), or a mixed gas thereof is used. As an example of a halogen gas, chlorine gas (Cl2) can be cited. Alternatively, as an example of a halogen-based gas, hydrogen chloride gas (HCl), hydrogen bromide gas (HBr), etc. can be cited.

[0059] In the manufacturing method of the infrared light receiving element 100 involved in this embodiment, since the etching gas does not contain an oxidizing gas such as oxygen, the selectivity of the resist and the semiconductor layer can be improved in the etching process of forming the first terrace portion 10 to prevent the disappearance of the resist in the etching process.

[0060] exist Figure 3D Shown in Figure 3C The details of the shape of the first terrace portion 10. If V1 is high, θ2 can be increased, that is, W2 can be reduced. In addition, if V2 is low, W3 can be increased.

[0061] [Comparative Example 1]

[0062] Figure 4 : is an electron microscope photograph showing a cross section of an infrared light receiving element 100 in which a first terrace portion 10 is formed. In Comparative Example 1, a film of an n-type semiconductor layer, an intrinsic semiconductor layer, and a p-type semiconductor layer of InSb with a total thickness of 3.6 μm is formed on a GaAs substrate, and a photoresist "THMR-ip5700HP" manufactured by Tokyo Ohka Kogyo Co., Ltd. is applied to a thickness of 3.5 μm, and a photoresist pattern is formed by exposure. After that, V1 is set to 740 V, and a first etching process is performed using chlorine gas, and a second etching process is performed using chlorine gas while continuously maintaining V2 at 740 V without changing the inter-electrode voltage in the dry etching device. In electron microscope observation, Helios650 manufactured by FEI Company was used, and observation was performed at a magnification of 20,000 times using an acceleration voltage of 2.0 kV.

[0063] Figure 5 The solid line shows the extraction using the image processing software "ImageJ" (using open source software, version 1.52u17) Figure 4 The result is the shape of the surface of the first stage portion 10. Here, as a process of extracting the shape, the following [1], [2], [3] and [4] are implemented.

[0064] [1] Implement Find Edges processing to emphasize sharp brightness changes in electron microscope images.

[0065] [2] Gaussian Blur processing is performed to smooth the image. At this time, the standard deviation of the Gaussian function can be set to an arbitrary value according to the electron microscope photograph.

[0066] [3] Threshold processing is performed and Clear processing is performed on unnecessary areas other than the extracted shape, and only the extracted shape is designated as the foreground color.

[0067] [4] Implement Analyze Line Graph processing to obtain the coordinate information of the extracted shape specified as foregroundcolor.

[0068] in addition, Figure 5 The dotted line indicates a result of differentiating the shape of the extracted surface of the first terrace portion 10 with respect to a direction parallel to the surface 1 a of the substrate 1 (hereinafter referred to as a differential value of the shape).

[0069] Here, since the first side surface 101b in the first terrace portion 10 is a portion where the first angle θ1 is greater than or equal to 0.6° and less than 45°, the first side surface 101b in the first terrace portion 10 is a portion from a point where the differential value of the shape relative to the direction of the first terrace portion 10 is greater than 0.01 (tan(0.6°)) for the first time to a point greater than 1 (tan(45°)). The second side surface 102b in the first terrace portion 10 is located on the upper side of the first side surface 101b and is a portion where the second angle θ2 is greater than or equal to 45° and less than 90°, and therefore, the second side surface 102b in the first terrace portion 10 is a portion from the end point of the first side surface 101b to a point where the differential value of the shape is less than 1. The third side surface 103b in the first table portion 10 is located on the upper side of the second side surface 102b and is a portion where the third angle θ3 is greater than or equal to 0.6° and less than 45°. Therefore, the third side surface 103b in the first table portion 10 is a portion between the end point of the second side surface 102b and a point where the differential value of the shape is less than or equal to 0.01 with respect to the direction of the first table portion 10. In this way, the start and end points of the first side surface 101b, the second side surface 102b, and the third side surface 103b can be clearly determined using the differential value of the shape.

[0070] The ratio of the length W2 of the second side surface 102b in the direction parallel to the surface 1a of the substrate 1 to the length W3 of the third side surface 103b in the direction parallel to the surface 1a of the substrate 1, i.e., W3 / W2, obtained through the above process, is 0.14. In addition, the ratio of W2 to the length W1 of the first side surface 101b in the direction parallel to the surface 1a of the substrate 1, i.e., W1 / W2, is 0.90.

[0071] [Example 1]

[0072] The infrared light receiving element 100 was obtained by the same method as in Comparative Example 1 except that V2 was set to 190V.

[0073] Figure 6 is an electron microscope photograph showing a cross section of the infrared light receiving element 100. Figure 7The solid line shows the image processing software ImageJ, which was used to extract the Figure 6 The shape of the surface of the first stage portion 10 is obtained as a result. Figure 7 The dotted line is the result of differentiating the shape of the surface of the first terrace portion 10 extracted with respect to the direction parallel to the surface 1a of the substrate 1. At this time, when W3 / W2 is obtained by the same process as in Comparative Example 1, W3 / W2 is 0.51. In addition, when W1 / W2 is obtained, W1 / W2 is 1.06.

[0074] [Comparative Example 2]

[0075] Figure 8 The black triangles are the following results: The infrared light receiving element 100 was made by the same method as in Comparative Example 1, and the surface shape was extracted by scanning the first stage surface 10 just after dry etching using a laser microscope OLS4000 manufactured by OLYMPUS, and the result of W3′ / W2′ was obtained. The first stage surface 10 was scanned using a 100x objective lens. The photography mode was performed under the conditions of the high-precision mode. The W3′ / W2′ obtained by measuring with a laser microscope with V2 set to 740V was 1.86.

[0076] Infrared receiving element 100 was obtained in the same manner as in Comparative Example 2 except that V2 was set to 450 V and 330 V. At this time, W3' / W2' measured with a laser microscope when V2 was set to 450 V and 330 V was 1.63 and 1.71.

[0077] [Example 2]

[0078] The infrared light receiving element 100 was obtained in the same manner as in Comparative Example 2 except that V2 was set to 190 V and 120 V, and W3′ / W2′ was calculated by a laser microscope in the same manner as in Comparative Example 2. At this time, W3′ / W2′ when V2 was set to 190 V and 120 V was 2.29 and 2.57.

[0079] According to the results of Comparative Example 2 and Example 2 ( Figure 8 It can be seen from the black triangle and dotted line that when V2 is set to 330V or more, W3′ / W2′ does not depend on V2, but when V2 is 120V or more and less than 330V, W3′ / W2′ has a negative correlation with V2 and increases linearly ( Figure 8 Here, when considering the result of W3 / W2 obtained from the electron microscope photograph in Comparative Example 1 ( Figure 8When V2 is 330V or more, W3 / W2 is 0.14. In addition, when considering the result of W3 / W2 obtained from the electron microscope photograph in Example 1, when V2 is less than 330V, W3 / W2 is at least 0.15 or more. In addition, since W3 / W2 has a negative correlation with V2 and increases linearly in the range of V2 being 120V or more and less than 330V, it can be calculated that W3 / W2 is 0.65 ( Figure 8 That is, when V2 is greater than or equal to 120 V and less than 330 V, W3 / W2 is greater than or equal to 0.15 and less than or equal to 0.65.

[0080] Fig.9A , Fig. 9B The following is a result obtained by comparing the shape of the first terrace portion 10 when V2 shown in Comparative Example 1 is set to 740 V and 190 V (electron microscope photographs in the figure) with the shape of the first terrace portion 10 when V2 is set to 190 V and 120 V (white lines in the figure). In this way, if V2 is set to 120 V or more and less than 330 V, W3 / W2 can be increased.

[0081] In any of the above embodiments, θ2 is greater than or equal to 45° and less than or equal to 75°. Fig. 9B In the case where V2 is set to 190 V, θ2 is 54°.

[0082] In any of the above-described embodiments, the surface of the first mesa portion 10 was flat, and no corrosion holes with a diameter of 1 μm or more, which are called etching pits introduced when the mesa shape is formed by wet etching, were observed.

[0083] <Effects of the present embodiment>

[0084] The infrared light receiving element 100 according to the present embodiment achieves the following effects.

[0085] like Figure 2 As shown, the second semiconductor layer 12 as an active layer is included in the steeply inclined second side surface 102b, so that the volume of the second semiconductor layer 12 can be increased. Therefore, the efficiency of photoelectric conversion can be increased, thereby improving the infrared light receiving efficiency.

[0086] In addition, since the gently inclined third side surface 103 b is located at the uppermost portion of the first terrace portion 10 , coverage (ie, step coverage) of the insulating film 30 and the wiring portion 43 on the upper portion of the first terrace portion 10 can be improved.

[0087] In addition, the ratio of the length W3 formed by the third side surface 103b located on the upper part of the first terrace portion 10 in the direction parallel to the surface 1a of the substrate 1 to the length W2 formed by the second side surface 102b in the direction parallel to the surface 1a of the substrate 1, that is, W3 / W2, is greater than or equal to 0.15 and less than or equal to 0.65, so that the ratio of the volume occupied by the active layer of the infrared light receiving element 100 can be increased. Therefore, the efficiency of photoelectric conversion can be increased, thereby improving the infrared light receiving efficiency.

[0088] In addition, the ratio of the length W1 formed by the first side surface 101b located at the lower part of the first terrace portion 10 in the direction parallel to the surface 1a of the substrate 1 to the length W2 formed by the second side surface 102b in the direction parallel to the surface 1a of the substrate 1, that is, W1 / W2, is greater than or equal to 0.2 and less than or equal to 3.0, so that the ratio of the volume occupied by the active layer of the infrared light receiving element 100 can be increased. Therefore, the efficiency of photoelectric conversion can be increased, thereby improving the infrared light receiving efficiency.

[0089] The infrared light emitting element 200 according to the present embodiment having the same structure as the infrared light receiving element 100 also achieves the above-mentioned effects as the infrared light receiving element 100. However, the “light receiving efficiency” in the above-mentioned effects is replaced by “light emitting efficiency”.

Claims

1. An infrared device, characterized in that: A first mesa portion is provided, wherein the first mesa portion includes: a first semiconductor layer of a first conductivity type provided on one surface side of a substrate; a second semiconductor layer which is an active layer stacked on the first semiconductor layer; and a third semiconductor layer of a second conductivity type stacked on the second semiconductor layer, The side surface of the first table portion includes: a first side surface located at a side of the first table portion close to the lower surface; a second side surface located at an upper portion than the first side surface; and a third side surface located at an upper portion than the second side surface. A first angle formed between the first side surface and the upper surface of the substrate is greater than 0.6° and less than 45°, a second angle formed between the second side surface and the upper surface of the substrate is greater than 45° and less than 90°, and a third angle formed between the third side surface and the upper surface of the substrate is greater than 0.6° and less than 45°. When the length of the first side surface in a direction parallel to the surface of the substrate is set to W1, the length of the second side surface in a direction parallel to the surface of the substrate is set to W2, and the length of the third side surface in a direction parallel to the surface of the substrate is set to W3, W3 / W2 is greater than 0.15, and W1 / W2 is greater than 0.1 and less than 3.

0.

2. The infrared device according to claim 1, characterized in that: The first side surface is a portion of the side surface of the upper portion of the first semiconductor layer. The second side surface is another part of the side surface of the upper part of the first semiconductor layer, the entire side surface of the second semiconductor layer, and a part of the side surface of the third semiconductor layer. The third side surface is another portion of the side surface of the third semiconductor layer.

3. The infrared device according to claim 1 or 2, characterized in that: The W3 / W2 is greater than or equal to 0.15 and less than or equal to 1.

4. The infrared device according to claim 1 or 2, characterized in that: The W3 / W2 is greater than or equal to 0.15 and less than or equal to 0.

65.

5. The infrared device according to claim 1 or 2, characterized in that: The second angle is greater than or equal to 45° and less than or equal to 75°.

6. The infrared device according to claim 1 or 2, characterized in that: The W1 / W2 is greater than or equal to 0.2 and less than or equal to 3.

0.

7. The infrared device according to claim 1 or 2, characterized in that: The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are semiconductor layers containing Al, P, Ga, As, In, or Sb.

8. The infrared device according to claim 1 or 2, characterized in that: The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are In compounds.

9. The infrared device according to claim 1 or 2, characterized in that: No etching hole having a diameter of 1 μm or more exists on the first flat portion of the surface provided at the lower portion of the first semiconductor layer.

10. The infrared device according to claim 1 or 2, characterized in that: An angle formed between a first flat portion provided on a surface of a lower portion of the first semiconductor layer and the upper surface of the substrate is greater than or equal to 0° and less than 0.6°.

11. The infrared device according to claim 1 or 2, characterized in that: An angle formed between a second flat portion provided at the uppermost portion of the first mesa portion and the upper surface of the substrate is greater than or equal to 0° and less than 0.6°.

12. The infrared device according to claim 1 or 2, characterized in that: The infrared device is at least one of an infrared light emitting element and an infrared light receiving element.

13. A method for manufacturing an infrared device, characterized in that: Including the following processes: forming a first semiconductor layer of a first conductivity type on one surface side of a substrate; forming a second semiconductor layer as an active layer on the first semiconductor layer; forming a third semiconductor layer of the second conductivity type on the second semiconductor layer; In a first etching step, dry etching is performed at an inter-electrode voltage of 330 V or more to form a first terrace portion including an upper portion of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; and In the second etching step, dry etching is performed at an inter-electrode voltage of less than 330V.

14. The method for manufacturing an infrared device according to claim 13, characterized in that: In the second etching step, dry etching is performed at an inter-electrode voltage of 120V or more and less than 330V.

15. The method for manufacturing an infrared device according to claim 13 or 14, characterized in that: A masking step of forming a resist pattern as a mask on the third semiconductor layer is further provided between the step of forming the third semiconductor layer and the first etching step.

16. The method for manufacturing an infrared device according to claim 15, characterized in that: The mask is a resist layer or a hard mask.

17. The method for manufacturing an infrared device according to claim 13 or 14, characterized in that: The etching gas in the first etching step and the second etching step is any one of a halogen gas and a halogen-based gas, or a mixed gas thereof.

18. The method for manufacturing an infrared device according to claim 17, characterized in that: The halogen gas is chlorine gas, and the halogen-based gas is hydrogen chloride gas or hydrogen bromide gas.

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