A memristor emulator circuit

Abstract

The present invention discloses a memristor emulator circuit, comprising a voltage feedback operational amplifier A, a field effect transistor M, a resistor R1, a resistor RD, a capacitor C, a positive voltage source Vp, and a negative voltage source Vn. i They are respectively connected to the "+" terminal of op amp A and one end of resistor RD. The other end of resistor RD is connected to the drain D terminal of field effect transistor M. The source S terminal of field effect transistor M is grounded. The gate G terminal of field effect transistor is respectively connected to the output terminal of op amp A and one end of capacitor C. The other end of capacitor C is respectively connected to the "-" terminal of op amp A and one end of resistor R1. The other end of resistor R1 is grounded.

Description

Technical Field

[0001] The invention relates to a memristor simulation model and belongs to the field of circuit design. Background Art

[0002] In 1971, Chua, based on symmetry theory, deduced the existence of a fourth basic circuit element—the memristor—in addition to resistor R, inductor L, and capacitor C. Theoretical research on memristors continued until 2008, when HP Labs discovered the first physical nanoscale memristor with a Pt-TiO2-Pt sandwich structure. Memristors have the potential to realize integrated storage and computing devices, making them one of the most powerful devices for breaking through the "memory wall" between CPU and memory in existing computer architectures. Furthermore, memristors are also one of the optimal choices for the physical realization of synapses in brain-inspired neural networks. These two key advantages of memristors have attracted countless researchers to conduct memristor research. Since there are no publicly available physical memristor devices for sale, memristor emulator circuits have become a key tool for many memristor researchers in their research and teaching. Existing memristor emulator circuits can generally be divided into digital and analog types. Digital memristor emulator circuits simulate memristor characteristics by controlling the voltage and current of the memristor emulator using discrete methods, such as FPGAs or microcontrollers. A disadvantage of digital memristor emulator circuits is that the maximum operating frequency of the memristor is limited by the system clock frequency and sampling frequency. Analog memristor emulator circuits can be divided into passive analog memristor circuits (composed of passive components) and active analog memristor circuits (composed of active devices). The disadvantages of passive analog memristor emulator circuits are low operating frequency and difficulty in constructing nonlinear resistors. Active analog memristor emulator circuits, while operating at a much higher frequency than passive analog memristor emulator circuits, have complex topologies and are difficult to control. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to realize an active analog memristor emulator circuit using a simple circuit topology. The memristor emulator circuit uses a voltage feedback op amp A to construct a non-inverting integrator to realize the input signal v i The output of op amp A is v g By controlling the conductive channel resistance between the drain D and source S of the field effect transistor, the simulation of the memristor is realized.

[0004] The present invention adopts the following technical solutions to solve the above technical problems:

[0005] A memristor emulator circuit includes an operational amplifier A, a field effect transistor M, a resistor R1, a resistor RD, a capacitor C, a positive voltage source Vp, and a negative voltage source Vn;

[0006] Input vi They are respectively connected to the "+" terminal of op amp A and one end of resistor RD, the other end of resistor RD is connected to the drain D terminal of field effect tube M, the source S terminal of field effect tube M is grounded, the gate G terminal of field effect tube is respectively connected to the output terminal of op amp A and one end of capacitor C, the other end of capacitor C is respectively connected to the "-" terminal of op amp A and one end of resistor R1, and the other end of resistor R1 is grounded.

[0007] Furthermore, the op amp A, resistor R1, capacitor C, positive voltage source Vp, and negative voltage source Vn form a pair of input v i The output of the non-inverting integrator

[0008] Furthermore, the equivalent resistance between the drain D and source S of the field effect tube M when the conductive channel is turned on is affected by v g control.

[0009] Furthermore, the FET drain current i i It includes the current in the conductive channel between the drain D terminal and the source S terminal of the field effect transistor and the current in the parasitic diode between the drain D terminal and the source S terminal of the field effect transistor and the substrate.

[0010] Furthermore, when inputting v i is a sinusoidal signal, the drain current i of the field effect tube M i With the input signal v i The relationship curve shows the characteristics of a hysteresis loop.

[0011] Furthermore, when inputting v i is a sinusoidal signal, the drain current i of the field effect tube M i With the input signal v i The relationship curve will change with the input signal v i As the frequency increases, it gradually shrinks and eventually shrinks into a single-valued function curve.

[0012] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0013] 1. The memristor emulator circuit has a simple topology and is easy to implement;

[0014] 2. The working process of the memristor emulator circuit is easy to analyze and control;

[0015] 3. The field effect transistor M in the memristor emulator circuit can be a P-channel or N-channel field effect transistor;

[0016] 4. The “+” input current of the op amp in the memristor emulator resistor is negligible compared to the memristor input current ii. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a memristor emulator circuit;

[0018] Figure 2 Yes When V, v i (t),i i (t),v g (t) waveform;

[0019] Figure 3 Yes When f=25kHz, 30kHz and 35kHz, i i (t)~v i (t) waveform.

[0020] Figure 4 Yes When v i (t),i i (t),v g (t) waveform;

[0021] Figure 5 Yes When f=40kHz, 50kHz and 70kHz, i i (t)~v i (t) waveform. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0023] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless defined as such, will not be interpreted in an idealized or overly formal sense.

[0024] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings.

[0025] Example 1

[0026] Take op amp A as OPA187, R1 as 2kΩ, C as 20pF, positive voltage source Vp=10V, negative voltage source Vn=-10V, field effect tube M as P-channel MOSFET 3N163, RD as 100Ω. When v i (t),i i (t),v g The waveform of (t) is as follows Figure 2 shown.

[0027] Output of op amp A:

[0028]

[0029] The drain current of the field effect transistor i i It mainly consists of two parts: the first part of the current is the current i in the conductive channel when the conductive channel between the drain D and the source S of the field effect tube M is turned on. c The second part of the current is the parasitic diode current i between the drain D of the field effect transistor M and the substrate (which is connected to the source S of the field effect transistor M). d .

[0030] According to the IV relationship formula of P-channel field effect tube, it can be known that when v g >V th When c =0; when v g ≤V th When the field effect tube is in the variable resistance area:

[0031] i c =k p *(v g -i c *RS-V th )[v i -i c *(RD+RD2+RS)]-0.5*kp*[v i -i c *(RD+RD2+RS)] 2 ;

[0032] When v g ≤V th When the field effect tube is in the saturation region:

[0033] i c =0.5*k p *(v g -i c *RS-V th ) 2 .

[0034] Here, V th is the threshold voltage of field effect tube M (3N163), k p is the transconductance coefficient of the field effect transistor M, RD2 is the drain body resistance of the field effect transistor M, and RS is the source body resistance of the field effect transistor M.

[0035] According to the IV relationship formula of the diode, it can be known that the current i in the parasitic diode between the drain D end of the field effect transistor M and the substrate (which is connected to the source S end of the field effect transistor M) is d for:

[0036]

[0037] Here, I s is the reverse saturation leakage current of the diode, v d is the forward voltage drop of the diode, V T Take 26mV at room temperature.

[0038] The final FET drain current is:

[0039] i i =i c +i d .

[0040] In taking When f=25kHz, 30kHz and 35kHz, i i (t)~v i The waveform of (t) is as follows Figure 3 As shown. On the one hand, i i (t)~v i The waveform of (t) shows the characteristics of pinch hysteresis curve; on the other hand, as the input signal v i The frequency changes from 25kHz to 30kHz and finally increases to 35kHz, i i (t)~v i The waveform of (t) is finally compressed into a single-valued function curve. The above two aspects can show that this circuit is a memristor emulator circuit.

[0041] Example 2

[0042] Take op amp A as OPA187, R1 as 2kΩ, C as 20pF, positive voltage source Vp=10V, negative voltage source Vn=-10V, field effect tube M as N-channel MOSFET RK7002BM, RD as 30Ω. When v i (t),i i (t),v g The waveform of (t) is as follows Figure 4 As shown. When f=40kHz, 50kHz and 70kHz, i i (t)~v i The waveform of (t) is as follows Figure 5 shown.

[0043] Output of op amp A:

[0044]

[0045] The drain current of the field effect tube i i It mainly consists of two parts: the first part of the current is the current i in the conductive channel when the conductive channel between the drain D and the source S of the field effect tube M is turned on. c The second part of the current is the parasitic diode current i between the source S of the field effect transistor M and the substrate (which is connected to the source S of the field effect transistor M). d .

[0046] According to the IV relationship formula of N-channel field effect tube, it can be known that when v g <V th When c =0; when v g ≥V th When the field effect tube is in the variable resistance area:

[0047] i c =k n *(v g -i c *RS-V th )[v i -i c *(RD+RD2+RS)]-0.5*k n *[v i -i c *(RD+RD2+RS)] 2 ;

[0048] When v g ≥V th When the field effect tube is in the saturation region:

[0049] i c =0.5*k n *(v g -i c *RS-V th ) 2 .

[0050] Here, V th is the threshold voltage of field effect tube M (RK7002BM), k n is the transconductance coefficient of the field effect transistor M, RD2 is the drain body resistance of the field effect transistor M, and RS is the source body resistance of the field effect transistor M.

[0051] According to the IV relationship formula of the diode, it can be known that the current i in the parasitic diode between the source D end of the field effect tube and the substrate (which is connected to the source S end of the field effect tube M) is d for:

[0052]

[0053] Here, I s is the diode reverse saturation leakage current, v d is the forward voltage drop of the diode, V T Take 26mV at room temperature.

[0054] The final FET drain current is:

[0055] i i =i c +i d .

[0056] In taking When f=40kHz, 50kHz and 70kHz, i i (t)~v i The waveform of (t) is as follows Figure 5 As shown. On the one hand, i i (t)~v i The waveform of (t) shows the characteristics of pinch hysteresis curve; on the other hand, as the input signal v i The frequency changes from 40kHz to 50kHz and finally increases to 70kHz, i i (t)~v i The waveform of (t) is finally compressed into a single-valued function curve. The above two aspects can show that this circuit is a memristor emulator circuit.

[0057] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technology can understand and think of any changes or replacements within the technical scope disclosed by the present invention, which should be included in the scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A memristor emulator circuit, characterized in that: Including operational amplifier A, field effect tube M, resistor R1, resistor RD, capacitor C, positive voltage source Vp, negative voltage source Vn; The input vi is connected to the "+" terminal of the operational amplifier A and one end of the resistor RD respectively. The other end of the resistor RD is connected to the drain D terminal of the field effect transistor M. The source S terminal of the field effect transistor M is grounded. The gate G terminal of the field effect transistor is connected to the output terminal of the operational amplifier A and one end of the capacitor C respectively. The other end of the capacitor C is connected to the "-" terminal of the operational amplifier A and one end of the resistor R1 respectively. The other end of the resistor R1 is grounded. Operational amplifier A, resistor R1, capacitor C, positive voltage source Vp, and negative voltage source Vn form a non-inverting integrator for input vi. The output of the non-inverting integrator is The equivalent resistance of the conductive channel between the drain D and source S of the field effect transistor M when it is turned on is controlled by vg.

2. A memristor emulator circuit according to claim 1, characterized in that: The field effect transistor drain current ii includes the current in the conductive channel between the field effect transistor drain D terminal and the source S terminal and the current in the parasitic diode between the field effect transistor drain D terminal and the source S terminal to the substrate.

3. The memristor emulator circuit according to claim 1, wherein: When the input vi is a sinusoidal signal, the relationship curve between the drain current ii of the field effect transistor M and the input signal vi shows a hysteresis loop feature.

4. The memristor emulator circuit according to claim 1, wherein: When the input vi is a sinusoidal signal, the relationship curve between the drain current ii of the field effect transistor M and the input signal vi will gradually shrink as the frequency of the input signal vi increases, and eventually shrink into a single-valued function curve.

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