Reading method, three-dimensional memory and memory system

Abstract

Embodiments of the present invention relate to a reading method, a three-dimensional memory, and a memory system, wherein the three-dimensional memory includes one or more memory pages and one or more word lines respectively coupled to the one or more memory pages; each memory page contains one or more memory cells, and the reading method includes: when performing a read operation on a memory cell of a selected word line, determining whether the read operation is a first read operation; when the read operation is the first read operation, applying a first pulse voltage to the selected word line before applying a read voltage to the selected word line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This invention is based on the Chinese patent application with application number 202011531516.0 and application date of December 22, 2020, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this application by introduction. Technical Field

[0003] The present invention relates to the field of memory technology, and in particular to a three-dimensional memory reading method, a three-dimensional memory, and a memory system. Background Art

[0004] As technology advances, the semiconductor industry continues to seek new production methods to increase the number of memory cells per memory die in memory devices. In non-volatile memory devices, such as NAND memory, one approach to increasing memory density is through the use of vertical memory arrays, known as 3D NAND (three-dimensional NAND) memory. With increasing levels of integration, 3D NAND memory has evolved from 32 layers to 64 layers, and even higher.

[0005] As market demands for storage density continue to increase, the industry is developing programming methods with more programming states, allowing each physical memory cell to represent more bits of information. However, achieving more programming states places higher demands on the formation process of individual memory cells and the uniformity of the distribution of multiple memory cells. Therefore, how to increase the storage density of memory cells and improve the performance of three-dimensional memory is a pressing technical challenge.

[0006] In enterprise-level three-dimensional memories (such as 3D NAND), low-density parity-check (LDPC) codes are often used for error correction. Figure 1 This is a flowchart of LDPC error correction. Figure 1 As shown in Figure 2, these error correction codes inevitably lead to additional read time delays and a degradation in overall storage performance, especially for soft-decoding. Therefore, reducing the Fail Bit Count (FBC) is particularly important.

[0007] Temporary Read Errors (TER) are a new threat to 3D NAND reliability. They occur when a large number of transient read errors (FBC) occur during the first read of a 3D NAND Flash memory after a period of idle time following programming or reading. This results in a high FBC, which stabilizes in the second and third reads. Figure 2A and Figure 2B Schematic diagrams of FBC with multiple reads without idle time from the end of programming to the first read and FBC with multiple reads with idle time from the end of programming to the first read. Figure 2A is the FBC for three reads without idle time, Figure 2B This is the FBC at the time of five reads after 24 hours of idle time. Figure 2A and Figure 2B As shown, the first read issue (FRI) is strongly correlated with the idle time before reading. FRI does not occur when reading is performed directly after programming without idle time. However, FRI occurs when reading is performed after 24 hours after programming, and is most severe when reading the first word line (WL). Figure 3 This is a schematic diagram of a conventional transient read error (TER) (cited from C. Zambelli, R. Micheloni, S. Scommegna and P. Olivo, "First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State"). Figure 3 As shown, the first reading phenomenon ( Figure 3 w / TER) will greatly increase the probability of triggering soft decision decoding in LDPC, resulting in a decrease in the overall performance of the memory. Summary of the Invention

[0008] Embodiments of the present invention provide a three-dimensional memory reading method, a three-dimensional memory, and a memory system, which can at least reduce the failure bit count during the first reading operation.

[0009] In one aspect, an embodiment of the present invention provides a method for reading a three-dimensional memory, wherein the three-dimensional memory includes one or more memory pages and one or more word lines respectively coupled to the one or more memory pages; each memory page includes one or more memory cells, and the reading method includes:

[0010] When performing a read operation on a memory cell of a selected word line, determining whether the read operation is a first read operation;

[0011] When the read operation is the first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line.

[0012] In another aspect, an embodiment of the present invention provides a three-dimensional memory, including:

[0013] A memory array, the memory array comprising one or more memory pages; each of the memory pages comprising one or more memory cells;

[0014] one or more word lines respectively coupled to the one or more memory pages;

[0015] and a peripheral circuit coupled to the plurality of word lines and configured to control the memory array; wherein,

[0016] The peripheral circuit is configured to: when performing a read operation on a memory cell of a selected word line, determine whether the read operation is a first read operation;

[0017] When the read operation is the first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line.

[0018] In a third aspect, an embodiment of the present invention further provides a memory system, including a three-dimensional memory, wherein the three-dimensional memory includes:

[0019] A memory array, wherein the memory array includes one or more memory pages; each memory page includes one or more memory cells;

[0020] one or more word lines respectively coupled to the one or more memory pages;

[0021] and a peripheral circuit coupled to the one or more word lines and configured to control the memory array; wherein the peripheral circuit is configured to: when performing a read operation on a memory cell of a selected word line, determine whether the read operation is a first read operation; and when the read operation is the first read operation, apply a first pulse voltage to the selected word line before applying a read voltage to the selected word line;

[0022] and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, wherein:

[0024] Figure 1 It is a flow chart of LDPC error correction;

[0025] Figure 2A and Figure 2B Schematic diagrams of an FBC for multiple reads with no idle time between the end of programming and the first read and an FBC for multiple reads with idle time between the end of programming and the first read;

[0026] Figure 3 is a schematic diagram of an existing transient read error (TER);

[0027] Figures 4 and 5 is a schematic diagram of transient read errors in different programming states during the first read;

[0028] Figure 6 A schematic diagram of a reading method of a three-dimensional memory in a TLC programming mode;

[0029] Figure 7 is a schematic diagram of the physical mechanism of transient read errors during the first read;

[0030] Figure 8 is a flow chart of a method for reading a three-dimensional memory according to an embodiment of the present invention;

[0031] Figure 9 is a schematic diagram of a method for reading a three-dimensional memory according to an embodiment of the present invention;

[0032] Figure 10 A schematic diagram of a failure bit count of a three-dimensional memory reading method;

[0033] Figure 11 is a circuit diagram of an exemplary three-dimensional memory 100 including peripheral circuits according to some aspects of an embodiment of the present invention;

[0034] Figure 12 is a side view of a cross section of an exemplary memory array 1101 including NAND memory strings 1108 according to aspects of the present invention;

[0035] Figure 13 is a block diagram of an exemplary memory including a memory array and peripheral circuits according to aspects of the present invention;

[0036] Figure 14 A schematic diagram of the structure of a memory system provided by an embodiment of the present invention;

[0037] Figure 15 is a block diagram of an exemplary data system 300 having a three-dimensional memory 100 according to some aspects of the present invention;

[0038] FIG. 16(A) is a diagram of an exemplary memory card having three-dimensional memory 100 according to aspects of the present invention;

[0039] FIG. 16(B) is a diagram of an exemplary solid-state drive (SSD) having a three-dimensional memory 100 according to aspects of the present invention. DETAILED DESCRIPTION

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, the drawings described below are merely examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without inventive effort. Unless otherwise apparent from the context or otherwise noted, the same reference numerals in the figures represent the same structure or operation.

[0041] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0042] As used in this application and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not intended to refer to the singular but may include the plural. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0043] Unless otherwise specifically stated, the relative arrangement of the parts and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to actual proportional relationships. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed here, any specific values ​​should be interpreted as being merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0044] When describing the embodiments of the present invention, for ease of explanation, cross-sectional views illustrating device structures may be partially enlarged and not to scale. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0045] In the description of this application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of this application; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0046] For ease of description, spatial relational terms such as "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of the element described as "below" or "below" or "below" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both the up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), so the spatial relational descriptors used herein should be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0047] In the context of the present application, a description of a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be understood that when a component is referred to as being “on,” “connected to,” “coupled to,” or “contacting” another component, it can be directly on, connected to, coupled to, or contacting the other component, or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly contacting” another component, there are no intervening components present.

[0049] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is solely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. Furthermore, while the terms used in this application are selected from commonly known and commonly used terms, some terms mentioned in this specification may have been selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant sections of this description. Furthermore, this application should be understood not only by the actual terms used, but also by the meaning implied by each term.

[0050] 3D memory can experience numerous transient read errors during the first read after a period of idle time following programming, verification, and read operations. These transient errors disappear during the second or third read, performed a short time later. The fault bit count during the first read can be several times higher than during the second read. This phenomenon severely impacts the reliability of 3D memory. While methods like low-density parity check (LDPC) can address the high fault bit count, they significantly increase power consumption and impact the overall device quality of service (QoS).

[0051] Figures 4 and 5 FIG. 1 is a schematic diagram of a transient read error when reading different logical pages for the first time in the TLC programming mode of a three-dimensional memory. Figure 6 The present invention is a schematic diagram of the sequence of applying a read voltage to a selected word line coupled to a certain memory page during a read operation in a TLC programming mode of a three-dimensional memory. It should be noted that: Figure 6The schematic diagram of the order of applying the read voltage shown in the figure corresponds to a Gray code encoding. When the Gray code encoding is used, for the three-dimensional memory TLC programming mode, the binary codes mapped to the eight data states are as follows: (111) corresponds to the erased state; (110) corresponds to the first programming state; (100) corresponds to the second programming state; (000) corresponds to the third programming state; (010) corresponds to the fourth programming state; (011) corresponds to the fifth programming state; (001) corresponds to the sixth programming state; and (101) corresponds to the seventh programming state. The three-bit binary code can be named from left to right as the most significant bit (MSB), the middle significant bit (CSB), and the least significant bit (LSB). For example, the binary code corresponding to the fifth programming state is (011), where the MSB is "0", the CSB is "1", and the LSB is "1". In some embodiments, the memory is read in units of memory pages, and in the TLC programming mode, each memory page has a logic low page (LowerPage), a logic middle page (MiddlePage), and a logic high page (UpperPage), as shown in Table 1. That is, when reading each memory page in the TLC programming mode, three logical pages need to be read, and the reading order can be reading the logic low page, reading the logic middle page, and reading the logic high page. According to such a reading order, the order of applying the read voltage to the selected word line coupled to a certain memory page can be as follows: Figure 6 As shown, the logic low page is first read by reading P1 and P5, and the first read voltage for reading P1 and the fifth read voltage for reading P5 need to be applied to the selected word line; then the logic middle page is read by reading P2, P4 and P6, and the second read voltage for reading P2, the fourth read voltage for reading P4 and the sixth read voltage for reading P6 need to be applied to the selected word line; finally, the logic high page is read by reading P3 and P7, and the third read voltage for reading P3 and the seventh read voltage for reading P7 need to be applied to the selected word line.

[0052] It should be understood that in actual application, other forms of encoding methods can also be used to program the memory, and the reading order corresponding to different encoding methods may also be different. In other words, Figure 6 The reading order shown is only an example.

[0053] Table 1

[0054] Er P1 P2 P3 P4 P5 P6 P7 Logical low page 1 0 0 0 0 1 1 1 Logic Middle Page 1 1 0 0 1 1 0 0 Logical high page 1 1 1 0 0 0 1 0

[0055] refer to Figures 4 to 6 As shown, in Figure 6In the storage encoding scheme shown, transient read errors during the first read are particularly severe when reading the logic-low page of the three-dimensional memory TLC programming mode, especially in the fifth programming state (P5). This is because, compared to reading other programming states, the previous read operation for reading the P5 state is the first programming state (P1). When reading P1, a negative voltage is applied to the control gate of the selected word line. This negative voltage causes more grain boundary traps (GBTs) to release electrons, resulting in a larger number of failed bits and more severe transient read errors during the first read.

[0056] Figure 7 This is a diagram of the physical mechanism of transient read errors during first read. Figure 7 As shown in the figure, immediately after programming a memory cell, the quasi-Fermi level approaches the conduction band due to the high gate voltage, resulting in a 50% probability of traps being occupied at the Fermi level. According to the Fermi-Dirac function, below the Fermi level, the closer to the valence band, the greater the probability of trap occupation. At time t0, most of the traps in the polysilicon channel are filled. During the idle time from t0 to t1, the gate voltage becomes floating, eventually dropping to 0V. This causes the quasi-Fermi level to shift downward, releasing electrons from the polysilicon traps, leaving them empty. Therefore, at time t1, when the first read begins, there are many empty traps. The threshold voltage for reading at this time is low, resulting in a high number of failed bit counts. After the first read, the traps are refilled, and the polysilicon trap population is now closer to the state immediately after programming. The failed bit count during this read returns to normal, significantly different from the failed bit count during the first read. Furthermore, if a negative voltage is applied to the control gate of the selected word line, the Fermi level moves further away from the conduction band, which in turn exacerbates the release of electrons from the traps, exacerbating transient read errors during the first read. Therefore, an optimized readout method for 3D memory is particularly important.

[0057] To address the above technical issues, the following embodiments of the present invention provide a reading method of a three-dimensional memory and a three-dimensional memory, so as to at least reduce the failure bit count during the first reading operation.

[0058] Figure 8 The flowchart of a method for reading a three-dimensional memory according to an embodiment of the present invention is shown. Figure 9 This is a schematic diagram of a method for reading a three-dimensional memory according to an embodiment of the present invention. Figure 8 and Figure 9 It is understood that the following description is merely exemplary, and those skilled in the art may make various changes without departing from the spirit of the present invention.

[0059] refer to Figure 8 As shown, a three-dimensional memory of the present invention includes one or more memory pages and one or more word lines respectively coupled to the one or more memory pages. Each memory page includes one or more memory cells. Based on this, the reading method includes:

[0060] When performing a read operation on a memory cell of a selected word line, determining whether the read operation is a first read operation;

[0061] When the read operation is the first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line.

[0062] Here, the selected word line is the word line to which the memory page desired to be read is coupled.

[0063] It should be noted that this reading method is applicable to any type of memory cell. In other words, the memory cells in a memory page can be any type of SLC, MLC, TLC, or QLC. When performing a read operation on the memory cells of a selected word line, a determination is made as to whether the read operation is the first read operation. If the read operation is the first read operation, a first pulse voltage is applied to the selected word line before applying a read voltage to the selected word line. In some embodiments, the first pulse voltage is a positive voltage. This allows electrons released from traps in long-term idle memory cells in the memory page coupled to the selected word line to be refilled into the traps before the first read operation is performed on the three-dimensional memory, thereby effectively improving transient read errors during the first read.

[0064] In some embodiments, determining whether the read operation is the first read operation may include:

[0065] determining an idle time between a previous execution of a first operation on the three-dimensional memory and a previous execution of the read operation on the three-dimensional memory; wherein the first operation is the same as or different from the read operation;

[0066] It is determined whether the read operation is the first read operation based on the idle time.

[0067] In some embodiments, the first operation may include one of the following: programming, verification, or reading. Alternatively, the first operation may be any other operation on the three-dimensional memory. For example, the first operation performed on the three-dimensional memory is a power-on operation. That is, the first operation performed on the three-dimensional memory before performing the read operation is a power-on operation. That is, the three-dimensional memory is idle for a period of time after being powered on before performing the read operation.

[0068] In some embodiments, determining whether the read operation is the first read operation based on the idle time may include:

[0069] Determining whether the idle time is greater than or equal to the first time;

[0070] When it is determined that the idle time is greater than or equal to the first time, determining that the read operation is a first read operation;

[0071] When it is determined that the idle time is less than the first time, it is determined that the read operation is not the first read operation.

[0072] That is, in one embodiment of the present invention, the above-mentioned reading method further includes determining whether the reading operation is the first reading operation according to the idle time of the three-dimensional memory before the reading operation.

[0073] Exemplarily, when the idle time is greater than or equal to the first time, the read operation may be determined to be the first read operation. When it is determined that the idle time is less than the first time, the read operation may not be determined to be the first read operation.

[0074] Preferably, in an embodiment of the present invention, the first time is 12 hours. For example, if the idle time of the three-dimensional memory before the read operation is greater than or equal to 12 hours, the read operation is determined to be the first read operation.

[0075] In some embodiments, determining whether the read operation is the first read operation may also include:

[0076] determining a gate voltage applied to the selected word line when a first operation was previously performed on the three-dimensional memory;

[0077] It is determined whether the read operation is a first read operation based on the gate voltage.

[0078] In some embodiments, determining whether the read operation is a first read operation based on the gate voltage includes:

[0079] Determining whether the gate voltage is a negative voltage;

[0080] When the gate voltage is a negative voltage, the read operation is determined to be a first read operation.

[0081] Here, when the gate voltage applied to the selected word line during the first operation previously performed on the three-dimensional memory is a negative voltage, the current read operation can also be considered the first read operation because it also has the transient read error phenomenon. When the gate voltage is not negative (for example, a positive voltage), the read operation is determined not to be the first read operation, that is, the current read operation is not considered the first read operation.

[0082] As previously explained, the reading method provided by the embodiments of the present invention is applicable to any type of memory cell. In some embodiments, the memory cells of the selected word line are triple-level cells (TLCs). In other words, in one embodiment of the present invention, the programming mode of the 3D memory is triple-level cell (TLC). The TLC programming mode is 3 bits / cell, meaning each memory cell stores 3 bits of data.

[0083] In some embodiments, the memory cells of the selected word line include different first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6 and seventh programming state P7.

[0084] It should be noted that, as described above, a TLC type memory cell has 8 data states, one erased state and 7 programmed states, which can be divided into a logic high page, a logic middle page and a logic low page to store 3 bits of data.

[0085] In some embodiments, when the memory cells of the selected word line are encoded according to the Gray code shown in Table 1, the order of applying the read voltage pulses to the selected word line to read the memory cells of the selected word line may be as follows: Figure 6 At this point, in some embodiments, when reading the logic lower page of the memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the reading method further includes:

[0086] applying the first pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line;

[0087] The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

[0088] It should be noted that when the read operation is the first read operation, it is necessary to read the first programming state P1 and the fifth programming state P5 when reading the logic low page in the storage cell of the selected word line, that is, it is necessary to first apply the first read voltage for reading P1 to the selected word line of the storage cell coupled to the selected word line. Because in some embodiments, in some examples, when reading the first programming state P1, the first read voltage applied to the control gate of the selected word line of the three-dimensional memory is a negative voltage; when reading the fifth programming state P5, the fifth read voltage applied to the control gate of the selected word line of the three-dimensional memory is a positive voltage, that is: the first read voltage for reading P1 may be a negative voltage; the fifth read voltage for reading P5 is a positive voltage. Based on Figure 7 After the three-dimensional memory is idle for a period of time, the threshold voltage corresponding to the memory cell shifts to a smaller value. When reading P1 again, the first read voltage is a negative voltage, resulting in a lower corresponding threshold voltage before reading P5, resulting in a larger number of fault bit counts when reading P5. Therefore, in order to solve this problem, in this case, the embodiment of the present invention applies the first pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line when reading the logic low page of the memory cell of the selected word line. For details, see Figure 9 shown.

[0089] In some examples, the magnitude of the first pulse voltage may be 2-7 V. The duration of the first pulse voltage may be 5-15 μs.

[0090] Preferably, the first pulse voltage is greater than the read voltage applied to the selected word line.

[0091] Optionally, the first pulse voltage is 2 V, and the read voltage is 1.41 V. The read voltage may be the fifth read voltage mentioned above.

[0092] It should be understood that those skilled in the art can make corresponding adjustments to the magnitude and duration of the first pulse voltage according to actual needs, and the present invention is not limited thereto.

[0093] In one embodiment of the present invention, the magnitude of the first pulse voltage is greater than the read voltage of the highest state in the programming state. Figure 9 In one example shown, the magnitude of the first pulse voltage may also be greater than the highest voltage in the programming state (the seventh read voltage of the seventh programming state P7 ).

[0094] In one embodiment of the present invention, the duration of the first pulse voltage is shorter than the duration of the read voltage required for reading any programming state of the memory cells of the selected word line, that is, the duration of the first pulse voltage is shorter than the duration of any programming state. Specifically, the duration of the first pulse voltage is shorter than the duration of the read voltage for reading any programming state: the first read voltage for reading the first programming state P1, the fifth read voltage for reading the fifth programming state P5, the second read voltage for reading the second programming state P2, the fourth read voltage for reading the fourth programming state P4, the sixth read voltage for reading the sixth programming state P6, the third read voltage for reading the third programming state P3, and the seventh read voltage for reading the seventh programming state P7.

[0095] According to an embodiment of the present invention, after applying a first pulse voltage between reading the first programming state P1 and reading the fifth programming state P5, a trap that releases electrons in the first programming state P1 after the previous read state recaptures electrons, thereby reducing the number of failed bits when reading the fifth programming state P5 during the first read operation of the three-dimensional memory, thereby optimizing transient read errors during the first read.

[0096] It will be appreciated that in some examples of the present invention (e.g. Figure 9 In an example shown), the above reading order includes reading the first programming state P1, reading the fifth programming state P5, reading the second programming state P2, reading the fourth programming state P4, reading the sixth programming state P6, reading the third programming state P3 and reading the seventh programming state P7 in this order.

[0097] It should be noted that according to Figure 9 In the reading sequence shown, when the memory cell of the selected word line is read for the first time, the reading of the logical middle page and the logical high page is not the first time the read voltage is applied to the selected word line. At this time, the time interval between the two readings is relatively short, and the threshold voltage of the memory cell caused by TER will not shift downward. Therefore, when reading the second programming state P2, the fourth programming state P4, the sixth programming state P6, the third programming state P3, and the seventh programming state P7, it is not necessary to apply a positive pulse voltage before reading.

[0098] Figure 9 This is just an example. Different encoding methods of the three-dimensional memory may correspond to different reading orders. For different reading orders, TER will occur when the three-dimensional memory is read for the first time, and thus FBC will be relatively high. In this case, a positive pulse voltage needs to be applied to the control gate of the selected word line when performing the first read operation to refill the lost electrons into the traps of the memory cell, thereby effectively improving the transient read error during the first read.

[0099] Figure 10This is a schematic diagram of the failure bit count of a three-dimensional memory read method. Figure 10 As shown, during the idle time before the first read operation, the gate voltage Vg on the word line is kept floating and 2V, respectively. It is not difficult to see that when performing the first read operation on the three-dimensional memory, the fault bit count when reading the fifth programming state P5 is more serious than when reading other programming states. Moreover, when the control gate voltage of the selected word line is kept at 2V (the first pulse voltage), the fault bit count when reading the fifth programming state P5 is significantly reduced compared to when the control gate voltage of the selected word line is floating (i.e., Vg = 0V). Compared to reading other programming states, keeping the control gate voltage of the selected word line at 2V has a large optimization space and a better optimization effect for reading the fifth programming state P5. That is, in one embodiment of the present invention, the first pulse voltage is a positive pulse.

[0100] Combine Figure 7 As shown, the first pulse voltage can induce empty traps to recapture electrons, mitigating the increased electron release from traps caused by applying a negative voltage to the selected line when reading the first programming state P1 in the aforementioned example. Applying the first pulse voltage to the selected word line is particularly important for mitigating the first time read artifact (FRI) when reading the fifth programming state P5. This is the state with the most severe FRI among TLC programming states using the encoding scheme in Table 1. Resolving FRI when reading the fifth programming state P5 will significantly improve FRI for the entire 3D memory in the TLC programming mode.

[0101] On the other hand, if the time since the last programming / reading during the reading operation is not long, that is, the idle time is short, the first pulse voltage can be omitted because the transient read error during the first reading can be repaired by error correction control coding (ECC) such as low-density parity check code.

[0102] In an embodiment of the present invention, when the first operation is a read operation, the reading method may further include:

[0103] When performing an Nth read operation on a memory cell of the selected word line, determining a time interval between performing the Nth read operation on the three-dimensional memory and performing an N-1th read operation on the three-dimensional memory;

[0104] When determining whether the time interval is greater than or equal to the second time;

[0105] When the time interval is greater than or equal to a second time, before performing the Nth read operation on the three-dimensional memory, applying a second pulse voltage to the selected word line;

[0106] When the time interval is less than the second time, the read voltage is directly applied to the selected word line when the Nth read operation is performed on the three-dimensional memory; wherein N is greater than or equal to 2.

[0107] In a reading method for a three-dimensional memory having multiple read operations, in a plurality of read operations after a first read operation, if a time interval between an N-th read operation and an N-1-th read operation before the N-th read operation is greater than or equal to a second time, a second pulse voltage is applied to the selected word line before performing the N-th read operation on the three-dimensional memory, where N is greater than or equal to 2.

[0108] For example, in a reading method for a three-dimensional memory having three read operations, if the time interval between the second read operation and the first read operation is greater than or equal to a second time, then before performing the second read operation on the three-dimensional memory, a second pulse voltage needs to be applied to the selected word line. Similarly, if the time interval between the third read operation and the second read operation is greater than or equal to the second time, then before performing the third read operation on the three-dimensional memory, a second pulse voltage needs to be applied to the selected word line.

[0109] In some embodiments, when the time interval is less than the second time, the read voltage is directly applied to the selected word line when performing the Nth read operation on the three-dimensional memory, where N is greater than or equal to 2. That is, the time interval between two read operations is relatively short, and it is not necessary to apply the second pulse voltage to the selected word line before the next read operation.

[0110] In some embodiments, the memory cells included in the selected word line are triple-level cells (TLCs); the Nth read operation on the memory cells of the selected word line is performed in the following order: reading a logic low page of the memory cells of the selected word line, reading a logic middle page of the memory cells of the selected word line, and reading a logic high page of the memory cells of the selected word line; when reading the logic low page of the memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the read method further comprises:

[0111] applying the second pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line;

[0112] The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

[0113] That is, if the three-dimensional memory is programmed according to the aforementioned TLC programming mode, and the encoding method of the corresponding memory cells is in the format shown in Table 1, then when two read operations are performed, when the time interval between the two read operations is greater than or equal to the second time, the second pulse voltage is applied to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line.

[0114] For example, in a reading method for a three-dimensional memory having three read operations, if the time interval between the second read operation and the first read operation is greater than or equal to the second time, then the second read operation requires applying a second pulse voltage between reading the first programming state P1 and reading the fifth programming state P5. Similarly, if the time interval between the third read operation and the second read operation is greater than or equal to the second time, then the third read operation requires applying a second pulse voltage between reading the first programming state P1 and reading the fifth programming state P5.

[0115] It should be noted that the three-dimensional memory is programmed according to the aforementioned TLC programming mode, and the encoding method of the corresponding storage unit is in the form shown in Table 1. The reading order when performing a read operation on the three-dimensional memory is as follows: Figure 6 shown.

[0116] In one embodiment of the present invention, the second time period is 12 hours. That is, in a plurality of read operations after the first read operation, if the time interval between two adjacent read operations is greater than or equal to 12 hours, the corresponding read operations require applying a second pulse voltage between the first programming state P1 and the fifth programming state P5.

[0117] In one embodiment of the present invention, the magnitude and / or duration of the second pulse voltage is the same as that of the first pulse voltage.

[0118] In one embodiment of the present invention, the duration of the second pulse voltage is shorter than that of the first pulse voltage.

[0119] In some examples, the magnitude of the second pulse voltage can be 2-7 V. The duration of the second pulse voltage can be 5-15 μs. By applying the first pulse voltage between reading the first programming state P1 and reading the fifth programming state P5 in the first read operation, or applying the second pulse voltage between reading the first programming state P1 and reading the fifth programming state P5 in subsequent read operations, interference caused by electrons released from grain boundary traps when a negative voltage is applied to the control gate of the selected word line when reading the previous programming state can be suppressed, thereby optimizing the problem of a significant increase in the number of failed bits caused by electrons released from grain boundary traps that occur before reading.

[0120] The above embodiments of the present invention provide a method for reading a three-dimensional memory, which can reduce the failure bit count during the first read operation.

[0121] Another aspect of the present invention provides a three-dimensional memory that can reduce a failure bit count when performing a first read operation or two read operations with a time interval greater than a second time.

[0122] Figure 11 This is a diagram of the architecture of a three-dimensional memory according to an embodiment of the present invention. Figure 11 The three-dimensional memory provided by the embodiment of the present invention is described. It should be understood that the following description is merely exemplary, and those skilled in the art may make various changes without departing from the spirit of the present invention.

[0123] like Figure 11 FIG. 1 shows a circuit diagram of an exemplary three-dimensional memory 100 including peripheral circuits according to some aspects of an embodiment of the present invention. Figure 11 The three-dimensional memory 100 provided by the embodiment of the present invention may include a memory array 1101 and a peripheral circuit 1103 coupled to the memory array 1101. Specifically, Figure 11 As shown, the three-dimensional memory 100 may include:

[0124] A memory array 1101, wherein the memory array 1101 includes one or more memory pages; each of the memory pages includes one or more memory cells;

[0125] One or more word lines 1102 respectively coupled to the one or more memory pages 1120;

[0126] and a peripheral circuit 1103 coupled to the one or more word lines and configured to control the memory array; wherein,

[0127] The peripheral circuit is configured to: when performing a read operation on a memory cell of a selected word line, determine whether the read operation is a first read operation;

[0128] When the read operation is the first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line.

[0129] In some embodiments, determining whether the read operation is the first read operation includes:

[0130] determining an idle time between a previous execution of a first operation on the three-dimensional memory and a previous execution of the read operation on the three-dimensional memory; wherein the first operation is the same as or different from the read operation;

[0131] It is determined whether the read operation is the first read operation based on the idle time.

[0132] In some embodiments, determining whether the read operation is the first read operation based on the idle time includes:

[0133] Determining whether the idle time is greater than or equal to the first time;

[0134] When it is determined that the idle time is greater than or equal to the first time, determining that the read operation is a first read operation;

[0135] When it is determined that the idle time is less than the first time, it is determined that the read operation is not the first read operation.

[0136] In some embodiments, determining whether the read operation is the first read operation includes:

[0137] determining a gate voltage applied to the selected word line when a first operation was previously performed on the three-dimensional memory;

[0138] It is determined whether the read operation is a first read operation based on the gate voltage.

[0139] In some embodiments, determining whether the read operation is a first read operation based on the gate voltage includes:

[0140] Determining whether the gate voltage is a negative voltage;

[0141] When the gate voltage is a negative voltage, determining that the read operation is a first read operation;

[0142] When the gate voltage is a negative voltage, it is determined that the read operation is not the first read operation.

[0143] In some embodiments, the first operation includes one of: programming or verifying or reading.

[0144] In some embodiments, the first time is 12 hours.

[0145] In some embodiments, the memory cells of the selected word line are triple-level cells (TLCs).

[0146] In some embodiments, the memory cells of the selected word line include different first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6 and seventh programming state P7.

[0147] In some embodiments, when reading a logic lower page of memory cells of the selected word line by applying a first read voltage for reading a first program state to the selected word line and applying a fifth read voltage for reading a fifth program state to the selected word line, the reading method further includes:

[0148] applying the first pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line;

[0149] The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

[0150] In some embodiments, when reading a logic low page of memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the peripheral circuit is further configured to: sequentially apply the first read voltage to the selected word line, apply the first pulse voltage to the selected word line; and apply the fifth read voltage to the selected word line;

[0151] The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state. That is, the first pulse voltage is applied to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line.

[0152] In some embodiments, the first read voltage is a negative voltage; and the fifth read voltage is a positive voltage.

[0153] In some embodiments, the first pulse voltage is greater than the read voltage applied to a selected word line.

[0154] In some embodiments, the first pulse voltage is 2 volts; and the read voltage is 1.41 volts.

[0155] In some embodiments, when the first operation is a read operation, the peripheral circuit may be further configured as follows:

[0156] When performing an Nth read operation on a memory cell of the selected word line, determining a time interval between performing the Nth read operation on the three-dimensional memory and performing an N-1th read operation on the three-dimensional memory;

[0157] When determining whether the time interval is greater than or equal to the second time;

[0158] When the time interval is greater than or equal to a second time, before performing the Nth read operation on the three-dimensional memory, applying a second pulse voltage to the selected word line;

[0159] When the time interval is less than the second time, the read voltage is directly applied to the selected word line when the Nth read operation is performed on the three-dimensional memory; wherein N is greater than or equal to 2.

[0160] In some embodiments, the memory cells included in the selected word line are triple-level cells (TLCs); the Nth read operation on the memory cells of the selected word line is performed in the following order: reading a logic low page of the memory cells of the selected word line, reading a logic middle page of the memory cells of the selected word line, and reading a logic high page of the memory cells of the selected word line; when reading the logic low page of the memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the control voltage is further configured as follows:

[0161] applying the second pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line;

[0162] The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

[0163] In some embodiments, the memory array is a three-dimensional NAND array.

[0164] It should be noted that the operations performed by the three-dimensional memory provided by the embodiment of the present invention have been explained in detail in the reading method provided by the aforementioned embodiment of the present invention, and each term and step are also applicable here and will not be repeated.

[0165] In some embodiments, as previously described, memory array 1101 may be a NAND flash memory cell array, wherein memory cells 1106 are provided in the form of an array of NAND memory strings 1108, each NAND memory string 1108 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 1108 includes a plurality of memory cells 1106 coupled in series and stacked vertically. Each memory cell 1106 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 1106. Each memory cell 1106 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0166] In some embodiments, each memory cell 1106 may be a single-level cell (SLC) having two possible memory states and thus can store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 1106 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell. In some embodiments, three bits are stored per memory cell 1106 (also known as a triple-level cell (TLC)), or four bits are stored per memory cell 1106 (also known as a quad-level cell (QLC)). Each MLC may be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from an erased state by writing one of the three possible nominal storage values ​​to the memory cell. A fourth nominal storage value may be used for the erased state. In another example, if each TLC stores three bits of data, the TLC has seven programmed states and one erased state, and can be encoded in the encoding manner shown in Table 1 above.

[0167] like Figure 11 As shown in FIG, each NAND memory string 1108 may include a source select gate (SSG) 1110 at its source terminal and a drain select gate (DSG) 1112 at its drain terminal. The SSG 1110 and the DSG 1112 may be configured to activate a selected NAND memory string 1108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 1108 in the same block 1104 are coupled via the same source line (SL) 1214 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 1108 in the same block 1104 have an array common source (ACS). According to some embodiments, the DSG 1112 of each NAND memory string 1108 is coupled to a corresponding bit line 1116, from which data may be read or written via an output bus (not shown). In some embodiments, each NAND memory string 1108 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG 1112) or a deselect voltage (e.g., 0 V) ​​to a corresponding DSG 1112 via one or more DSG lines 1113 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG 1110) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG 1110 via one or more SSG lines 1115.

[0168] like Figure 11 As shown in FIG, a NAND memory string 1108 can be organized into a plurality of blocks 1104, each of which can have a common source line 1114 (e.g., coupled to ground). In some embodiments, each block 1104 is a basic data unit for an erase operation, i.e., all memory cells 1106 on the same block 1104 are erased simultaneously. To erase the memory cells 1106 in a selected block 1104, the source lines 1114 coupled to the selected block 1104 and to unselected blocks 1104 in the same plane as the selected block 1104 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of a block. The memory cells 1106 of adjacent NAND memory strings 1108 can be coupled by word lines 1102, which select which row of memory cells 1106 is affected by read and programming operations. In some embodiments, each word line 1102 is coupled to a memory page 1120 of memory cells 1106, which is the basic data unit for programming operations. The size of a memory page 1120 in bits can be related to the number of NAND memory strings 1108 coupled by word lines 1102 in a block 1104. Each word line 1102 may include multiple control gates (gate electrodes) at each memory cell 1106 in the corresponding memory page 1120 and gate lines coupling the control gates. It should be noted that embodiments of the present invention Figure 11 Memory cells of a selected word line in the provided three-dimensional memory 100 may include one or more memory pages 1120 .

[0169] Figure 12 1 shows a side view of a cross section of an exemplary memory array 1101 including NAND memory strings 1108 according to aspects of the present invention. Figure 12 , NAND memory strings 1108 can extend vertically through a memory stack 1204 over a substrate 1202. The substrate 1202 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0170] The memory stack 1204 may include alternating gate conductive layers 1206 and gate-to-gate dielectric layers 1208. The number of pairs of gate conductive layers 1206 and gate-to-gate dielectric layers 1208 in the memory stack 1204 may determine the number of memory cells 1106 in the memory array 1101. The gate conductive layers 1206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 1206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 1206 includes a doped polysilicon layer. Each gate conductive layer 1206 may include a control gate surrounding the memory cell 1106 and may extend laterally as a DSG line 1113 at the top of the memory stack layer 1204, extend laterally as an SSG line 1115 at the bottom of the memory stack layer 1204, or extend laterally between the DSG line 1113 and the SSG line 1115 as a word line 1102.

[0171] like Figure 12 As shown in FIG, NAND memory string 1108 includes a channel structure 1212 extending vertically through memory stack layer 1204. In some embodiments, channel structure 1212 includes a channel hole filled with one or more semiconductor materials (e.g., as semiconductor channel 1220) and one or more dielectric materials (e.g., as memory film 1218). In some embodiments, semiconductor channel 1220 includes silicon, such as polysilicon. In some embodiments, memory film 1218 is a composite dielectric layer including a tunneling layer 1226, a storage layer 1224 (also referred to as a "charge trapping / storage layer"), and a barrier layer 1222. Channel structure 1212 can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, semiconductor channel 1220, tunneling layer 1226, storage layer 1224, and barrier layer 1222 are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. Tunneling layer 1226 can include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 1224 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 1222 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 1218 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0172] According to some embodiments, Figure 12As shown in FIG, a well 1214 (e.g., a P-well and / or an N-well) is formed in the substrate 1202, and the source terminal of the NAND memory string 1108 is in contact with the well 1214. For example, a source line 1114 can be coupled to the well 1214 to apply an erase voltage to the well 1214 (i.e., the source of the NAND memory string 1108) during an erase operation. In some embodiments, the NAND memory string 1108 also includes a channel plug 1216 at the drain terminal of the NAND memory string 1108. It should be understood that although Figure 13 Not shown, but additional features of the memory array 1101 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0173] Return Reference Figure 11 , the peripheral circuit 1103 may be coupled to the memory array 1101 via the bit line 1116, the word line 1102, the source line 1114, the SSG line 1115, and the DSG line 1113. The peripheral circuit 1103 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 1101 by applying a voltage signal and / or a current signal to each target memory cell 1106 and sensing a voltage signal and / or a current signal from each target memory cell 1106 via the bit line 1116, the word line 1102, the source line 1114, the SSG line 1115, and the DSG line 1113. The peripheral circuit 1103 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 13 Some exemplary peripheral circuits are shown, and the peripheral circuit 1103 includes a page buffer / sense amplifier 1304, a column decoder / bit line driver 1306, a row decoder / word line driver 1308, a voltage generator 1310, a control logic unit 1312, a register 1314, an interface 1316, and a data bus 1318. It should be understood that in some examples, the peripheral circuit 1103 may also include Figure 14 Additional peripheral circuits not shown.

[0174] The page buffer / sense amplifier 1304 can be configured to read data from the memory array 1101 and program (write) data to the memory array 1101 based on control signals from the control logic unit 1312. In one example, the page buffer / sense amplifier 1304 can store a page of program data (write data) to be programmed into one memory page 1120 of the memory array 1101. In another example, the page buffer / sense amplifier 1304 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 1106 coupled to the selected word line 1102. In yet another example, the page buffer / sense amplifier 1304 can also sense a low-power signal from the bit line 1116 representing a data bit stored in the memory cell 1106 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 1306 can be configured to be controlled by the control logic unit 1312 and select one or more NAND memory strings 1108 by applying a bit line voltage generated by the voltage generator 1310.

[0175] The row decoder / wordline driver 1308 can be configured to be controlled by the control logic unit 1312 and to select / deselect the block 1104 of the memory array 1101 and select / deselect the wordline 1102 of the block 1104, wherein the selected wordline, also referred to as the selected wordline, is read by applying a read voltage to the selected wordline to read the memory page coupled to the selected wordline, or is programmed by applying a program voltage to the selected wordline to program the memory page. The row decoder / wordline driver 1308 can also be configured to drive the wordline 1102 using a wordline voltage generated from the voltage generator 1310. In some embodiments, the row decoder / wordline driver 1308 can also select / deselect and drive the SSG line 1115 and the DSG line 1113. For example, the row decoder / wordline driver 1308 is configured to perform an erase operation on the memory cell 1106 coupled to the selected wordline(s) 1102. The voltage generator 1310 can be configured to be controlled by the control logic unit 1312 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 1101.

[0176] The control logic unit 1312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 1314 can be coupled to the control logic unit 1312 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 1316 can be coupled to the control logic unit 1312 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 1312, as well as buffer status information received from the control logic unit 1312 and relay it to the host. The interface 1316 can also be coupled to the column decoder / bitline driver 1306 via the data bus 1318 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory array 1101. It should be noted that the interface 1316 mentioned here can include the first memory interface and / or the second memory interface described below.

[0177] Based on the structure of the three-dimensional memory described above, when performing a write operation (also known as programming) on ​​the three-dimensional memory, programming can be performed on a memory page basis, or on a single or multiple memory cells. The programming principle can be to utilize the FN tunneling efficiency to write data to the selected memory cell. Taking the selected memory cell 1106 as an example, a programming voltage VPG, e.g., approximately 20V, is applied to the word line coupled to the selected memory cell 1106 (referred to as the selected word line), while the remaining word lines (referred to as the unselected word lines) are biased to a low voltage VPS1. For example, a low voltage (e.g., 0 volts (V)) is applied to the bit line connected to the selected NAND memory string 1108, turning on the included select transistors. A high voltage (e.g., system voltage VDD) is applied to the bit lines connected to the unselected NAND memory strings 1108, turning off the included select transistors.

[0178] When performing a read operation on a three-dimensional memory, the charge level in the floating gate is determined based on the conduction state of the selected memory cell, thereby obtaining data represented by this charge level. Taking the memory page as the read unit, and taking selected memory page 1120 as an example, the word line coupled to the selected memory page 1120 (referred to as the selected word line) is biased at the read voltage Vread, while the remaining word lines (referred to as the unselected word lines) are biased at the pass voltage Vpass. The conduction state of a memory cell in the selected memory page 1120 is related to its threshold voltage, that is, the charge level in the control gate. Therefore, the data value can be determined based on the conduction state of the memory cell in the selected memory page 1120. Other memory cells in the same NAND memory string as the selected memory cell are always on when subjected to the pass voltage.

[0179] In some embodiments, the present invention also provides a memory system including the aforementioned three-dimensional memory. Figure 14 As shown, it shows a structural schematic diagram of the memory system provided by an embodiment of the present invention.

[0180] See Figure 14 The memory system 200 includes the three-dimensional memory 100 described above; and a memory controller 1402 coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0181] In some embodiments, the memory system 200 includes a three-dimensional memory, wherein the three-dimensional memory includes:

[0182] A memory array, wherein the memory array includes one or more memory pages; each memory page includes one or more memory cells;

[0183] one or more word lines respectively coupled to the one or more memory pages;

[0184] and a peripheral circuit coupled to the one or more word lines and configured to control the memory array; wherein the peripheral circuit is configured to: when performing a read operation on a memory cell of a selected word line, determine whether the read operation is a first read operation; and when the read operation is the first read operation, apply a first pulse voltage to the selected word line before applying a read voltage to the selected word line;

[0185] and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0186] In some embodiments, the memory cells of the selected word line are triple-level cells (TLCs), wherein the memory cells include different first programming states P1, second programming states P2, third programming states P3, fourth programming states P4, fifth programming states P5, sixth programming states P6, and seventh programming states P7.

[0187] In some embodiments, when reading a logic low page of memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the peripheral circuit is further configured to: sequentially apply the first read voltage to the selected word line, apply the first pulse voltage to the selected word line; and apply the fifth read voltage to the selected word line;

[0188] The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

[0189] In some embodiments, the memory system 200 further includes a first memory interface and a second storage interface, wherein the memory controller communicates with the three-dimensional controller through the first storage interface; the memory controller communicates with a host coupled to the memory system through the second communication interface.

[0190] In some embodiments, the memory system may be included in a solid-state drive (SSD) or a memory card.

[0191] It should be noted that the first storage interface and the second storage interface may be included in the aforementioned Figure 13 In interface 1316.

[0192] It should be noted that Figure 14 The memory system can also form a data storage system 200 with a host. For example, Figure 15 A block diagram of an exemplary data system 300 having three-dimensional memory according to some aspects of the present invention is shown. The data system 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 15 As shown in FIG, data system 300 may include a host 1501 and a memory system 200, wherein the memory system 200 includes one or more three-dimensional memories 100 and a memory controller 1402. Host 1501 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 1501 may be configured to send data to or receive data from the three-dimensional memory 100.

[0193] The three-dimensional memory 100 can be any three-dimensional memory disclosed herein. As disclosed in detail below, the three-dimensional memory 100 (e.g., a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory)) can have reduced leakage current from driver transistors (e.g., string drivers) coupled to unselected word lines during an erase operation, which allows for further size reduction of the driver transistors.

[0194] According to some embodiments, memory controller 1402 is coupled to 3D memory 100 and host 1501 and is configured to control 3D memory 100. Memory controller 1402 can manage data stored in 3D memory 100 and communicate with host 1501. In some embodiments, memory controller 1402 is designed for operation in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 1402 is designed for operation in high-duty-cycle environments, such as SSDs or embedded MultiMediaCards (eMMCs), which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Memory controller 1402 can be configured to control operations of 3D memory 100, such as read, erase, and program operations. The memory controller 1402 may also be configured to manage various functions related to data stored or to be stored in the three-dimensional memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the memory controller 1402 may also be configured to process error correction code (ECC) for data read from or written to the three-dimensional memory 100. The memory controller 1402 may also perform any other suitable functions, such as formatting the three-dimensional memory 100. The memory controller 1402 may communicate with an external device (e.g., the host 1501) according to a specific communication protocol. For example, the memory controller 1402 may communicate with the external device using at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, and the like.

[0195] The memory controller 1402 and one or more three-dimensional memories 100 can be integrated into various types of storage devices, for example, included in the same package (for example, a universal flash storage (UFS) package or an eMMC package). That is, the memory system 200 can be implemented and packaged into different types of terminal electronic products. In one example as shown in FIG16(A), the memory controller 1402 and a single three-dimensional memory 100 can be integrated into a memory card 1602. The memory card 1602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1602 may also include a method of connecting the memory card 1602 to a host (for example, Figure 15 In another example as shown in FIG16(B), the memory controller 1402 and the plurality of three-dimensional memories 100 may be integrated into an SSD 1606. The SSD 1606 may also include a memory card connector 1604 that couples the SSD 1606 to the host (e.g., Figure 15 In some embodiments, the storage capacity and / or operating speed of the SSD 1606 is greater than the storage capacity and / or operating speed of the memory card 1602.

[0196] It should be noted that the present invention does not limit the number and size of each component. For example, in another embodiment of the present invention, the parallel mechanism of the present invention includes more than two groups of first connecting members, second connecting members and telescopic rods. Any selection and adjustment of the number and size of each component in order to achieve the free rotation effect and meet actual production needs falls within the spirit and scope of the present invention.

[0197] It will be understood that although the above disclosure discusses some embodiments of the invention that are currently considered useful through various examples, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover all modifications and any equivalent combinations that are consistent with the spirit and scope of the embodiments of the present application.

[0198] It should be understood that the embodiments described above are merely illustrative. The embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and / or other electronic units designed to perform the functions described herein, or a combination thereof.

[0199] The basic concepts have been described above. It will be apparent to those skilled in the art that the above disclosures are merely illustrative and do not constitute limitations on this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to this application. Such modifications, improvements, and amendments are suggested in this application and remain within the spirit and scope of the exemplary embodiments of this application.

[0200] At the same time, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0201] The computer program code required for the operation of each part of the present application can be written in any one or more programming languages, including object-oriented programming languages ​​such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc., conventional procedural programming languages ​​such as C language, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, dynamic programming languages ​​such as Python, Ruby and Groovy, or other programming languages. The program code can be run entirely on the user's computer, or as a separate software package on the user's computer, or partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any network form, such as a local area network (LAN) or a wide area network (WAN), or connected to an external computer (e.g., via the Internet), or in a cloud computing environment, or used as a service such as software as a service (SaaS).

[0202] In addition, unless expressly stated in the claims, the order of the processing elements and sequences described in this application, the use of alphanumeric characters, or the use of other names are not intended to limit the order of the processes and methods of this application. Although the above disclosure discusses some of the invention embodiments currently considered useful through various examples, it should be understood that such details are only for illustrative purposes, and the attached claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover all modifications and equivalent combinations that are consistent with the essence and scope of the embodiments of this application. For example, although the system components described above can be implemented by hardware devices, they can also be implemented only by software solutions, such as installing the described system on an existing server or mobile device.

[0203] Similarly, it should be noted that, in order to simplify the description of this application and thus facilitate understanding of one or more embodiments of the application, the foregoing description of the embodiments of this application sometimes combines multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not mean that the subject matter of this application requires more features than those recited in the claims. In fact, the features of an embodiment may be fewer than all the features of the individual embodiments disclosed above.

[0204] In some embodiments, numbers are used to describe the quantity of components and attributes. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise stated, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the description and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the settings of such numerical values ​​are as accurate as possible within the feasible range.

[0205] Although the present invention has been described with reference to the current specific embodiments, those skilled in the art should recognize that the above embodiments are merely illustrative of the present invention, and that various equivalent changes or substitutions may be made without departing from the spirit of the present invention. Therefore, any changes or modifications to the above embodiments within the spirit of the present invention shall fall within the scope of the claims of this application.

Claims

1. A method for reading a three-dimensional memory, characterized in that: The three-dimensional memory includes one or more memory pages and one or more word lines respectively coupled to the one or more memory pages, each memory page including one or more memory cells; the reading method includes: When performing a read operation on a memory cell of a selected word line, determining whether the read operation is a first read operation; When the read operation is the first read operation, before applying the read voltage to the selected word line, a first pulse voltage is applied to the selected word line; the first pulse voltage is a positive voltage; The determining whether the read operation is the first read operation includes: determining a gate voltage applied to the selected word line when a first operation was previously performed on the three-dimensional memory; and determining whether the read operation is the first read operation based on the gate voltage.

2. The reading method according to claim 1, wherein: The determining, based on the gate voltage, whether the reading operation is the first reading operation includes: Determining whether the gate voltage is a negative voltage; When the gate voltage is a negative voltage, the read operation is determined to be a first read operation.

3. The reading method according to claim 1, wherein: The first operation includes one of the following: programming, verification, or reading.

4. The reading method according to claim 1, wherein: The memory cells of the selected word line are triple-level cells (TLC).

5. The reading method according to claim 4, characterized in that: The memory cells of the selected word line include different first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6 and seventh programming state P7.

6. The reading method according to claim 5, characterized in that: When reading a logic lower page of memory cells of the selected word line by applying a first read voltage for reading a first program state to the selected word line and applying a fifth read voltage for reading a fifth program state to the selected word line, the reading method further includes: applying the first pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line; The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

7. The reading method according to claim 6, characterized in that The first read voltage is a negative voltage; the fifth read voltage is a positive voltage.

8. The reading method according to claim 1, wherein: The first pulse voltage is greater than the read voltage applied to a selected word line.

9. The reading method according to claim 8, characterized in that: The first pulse voltage is 2V; the read voltage is 1.41V.

10. The reading method according to claim 1, wherein: The duration of the first pulse voltage is shorter than the duration of a read voltage required for reading any programmed state of the memory cells of the selected word line.

11. A three-dimensional memory, characterized in that: include: a memory array comprising one or more memory pages; Each memory page contains one or more memory cells; one or more word lines respectively coupled to the one or more memory pages; and a peripheral circuit coupled to the one or more word lines and configured to control the memory array; wherein, The peripheral circuit is configured to: when performing a read operation on a memory cell of a selected word line, determine whether the read operation is a first read operation, including: determining a gate voltage applied to the selected word line when a first operation was previously performed on the three-dimensional memory; and determining whether the read operation is the first read operation based on the gate voltage; When the read operation is the first read operation, before applying the read voltage to the selected word line, a first pulse voltage is applied to the selected word line; the first pulse voltage is a positive voltage.

12. The three-dimensional memory according to claim 11, wherein: The determining, based on the gate voltage, whether the reading operation is the first reading operation includes: Determining whether the gate voltage is a negative voltage; When the gate voltage is a negative voltage, the read operation is determined to be a first read operation.

13. The three-dimensional memory according to claim 11, wherein: The first operation includes one of the following: programming, verification, or reading.

14. The three-dimensional memory according to claim 11, wherein: The memory cells of the selected word line are triple-level cells (TLCs), wherein the memory cells include different first programming states P1, second programming states P2, third programming states P3, fourth programming states P4, fifth programming states P5, sixth programming states P6, and seventh programming states P7.

15. The three-dimensional memory according to claim 14, wherein: When reading a logic low page of memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the peripheral circuit is further configured to: sequentially apply the first read voltage to the selected word line and the first pulse voltage to the selected word line; applying the fifth read voltage to the selected word line; The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

16. The three-dimensional memory according to claim 11, wherein: The memory array is a three-dimensional NAND array.

17. A memory system, characterized in that: A three-dimensional memory is included, wherein the three-dimensional memory includes: A memory array, wherein the memory array includes one or more memory pages; each memory page includes one or more memory cells; one or more word lines respectively coupled to the one or more memory pages; and a peripheral circuit coupled to the one or more word lines and configured to control the memory array; wherein the peripheral circuit is configured to: when performing a read operation on a memory cell of a selected word line, determine whether the read operation is a first read operation, comprising: determining a gate voltage applied to the selected word line when a first operation was previously performed on the three-dimensional memory; determining whether the read operation is the first read operation based on the gate voltage; and when the read operation is the first read operation, applying a first pulse voltage to the selected word line before applying the read voltage to the selected word line; the first pulse voltage being a positive voltage; and a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

18. The memory system according to claim 17, wherein: The memory cells of the selected word line are triple-level cells (TLCs), wherein the memory cells include different first programming states P1, second programming states P2, third programming states P3, fourth programming states P4, fifth programming states P5, sixth programming states P6, and seventh programming states P7.

19. The memory system according to claim 18, wherein: When reading a logic low page of memory cells of the selected word line by applying a first read voltage for reading a first programming state to the selected word line and applying a fifth read voltage for reading a fifth programming state to the selected word line, the peripheral circuit is further configured to: sequentially apply the first read voltage to the selected word line and the first pulse voltage to the selected word line; applying the fifth read voltage to the selected word line; The first programming state and the fifth programming state are two programming states in the TLC, and a threshold voltage corresponding to the first programming state is lower than a threshold voltage corresponding to the fifth programming state.

20. The memory system according to claim 17, wherein: The memory system further includes a first memory interface and a second memory interface, wherein the memory controller communicates with the three-dimensional memory through the first memory interface; and the memory controller communicates with a host coupled to the memory system through the second memory interface.

21. The memory system according to any one of claims 17 to 20, wherein: Contained in a solid-state drive (SSD) or memory card.

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