dynamic random access memory

Abstract

The application discloses a dynamic random access memory, comprising a substrate, a first active region, a first isolation region, a second active region and a second isolation region are arranged continuously along a first direction. A first bit line is located on the first active region. A second bit line is located on the second isolation region. A storage node contact structure is located between the first bit line and the second bit line, and directly contacts a top surface of the second active region, a sidewall of the first isolation region and a sidewall of the second isolation region. The storage node contact structure of the application has a large contact area between the top surface of the second active region, so that the contact resistance can be reduced.

Description

Technical Field

[0001] This invention relates to a dynamic random access memory, and more particularly to a dynamic random access memory including a storage node contact structure. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that comprises an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to store data. The control circuitry addresses each memory cell and controls data access to that cell via word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] To reduce the size of memory cells and fabricate chips with higher density, memory cell structures have evolved towards three-dimensional designs, such as using buried word lines and stacked capacitors. Stacked capacitors vertically position the capacitors of the memory cell above the substrate, saving substrate area occupied by the capacitors and allowing for larger capacitances by easily increasing the height of the capacitor's electrode plates. Currently, stacked capacitors are electrically connected to transistors fabricated within the substrate via storage node contact structures. There is still a need in the art for a storage node contact structure that provides good electrical connection quality to ensure the performance of dynamic random access memory (DRAM). Summary of the Invention

[0004] One of the objectives of this invention is to provide a dynamic random access memory (DRAM) with a large contact area between its storage node contact structure and the substrate, thereby reducing contact resistance and improving the performance of the DRAM.

[0005] An embodiment of the present invention provides a dynamic random access memory (DRAM) including a substrate, and a first active region, a first isolation region, a second active region, and a second isolation region arranged continuously along a first direction. A first bit line is located on the first active region. A second bit line is located on the second isolation region. A memory node contact structure is located between the first bit line and the second bit line, and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

[0006] Another embodiment of the present invention provides a dynamic random access memory (DRAM) including a substrate and an active region located between two isolation structures. Two embedded word lines are located in the active region, dividing the active region into a middle portion and two ends. A bit line is located on the middle portion. A memory node contact structure is located on the ends, wherein the memory node contact structure includes a contact portion and a plug portion. The contact portion directly contacts a top surface of the end, a sidewall of the embedded word line, and a sidewall of the isolation structure. The plug portion is located on the contact portion and has a width greater than the width of the contact portion. Attached Figure Description

[0007] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 9 The illustration shows different stages of the manufacturing process of a dynamic random access memory according to an embodiment of the present invention, wherein... Figure 1 and Figure 4 This is a floor plan. Figure 2 , Figure 3 , Figures 5 to 9 The legends on the left are respectively along Figure 1 or Figure 4 A cross-sectional view of the AA' tangent. Figure 2 , Figure 3 , Figures 5 to 9 The legends on the right are respectively along Figure 1 or Figure 4 A cross-sectional view of the BB' tangent.

[0009] Figure 10 The diagram shown is a cross-sectional view of a dynamic random access memory according to another embodiment of the present invention.

[0010] The reference numerals in the attached figures are explained as follows:

[0011] 10 Substrates

[0012] 12 Active regions

[0013] 14. Isolation Structure

[0014] 16 Insulation layer

[0015] 16a Bottom surface

[0016] 21 First Insulation Layer

[0017] 22 Second Insulation Layer

[0018] 32 Dielectric Layer

[0019] 42 Storage Node Contact Structure

[0020] 43 bottom angle

[0021] 44. Bottom angle

[0022] 45° bottom angle

[0023] 102 Conductive Layer

[0024] 104 Insulating Cover

[0025] 106 Gate insulation layer

[0026] 202 Semiconductor Layer

[0027] 204 metal layer

[0028] 206 Hard Mask Layer

[0029] 12a First Active Region

[0030] 12a1 Middle section

[0031] 12a2 end

[0032] 12b Second Active Region

[0033] 12b' Residue

[0034] 14a First Quarantine Zone

[0035] 14b Second Quarantine Zone

[0036] 16a Bottom surface

[0037] 42a Contact section

[0038] 42b Insertion part

[0039] 42c Contact pad

[0040] A1 Area

[0041] A2 area

[0042] AA' tangent

[0043] BB' tangent

[0044] BC groove

[0045] BL bitline

[0046] BL1 First Line

[0047] BL2 Second Line

[0048] D1 direction

[0049] D2 direction

[0050] D3 direction

[0051] E1 Etching Process

[0052] E2 etching process

[0053] L1 barrier layer

[0054] M1 metal layer

[0055] R1 deep groove

[0056] S1 semiconductor layer

[0057] S1D lower part

[0058] S1T upper part

[0059] SC storage node contact hole

[0060] SP gap wall

[0061] SP1 First gap wall

[0062] SP2 Second Spacer Wall

[0063] W1 width

[0064] W2 width

[0065] WL Embedded Typeface Detailed Implementation

[0066] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0067] Figures 1 to 9The illustration is a schematic diagram of a dynamic random access memory (DRAM) according to an embodiment of the present invention during manufacturing, wherein... Figure 1 and Figure 4 This is a floor plan. Figure 2 , Figure 3 , Figures 5 to 9 The legend on the left is roughly along Figure 1 or Figure 4 A cross-sectional view of the AA' tangent. Figure 2 , Figure 3 , Figures 5 to 9 The legend on the right is roughly along Figure 1 or Figure 4 A cross-sectional view of the BB' tangent. For simplicity of illustration, Figure 1 and Figure 4 The floor plan omits some of the structure.

[0068] Please refer to Figure 1 and Figure 2 First, a substrate 10 is provided, such as a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, but not limited thereto. Next, an isolation structure 14 is formed in the substrate 10, and the isolation structure 14 defines a plurality of mutually parallel active regions 12 in the substrate 10. The isolation structure 14 includes a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but not limited thereto. The active regions 12 each have a length extending along direction D1 and are arranged in an array along directions D2 and D3, wherein directions D2 and D3 are perpendicular to each other, and direction D1 is different from directions D2 and D3. According to some embodiments of the invention, the angle between directions D1 and D3 can be between 30 degrees and 75 degrees. According to some embodiments of the invention, a heavily doped region (not shown) can be formed in the upper half of each active region 12 for forming ohmic contacts with subsequently fabricated bit line contacts and memory node contact structures. In other embodiments, alternatively, grooves forming bit line contacts (such as...) can be selected... Figure 3 The groove BC shown is followed by the contact hole of the storage node (as shown). Figure 8 After the storage node contact hole SC and deep groove R1 are formed, a heavily doped region is formed in the exposed active region 12.

[0069] After forming the isolation structure 14 and the active region 12, an insulating layer 16 may be selectively formed on the substrate 10. Then, multiple word line trenches (not shown) are formed, passing through the insulating layer 16 and extending into the substrate 10, cutting through the isolation structure 14 and the active region 12. Embedded word lines WL are then formed in the word line trenches. The embedded word lines WL extend along direction D2 and are arranged parallel to each other along direction D3. The embedded word lines WL may include a conductive layer 102 located at the lower part of the word line trench, an insulating capping layer 104 located at the upper part of the word line trench, and a gate insulating layer 106 located between the substrate 10 and the conductive layer 102 and the insulating capping layer 104. The conductive layer 102 may include a metallic material, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), a work function metal, or a compound, alloy, and / or composite layer of the aforementioned metallic materials, but is not limited thereto. The insulating layer 16, the insulating cap layer 104, and the gate insulating layer 106 may each comprise a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), a high-k dielectric material, or a combination of the above materials, but are not limited thereto. According to some embodiments of the present invention, the insulating layer 16 and the insulating cap layer 104 may comprise the same material, such as silicon nitride (SiN). Figure 1 and Figure 2 As shown, each active region 12 is divided into a middle portion 12a1 and two end portions 12a2 by two embedded word lines WL. To more clearly describe the features of the invention, the portions of the active region 12 and the isolation structure 14 cut by the AA' tangent are specifically defined as the first active region 12a, the first isolation region 14a, the second active region 12b, and the second isolation region 14b, and are indicated as follows: Figure 1 and Figure 2 In the legend on the left. (And) Figure 1 By comparing them side by side, it should be clear that... Figure 2 The first active region 12a and the second active region 12b, as shown in the left-hand diagram, are the middle and end parts of two adjacent active regions 12, respectively.

[0070] Please refer to Figure 3 Next, a mask layer (not shown) can be formed on the substrate 10, which may include multiple openings that expose the middle portion 12a1 of each active region 12. Then, an etching process is performed on the substrate 10 through these openings to etch the middle portion 12a1 of each active region 12 below the side ends 12a2, thus forming a groove BC at the location of the middle portion 12a1 of each active region 12. Figure 3As shown in the left-hand diagram, the groove BC is approximately located above the first active region 12a (the middle part), and the top surface of the first active region 12a is recessed below the top surface of the second active region 12b. A portion of the first isolation region 14a is also removed during the etching process to form part of the groove BC, so a portion of the top surface of the first isolation region 14a is lower than the top surface of the second isolation region 14b.

[0071] Please refer to Figure 4 and Figure 5 After removing the mask layer, multiple deposition processes can be performed to sequentially form a semiconductor layer 202, a metal layer 204, and a hard mask layer 206 on the substrate 10. Then, a patterning process (e.g., photolithography and etching) is performed to remove excess portions of the semiconductor layer 202, metal layer 204, and hard mask layer 206, thereby forming multiple bit lines BL on the substrate 10. The bit lines BL extend along direction D3 and are arranged parallel to each other along direction D2. The portion of the bit lines BL passing through the groove BC (or bit line contact) directly contacts and is electrically connected to the middle portion 12a1 of the active region 12. The remaining portions of the bit lines BL are separated from and electrically isolated from the active region 12 by the insulating layer 16. The material of the semiconductor layer 202 of the bit lines BL may include polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of the metal layer 204 may include aluminum (Al), tungsten (W), copper (Cu), titanium-aluminum (TiAl) alloy, or other suitable low-resistance metal materials. The hard mask layer 206 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. In some embodiments, an interface layer (not shown) may be included between the semiconductor layer 202 and the metal layer 204, such as a single-layer or multi-layer structure layer composed of titanium (Ti), tungsten silicide (WSi), tungsten nitride (WN), and / or other metal silicides or metal nitrides, but is not limited thereto. To more clearly describe the features of the invention, this document specifically refers to... Figure 5 In the left-hand diagram, the bit line BL located on the first active region 12a is defined as the first bit line BL1, and the bit line BL located on the second isolation region 14b is defined as the second bit line BL2.

[0072] Please refer to Figure 6Next, deposition and etching processes can be performed to form spacer walls SP on the sidewalls of each bit line BL, and to fill the groove BC with the spacer walls SP. According to some embodiments of the present invention, the spacer walls SP may include a multilayer structure, for example, including a first insulating layer 21 and a second insulating layer 22, wherein the first insulating layer 21 covers the sidewalls of the bit line BL and the surface of the groove BC, and the second insulating layer 22 is located on the first insulating layer 21 and fills the remaining space of the groove BC. The first insulating layer 21 and the second insulating layer 22 may each include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination of the above materials, but are not limited thereto. According to one embodiment of the present invention, the first insulating layer 21 may include silicon nitride, and the second insulating layer 22 may include silicon oxide. To more clearly describe the features of the present invention, the following are specifically mentioned herein: Figure 6 In the left-hand diagram, the gap wall SP located on the side wall of the first line BL1 is defined as the first gap wall SP1, and the gap wall SP located on the side wall of the second line BL2 is defined as the second gap wall SP2.

[0073] Please refer to Figure 7 Next, a deposition process can be performed to form a dielectric layer 32 on the substrate 10 to fill the gaps between the bit lines BL. Then, an etching process E1 (e.g., dry etching) is performed to remove a portion of the dielectric layer 32 and a portion of the insulating layer 16, forming memory node contact holes SC located between the bit lines BL and penetrating the dielectric layer 32 and the insulating layer 16 to expose the surface of the active region 12. According to some embodiments of the present invention, the etching process may use a fluorine (F)-containing gas as an etchant, such as tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (C2F2), or combinations thereof, but is not limited thereto. Figure 7 As shown in the left-hand diagram, a portion of the top surface of the first isolation region 14a and the second active region 12b is exposed from the bottom of the storage node contact hole SC. According to some embodiments of the present invention, the top surface of the second active region 12b exposed from the storage node contact hole SC may have an area A1. For example... Figure 7 As shown in the diagram on the right, the two ends 12a2 of the active region 12 are exposed from different storage node contact holes SC.

[0074] Please refer to Figure 8Next, another etching process E2 (e.g., a wet etching process) can be performed to etch the exposed portion of the active region 12 through the memory node contact holes SC, forming a deep groove R1 below each memory node contact hole SC. Etching process E2 requires an etchant that is selective for the material of the substrate 10. For example, when the substrate 10 is a silicon substrate, the etchant for etching process E2 may include ammonia hydroxide (NH4OH), potassium hydroxide (KOH), hydrofluoric acid (HF), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), or combinations thereof, but is not limited to these. Figure 8 As shown in the left-hand diagram, viewed along the tangent AA', the deep groove R1 and the storage node contact hole SC may be misaligned in the vertical direction; they are not aligned. The deep groove R1, located between the first bit line BL1 and the second bit line BL2, extends to the positive side of the second gap wall SP2, exposing the top surface of the second active region 12b, the sidewalls of the first isolation region 14a, and the sidewalls of the second isolation region 14b. In some embodiments, the exposed top surface of the second active region 12b may have an area A2, and area A2 may be greater than or equal to area A1. In some embodiments, residue 12b' of the active region 12 may be present between the deep groove R1 and the bottom surface 16a of the insulating layer 16. Figure 8 As shown in the diagram on the right, when viewed along the tangent of BB', the deep groove R1 and the storage node contact hole SC are roughly aligned vertically. The sidewalls of the embedded word lines WL located on both sides of the middle part 12a1 (e.g., portions of the gate insulation layer 106 or the insulation capping layer 104) can be exposed from the deep groove R1.

[0075] It is worth noting that since the deep groove R1 is formed by selectively removing the exposed portion of the active region 12, the width of the deep groove R1 is primarily determined by the width of the end portion 12a2 of the active region 12. In some embodiments, the storage node contact hole SC and the deep groove R1 may have different widths, for example, please refer to... Figure 8 In the diagram on the right, the storage node contact hole SC can have a width W1, and the deep groove R1 can have a width W2, wherein the width W2 can be less than the width W1.

[0076] It is also worth noting that, Figure 8The fact that the top surface of the second active region 12b (or end 12a2) exposed from the deep groove R1 is shown as a plane is merely an example. In other embodiments, the type of etchant used in etching process E2 can be selected to make the top surface of the second active region 12b (or end 12a2) concave, convex, inclined, or angled, but is not limited thereto. In some embodiments, a suitable etchant can be selected and the depth of the deep groove R1 can be adjusted so that the area A2 is larger than the area A1.

[0077] Please refer to Figure 9 Next, an epitaxial growth process and / or deposition process can be performed to form a semiconductor layer S1 that fills the deep groove R1 and the lower part of the memory node contact hole SC. Then, a barrier layer L1 is formed to cover the top surface of the semiconductor layer S1 and the top surface of the spacer SP and bit line BL. Then, a metal layer M1 is formed to completely cover the bit line BL and fill the remaining space of the memory node contact hole SC. Next, a recess fabrication process is performed to remove the portion of the metal layer M1 and the barrier layer L1 outside the memory node contact hole SC, obtaining a memory node contact structure 42 that fills the memory node contact hole SC and the deep groove R1 and is in direct contact with and electrically connected to the end 12a2 of the active region 12. In detail, the memory node contact structure 42 may include three parts: a contact portion 42a located in the deep groove R1 and in direct contact with the end 12a2 of the active region 12; a plug portion 42b located in the memory node contact hole SC; and a contact pad portion 42c located outside the memory node contact hole SC. Contact portion 42a is mainly composed of semiconductor layer S1, plug portion 42b is jointly composed of semiconductor layer S1 and metal layer M1, and contact pad portion 42c is mainly composed of metal layer M1. The material of semiconductor layer S1 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of metal layer M1 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The shape, size, and position of contact portion 42a and plug portion 42b are determined by the deep groove R1 and the storage node contact hole SC, respectively. Contact portion 42a and plug portion 42b may have widths W2 and W1, respectively. In some embodiments, width W2 may be smaller than width W1. Figure 9 As shown in the left figure, the contact portion 42a and the plug portion 42b may be misaligned in the vertical direction, and they are not aligned. The contact portion 42a may be offset in the direction of one of the position lines BL, resulting in a misalignment with the plug portion 42b. As mentioned earlier, the shape of the contact surface between the contact portion 42a and the end portion 12a2 may be concave, convex, inclined, or angled, but is not limited to these.

[0078] At this point in the manufacturing process, the dynamic random access memory of this invention is complete. For example... Figure 9As shown in the left figure, the dynamic random access memory (DRAM) of the present invention may include a substrate 10, which includes a first active region 12a, a first isolation region 14a, a second active region 12b, and a second isolation region 14b arranged continuously along a first direction (i.e., the direction of the tangent to AA'). A first bit line BL1 is located on the first active region 12a, directly contacting and electrically connected to it. A second bit line BL2 is located on the second isolation region 14b, and is separated from it by an insulating layer 16, not in direct contact. A memory node contact structure 42 is located between the first bit line BL1 and the second bit line BL2, and is in direct contact with the top surface of the second active region 12b, the sidewalls of the first isolation region 14a and the second isolation region 14b.

[0079] In some embodiments, the top surface of the first active region 12a may be recessed below the top surface of the second active region 12b. The bottom surface of the storage node contact structure 42 is higher than the bottom surface of the first bit line BL1 and lower than the bottom surface of the second bit line BL2. A portion of the first isolation region 14a is removed when the groove BC is formed, so that its top surface is lower than the top surface of the second isolation region 14b.

[0080] In some embodiments, due to the misalignment between the storage node contact hole SC and the deep groove R1, the bottom of the storage node contact structure 42 may include a stepped profile.

[0081] In some embodiments, a first gap wall SP1 and a second gap wall SP2 may be provided on the sidewalls of the first bit line BL1 and the second bit line BL2, respectively, to achieve electrical isolation between the storage node contact structure 42 and the first bit line BL1 and the second bit line BL2. The stepped profile of the storage node contact structure 42 may include a bottom corner 43 located on the first gap wall SP1 and a lateral extension located directly below the second gap wall SP2 (or the insulating layer 16).

[0082] In some embodiments, the storage node contact structure 42, the insulating layer 16, and the second isolation region 14b may include a residue 12b' of the active region 12 left after the etching process E2.

[0083] In some embodiments, the storage node contact structure 42 may include a semiconductor layer S1 located in the lower half and in direct contact with the top surface of the second active region 12b, the sidewall of the first isolation region 14a, and the sidewall of the second isolation region 14b, and a metal layer M1 located in the upper half (on the semiconductor layer S1).

[0084] From another perspective, such as Figure 9As shown in the right-hand figure, the dynamic random access memory (DRAM) of the present invention may include a substrate 10, which includes an isolation structure 14 and an active region 12 located between the isolation structures 14. Two embedded word lines WL are located in the active region 12, dividing the active region 12 into a middle portion 12a1 and two ends 12a2. A bit line BL is located on the middle portion 12a1 of the active region 12, directly contacting and electrically connecting to the middle portion 12a1 of the active region 12. Storage node contact structures 42 are respectively located on the ends 12a2 of the active region 12, and include a contact portion 42a and a plug portion 42b located on the contact portion 42a, wherein the contact portion 42a directly contacts the top surface of the end 12a2, the sidewall of the embedded word line WL, and the sidewall of the isolation structure 14, and the width W2 of the plug portion 42b is greater than the width W1 of the contact portion 42a.

[0085] In some embodiments, a stepped profile may be included between the contact portion 42a and the plug portion 42b. One bottom corner 44 of the plug portion 42b may be located on the embedded letter line WL, and the other bottom corner 45 may be located on the isolation structure 14.

[0086] In some embodiments, the dynamic random access memory further includes a spacer wall SP located on the sidewall of the bit line BL, and electrically isolates the memory node contact structure 42 from the bit line BL.

[0087] In some embodiments, the top surface of the middle portion 12a1 may be recessed below the top surface of the end portion 12a2. The bottom surface of the storage node contact structure 42 may be higher than the bottom surface of the bit line BL and lower than the top surface of the embedded word line WL.

[0088] In some embodiments, the lower half of the contact portion 42a and the plug portion 42b of the storage node contact structure 42 is composed of a semiconductor layer S1, and the upper half of the plug portion 42b is composed of a metal layer M1.

[0089] Please refer to Figure 10 The diagram shown is a cross-sectional view of a dynamic random access memory according to another embodiment of the present invention, which is consistent with... Figure 9 The dynamic random access memories shown have roughly the same structure, including a substrate 10, an active region 12, an isolation structure 14, an embedded word line WL, a bit line BL, a memory node contact structure 42, etc. Figure 10 and Figure 9 The main difference between dynamic random access memory and dynamic random access memory is that... Figure 10 When fabricating the deep recess R1, the etching process E2 can be adjusted, for example, by adjusting the lateral etching rate or etching time of the etching process E2, to completely remove the residue 12b' between the deep recess R1 and the bottom surface 16a of the insulating layer 16. Therefore, Figure 10The memory node contact structure 42 of the dynamic random access memory can directly contact the bottom surface 16a of the insulating layer 16. In some embodiments, the semiconductor layer S1 can be divided into a lower part S1D that fills the deep groove R1 and an upper part S1T located between the lower part S1D and the metal layer M1, wherein the lower part S1D can be an epitaxial semiconductor layer formed by an epitaxial growth process, and the upper part S1T can be a deposited semiconductor layer formed by a deposition process. In some embodiments, the lower part S1D and the upper part S1T can include different materials. For example, the lower part S1D can include monocrystalline silicon, and the upper part S1T can include polycrystalline silicon. Preferably, the lower part S1D can be epitaxially grown until the top surface of the lower part S1D is higher than the bottom surface 16a of the insulating layer 16 before the upper part S1T is deposited.

[0090] Conventional methods for fabricating memory node contact structures typically involve filling the memory node contact structure with material immediately after forming the contact holes. However, if the etching depth of the contact holes is insufficient, their position is misaligned, or the bottom shape of the contact holes is abnormal, the exposed area of ​​the active region is often insufficient, leading to an abnormally high contact resistance in the memory node contact structure. The dynamic random access memory provided by this invention specifically employs a selective etching process (i.e., ...) after forming the memory node contact holes. Figure 8 The etching process (E2) further recesses the active region and expands the exposed area of ​​the active region (e.g., from area A1 to area A2). Therefore, the subsequent fabricated memory node contact structure can have a larger contact area and lower contact resistance with the active region, thereby improving the performance of the dynamic random access memory.

[0091] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic random access memory, characterized by, Comprising: a substrate comprising a first active region, a first isolation region, a second active region, and a second isolation region arranged successively along a first direction; a top surface of the first active region being lower than a top surface of the second active region; a first bit line on the first active region and in direct contact with the first active region; a second bit line on the second isolation region; an insulating layer between the second bit line and the second isolation region to isolate the second bit line from the second isolation region; and a storage node contact structure between the first bit line and the second bit line and in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region; the storage node contact structure and the insulating layer and the second isolation region comprising a residual portion of the second active region. A bottom of the storage node contact structure comprises a stepped profile.

2. The dynamic random access memory of claim 1, wherein, Further comprising:

3. The dynamic random access memory of claim 1, wherein, a first spacer on a sidewall of the first bit line and electrically isolating the storage node contact structure from the first bit line; and a second spacer on a sidewall of the second bit line and electrically isolating the storage node contact structure from the second bit line. A bottom corner of the storage node contact structure is on the first spacer. A portion of the storage node contact structure is directly below the second spacer.

4. The dynamic random access memory of claim 3, wherein, A top surface of the first isolation region is lower than a top surface of the second isolation region.

5. The dynamic random access memory as claimed in claim 3, wherein, The storage node contact structure comprises:

6. The dynamic random access memory of claim 1, wherein, a semiconductor layer in direct contact with the top surface of the second active region, the sidewall of the first isolation region, and the sidewall of the second isolation region; and 7. The dynamic random access memory of claim 1, wherein, a metal layer on the semiconductor layer. The semiconductor layer comprises: a lower portion comprising an epitaxial semiconductor layer, wherein a top surface of the lower portion is higher than a bottom surface of the insulating layer; and 8. The dynamic random access memory as claimed in claim 7, wherein, an upper portion between the lower portion and the metal layer and comprising a deposited semiconductor layer. Comprising: a substrate comprising an active region between two isolation structures; 9. A dynamic random access memory, characterized by two buried word lines in the active region dividing the active region into a middle portion and two end portions; a bit line on the middle portion; a storage node contact structure on the end portions, wherein the storage node contact structure comprises: a contact portion in direct contact with a top surface of the end portion, a sidewall of the buried word line, and a sidewall of the isolation structure; and a plug portion on the contact portion, wherein a width of the plug portion is greater than a width of the contact portion, and a bottommost surface of the contact portion has a width equal to a width of the end portion. A bottom corner of the plug portion is on the buried word line. Another bottom corner of the plug portion is on the isolation structure. A stepped profile is between the contact portion and the plug portion.

10. The dynamic random access memory as claimed in claim 9, wherein, Further comprising a spacer on a sidewall of the bit line and electrically isolating the storage node contact structure from the bit line.

11. The dynamic random access memory as claimed in claim 10, wherein, A top surface of the middle portion is lower than the top surface of the end portion.

12. The dynamic random access memory as claimed in claim 9, wherein, ​ 13. The dynamic random access memory as claimed in claim 9, wherein, ​ 14. The dynamic random access memory as in claim 9, wherein, ​ 15. The dynamic random access memory as in claim 9, wherein, The contact portion and the lower half of the plug portion are composed of a semiconductor layer, and the upper half of the plug portion is composed of a metal layer.

16. The dynamic random access memory as in claim 15, wherein, The semiconductor layer includes: a lower portion including an epitaxial semiconductor layer; and an upper portion between the lower portion and the metal layer including a deposited semiconductor layer.

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