Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a substrate having a dummy gate structure thereon; forming a sidewall structure on sidewall surfaces of the dummy gate structure, the sidewall structure including a first sidewall, a second sidewall, and a sacrificial sidewall between the first sidewall and the second sidewall, and the first sidewall being on the sidewall surfaces of the dummy gate structure; forming a first dielectric layer on the substrate, and the first dielectric layer being on sidewall surfaces of the sidewall structure; after forming the sidewall structure, removing the dummy gate structure to form a dummy gate opening in the first dielectric layer; forming a gate structure in the dummy gate opening; forming a plug opening in the first dielectric layer and a source / drain plug in the plug opening, and the plug opening exposing a sidewall surface of the second sidewall; after forming the source / drain plug, removing the sacrificial sidewall to form a cavity between the first sidewall and the second sidewall. The semiconductor structure formed by the method has better performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase their speed. Currently, due to the demands for high device density, high performance, and low cost, the semiconductor industry has progressed to the nanotechnology process node, and the fabrication of semiconductor devices is limited by various physical limits.

[0003] As CMOS device dimensions continue to shrink, manufacturing and design challenges have spurred the development of three-dimensional designs such as FinFETs. Compared to existing planar transistors, FinFETs are advanced semiconductor devices for process nodes of 20nm and below. They can effectively control the short-channel effect that is difficult to overcome due to the scaling down of devices, and can also effectively increase the density of transistor arrays formed on the substrate. At the same time, the gate in a FinFET is arranged around the fin (fin channel), so static electricity can be controlled from three sides, resulting in superior performance in static control.

[0004] However, the performance of fin field-effect transistors produced by existing technologies needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate having a gate structure thereon; a sidewall structure located on the sidewall surface of the gate structure, the sidewall structure comprising: a first sidewall, a second sidewall, and a cavity located between the first sidewall and the second sidewall, wherein the first sidewall is located on the sidewall surface of the gate structure, the top surface of the cavity is higher than the top surface of the gate structure, and the bottom surface of the cavity is flush with the bottom surface of the gate structure; and source / drain plugs located on the substrate on both sides of the gate structure, wherein the source / drain plugs are located on the sidewall surface of the second sidewall.

[0007] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a dummy gate structure; forming a sidewall structure on the sidewall surface of the dummy gate structure, the sidewall structure including a first sidewall, a second sidewall, and a sacrificial sidewall located between the first sidewall and the second sidewall, wherein the first sidewall is located on the sidewall surface of the dummy gate structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is located on the sidewall surface of the sidewall structure; after forming the sidewall structure, removing the dummy gate structure and forming a dummy gate opening in the first dielectric layer; forming a gate structure in the dummy gate opening; forming a plug opening in the first dielectric layer and a source / drain plug located in the plug opening, wherein the plug opening exposes the sidewall surface of the second sidewall; after forming the source / drain plug, removing the sacrificial sidewall and forming a cavity between the first sidewall and the second sidewall.

[0008] Optionally, the method for forming the sidewall structure includes: forming a first sidewall material layer on the top surface and sidewall surface of the dummy gate structure and on the substrate surface; forming a sacrificial material layer on the sidewall surface of the first sidewall material layer; forming a second sidewall material layer on the surface of the sacrificial material layer and the exposed surface of the first sidewall material layer; and etching back the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer until the top surface of the dummy gate structure is exposed, so that the first sidewall material layer forms the first sidewall, the sacrificial material layer forms the sacrificial sidewall, and the second sidewall material layer forms the second sidewall.

[0009] Optionally, the method for forming the sacrificial material layer includes: forming an initial sacrificial material film on the surface of the first sidewall material layer; and etching back the initial sacrificial material film until the top surface of the first sidewall material layer is exposed to form the sacrificial material layer.

[0010] Optionally, it further includes: after forming the second sidewall material layer and before etching back the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer, forming a sacrificial structure on the substrate, the sacrificial structure covering the surface of the second sidewall material layer on the substrate and exposing the top surface of the second sidewall material layer on top of the dummy gate structure; the process of etching back the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer removes the second sidewall material layer and the first sidewall material layer on top of the dummy gate structure, while retaining the first sidewall material layer and the second sidewall material layer on the substrate.

[0011] Optionally, the first sidewall and the sacrificial sidewall are made of different materials; the second sidewall and the sacrificial sidewall are made of different materials.

[0012] Optionally, the material of the first sidewall includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide; the material of the second sidewall includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide; and the material of the sacrificial sidewall includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.

[0013] Optionally, it further includes: forming source / drain doped regions in the substrate on both sides of the dummy gate structure after forming the first sidewall material layer and before forming the sacrificial material layer.

[0014] Optionally, the method for forming the source / drain doped region includes: removing the substrate on both sides of the dummy gate structure, forming a plug opening in the substrate, and forming the source / drain doped region in the plug opening.

[0015] Optionally, the method for forming the source / drain doped region within the plug opening includes: forming an epitaxial layer within the plug opening using an epitaxial growth process; and incorporating the source / drain ions into the epitaxial layer using an in-situ doping process during the formation of the epitaxial layer to form the source / drain doped region.

[0016] Optionally, the top surface of the source / drain plug is higher than the top surface of the gate structure.

[0017] Optionally, it further includes: after forming the gate structure and before removing the sacrificial sidewall, forming a second dielectric layer on the surface of the first dielectric layer and the surface of the gate structure; and forming the plug opening in the first dielectric layer and the second dielectric layer.

[0018] Optionally, the method for forming the plug opening includes: forming a patterned layer on the surface of the second dielectric layer, the patterned layer exposing the surface of the second dielectric layer on the source / drain doped region; using the patterned layer as a mask, etching the first dielectric layer and the second dielectric layer until the surface of the source / drain doped region is exposed, thereby forming the plug opening within the first dielectric layer and the second dielectric layer.

[0019] Optionally, the method for forming the source / drain plug includes: forming a source / drain plug material layer inside the plug opening and on the surface of the second dielectric layer; planarizing the source / drain plug material layer until the surface of the second dielectric layer is exposed; and forming the source / drain plug inside the plug opening.

[0020] Optionally, it further includes: after forming the cavity, forming a third dielectric layer on the gate structure, and the third dielectric layer sealing the top of the cavity.

[0021] Optionally, the method for forming the third dielectric layer includes: forming a lower dielectric layer on the top of the gate structure, the top of the first sidewall, the top of the second sidewall, and the top surface and part of the sidewall surface of the source / drain plug, wherein the lower dielectric layer closes the top of the cavity; and forming an upper dielectric layer on the surface of the lower dielectric layer, wherein the top surface of the upper dielectric layer is higher than the top surface of the source / drain plug.

[0022] Optionally, the lower dielectric layer is formed by a chemical vapor deposition process, which includes: ion-enhanced chemical vapor deposition, high-concentration plasma deposition, or high aspect ratio deposition.

[0023] Optionally, the size of the cavity ranges from 5 nanometers to 10 nanometers along the direction perpendicular to the cavity sidewall.

[0024] Optionally, the method for forming a gate structure within the dummy gate opening includes: forming an interface layer on the bottom surface of the dummy gate opening; forming a high-K dielectric material film on the bottom and sidewall surfaces of the dummy gate opening and on the surface of the first dielectric layer, wherein the high-K dielectric material film is located on the interface layer surface; forming a power function material film on the surface of the high-K dielectric material film; forming a gate material film on the surface of the power function material film; planarizing the high-K dielectric material film, the power function material film, and the gate material film until the surface of the first dielectric layer is exposed, thereby forming a high-K dielectric layer from the high-K dielectric material film, forming a power function layer from the power function material film, and forming a gate layer from the gate material film, thereby forming a gate structure within the dummy gate opening.

[0025] Optionally, the substrate includes: a substrate and a fin and an isolation layer located on the surface of the substrate, wherein the isolation layer covers a portion of the fin sidewall surface; the dummy gate structure is located on the surface of the isolation layer and spans the fin.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] In the semiconductor structure provided by the present invention, the sidewall surface of the gate structure has a sidewall structure, which includes a first sidewall, a second sidewall, and a cavity located between the first and second sidewalls, thereby improving the performance of the gate structure. Simultaneously, since the cavity is an open structure filled with air, the dielectric constant of the cavity is relatively low, which helps to reduce the parasitic capacitance between the gate structure and other devices, thus improving the performance of the semiconductor structure.

[0028] In the semiconductor structure formation method provided by this invention, after replacing the dummy gate structure with a gate structure, the sacrificial sidewall on the surface of the first sidewall is removed, forming a cavity between the first and second sidewalls. Since the gate structure sidewall has a first sidewall, it protects the gate structure, reducing damage to the sidewalls during subsequent processes and improving the gate structure's performance. Simultaneously, the cavity between the first and second sidewalls, with the first sidewall located on the gate structure sidewall surface, creates an open cavity filled with air. This cavity has a low dielectric constant, which helps reduce parasitic capacitance between the gate structure and other devices, thereby improving the semiconductor structure's performance.

[0029] Furthermore, the plug opening exposes the surface of the second sidewall, and the source / drain plug located within the plug opening is situated on the surface of the second sidewall. The second sidewall can protect the source / drain plug, reducing damage to the sidewall of the source / drain plug in subsequent processes, thus improving the performance of the source / drain plug.

[0030] Furthermore, during the etching process of the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer, the sacrificial structure enables the first and second sidewall material layers on the substrate to be retained. This allows the first and second sidewall material layers on the substrate to serve as stop layers for the etching process when forming the plug opening. This results in a better morphology of the formed plug opening and less damage to the source / drain doped regions, thereby improving the performance of the formed semiconductor structure.

[0031] Furthermore, the size of the cavity ranges from 5 nanometers to 10 nanometers along the direction perpendicular to the cavity sidewall. If the size is less than 5 nanometers, the isolation effect of the small cavity is weak, resulting in an insignificant effect on reducing the parasitic capacitance between the gate structure and other devices. If the size is greater than 10 nanometers, it is not conducive to sealing the top of the cavity during the subsequent formation of the third dielectric layer, and it is also easy for some material to enter the cavity, causing the dielectric constant of the cavity to be affected by the material of the third dielectric layer, which is not conducive to reducing the parasitic capacitance between the gate structure and other devices. Attached Figure Description

[0032] Figures 1 to 4 This is a schematic diagram of the steps in a method for forming an existing semiconductor structure.

[0033] Figures 5 to 16 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0034] As described in the background section, semiconductor structures have poor performance.

[0035] The following detailed explanation, with reference to the accompanying diagrams, explains the reasons for the poor performance of semiconductor structures. Figure 1 This is a schematic diagram of a semiconductor structure.

[0036] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0037] First, the reasons for the poor performance of existing semiconductor structures will be explained in detail with reference to the accompanying diagrams. Figures 1 to 4 This is a schematic diagram of the steps involved in forming an existing semiconductor structure.

[0038] Please refer to Figure 1 A substrate 100 is provided, on which a fin 110 and a dummy gate structure 120 are provided. The dummy gate structure 120 spans the fin 110 and is located on a portion of the top surface and sidewall surface of the fin 110. A sidewall 130 is formed on the sidewall surface of the dummy gate structure 120. Source / drain doped regions 140 are formed in the fin 110 on both sides of the dummy gate structure 120 and the sidewall 130.

[0039] Please refer to Figure 2 A first dielectric layer 150 is formed on the substrate 100, and the first dielectric layer 150 covers the sidewall surface of the sidewall 130.

[0040] Please refer to Figure 3 Remove the dummy gate structure 120 and form a dummy gate opening (not shown in the figure) in the first dielectric layer 150; form a gate structure 160 in the dummy gate opening.

[0041] Please refer to Figure 4 After forming the gate structure 160, the sidewall 130 is removed, and a cavity 170 is formed in the first dielectric layer 150; a second dielectric layer 180 is formed on the surface of the first dielectric layer 150, and the second dielectric layer 180 is located on top of the cavity 170 and closes the top of the cavity 170.

[0042] In the above method, by removing the sidewall 130, a cavity 170 is formed in the first dielectric layer 150. Specifically, the cavity 170 is a porous structure filled with air. Compared with the sidewall 130 material, air has a smaller dielectric constant. The method of setting the cavity 170 on the sidewall of the gate structure 160 helps to reduce the capacitance between the gate structure 160 and other devices, thereby improving the performance of the formed semiconductor structure.

[0043] However, during the process of removing the sidewall 130 to form the cavity 170, the sidewall of the gate structure 160 is exposed and is easily damaged by the etching process, resulting in a decrease in the performance of the gate structure 170 and making the performance of the semiconductor structure still poor.

[0044] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure and a method for forming the same. The structure includes: forming a sidewall structure on the sidewall surface of a dummy gate structure, the sidewall structure comprising a first sidewall, a second sidewall, and a sacrificial sidewall located between the first and second sidewalls, wherein the first sidewall is located on the sidewall surface of the dummy gate structure; after replacing the dummy gate structure to form a gate structure, removing the sacrificial sidewall to form a cavity between the first and second sidewalls. The first sidewall protects the gate structure, reducing damage to the sidewalls of the gate structure during subsequent processes. Furthermore, the cavity between the first and second sidewalls has a lower dielectric constant, which helps reduce parasitic capacitance between the gate structure and other devices, thereby improving the performance of the semiconductor structure.

[0045] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figures 5 to 16 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0047] Please refer to Figure 5 A substrate is provided on which a pseudo-gate structure 210 is provided.

[0048] In this embodiment, the substrate includes a substrate 201 and a fin 202 and an isolation layer (not shown in the figure) located on the substrate 201, and the isolation layer covers a portion of the sidewall surface of the fin 202.

[0049] In this embodiment, the substrate 201 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0050] In this embodiment, the fin 202 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0051] In this embodiment, the dummy gate structure 210 is located on the surface of the isolation layer and spans the fin 202.

[0052] The isolation layer can serve to electrically isolate adjacent fins 202.

[0053] In this embodiment, the material of the isolation layer is silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride or silicon oxynitride.

[0054] In other embodiments, the substrate is a planar substrate.

[0055] In this embodiment, the top surface of the dummy gate structure 210 has a hard mask structure.

[0056] The hard mask structure serves two purposes: firstly, it protects the top surface of the dummy gate structure 210, reducing the impact on the morphology of the dummy gate structure 210; secondly, it serves as a stop layer for subsequent etching.

[0057] In this embodiment, the hard mask structure includes: a first hard mask layer (not shown in the figure) located on the top surface of the dummy gate structure 210; and a second hard mask layer (not shown in the figure) located on the surface of the first hard mask layer.

[0058] In other embodiments, the hard mask structure may also be a single-layer structure.

[0059] Next, a sidewall structure is formed on the sidewall surface of the dummy gate structure 210. The sidewall structure includes a first sidewall, a second sidewall, and a sacrificial sidewall located between the first and second sidewalls. The first sidewall is located on the sidewall surface of the dummy gate structure 210. For details on the formation of the sidewall structure, please refer to [link / reference needed]. Figures 6 to 9 .

[0060] Please refer to Figure 6 A first sidewall material layer 220 is formed on the top surface and sidewall surface of the pseudo-gate structure 210 and on the surface of the substrate 200.

[0061] The first sidewall material layer 220 provides a material layer for the subsequent formation of the first sidewall.

[0062] The material of the first sidewall material layer 220 includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide. In this embodiment, the material of the first sidewall material layer 220 is silicon nitride.

[0063] In this embodiment, the method for forming the semiconductor structure further includes: after forming the first sidewall material layer 220 and before subsequently forming the sacrificial material layer, forming source / drain doped regions 204 in the substrate on both sides of the dummy gate structure 210.

[0064] Specifically, the source / drain doped regions 204 are located within the fins 202 on both sides of the pseudo-gate structure 210.

[0065] It should be noted that during the formation of the source / drain doped region 204, the first sidewall material layer 220 located on the substrate surfaces on both sides of the dummy gate structure 210 and the top surface of the dummy gate structure 210 is removed; after the formation of the source / drain doped region 204, a supplementary sidewall material layer is formed on the surface of the source / drain doped region 204 and the top surface of the dummy gate structure 210, and the supplementary sidewall material layer and the first sidewall material layer located on the sidewall surface of the dummy gate structure 210 together serve as the first sidewall material layer 220 for subsequent processes.

[0066] The method for forming the source / drain doped region 204 includes: removing the substrate on both sides of the dummy gate structure 210, forming a plug opening (not shown in the figure) in the substrate; and forming the source / drain doped region 204 in the plug opening.

[0067] The method for forming the source / drain doped region 204 within the plug opening includes: forming an epitaxial layer (not shown in the figure) within the plug opening using an epitaxial growth process; and incorporating the source / drain ions into the epitaxial layer (not shown in the figure) using an in-situ doping process during the formation of the epitaxial layer to form the source / drain doped region 204.

[0068] Please refer to Figure 7 A sacrificial material layer 230 is formed on the sidewall surface of the first sidewall material layer 220.

[0069] The sacrificial material layer 230 provides a material layer for the subsequent formation of the sacrificial sidewall.

[0070] The materials of the sacrificial material layer 230 and the first sidewall material layer 220 are different. The materials of the sacrificial material layer 230 include silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.

[0071] In this embodiment, the material of the sacrificial material layer 230 is silicon oxide.

[0072] The method for forming the sacrificial material layer 230 includes: forming an initial sacrificial material film (not shown in the figure) on the surface of the first sidewall material layer 220; and etching back the initial sacrificial material film until the top surface of the first sidewall material layer 220 is exposed to form the sacrificial material layer 230.

[0073] Please refer to Figure 8 A second sidewall material layer 240 is formed on the surface of the sacrificial material layer 230 and the exposed surfaces of the first sidewall material layer 210.

[0074] The second sidewall material layer 240 provides a material layer for the subsequent formation of the second sidewall.

[0075] The second sidewall material layer 240 and the sacrificial material layer 230 are made of different materials; the material of the second sidewall material layer 240 includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.

[0076] In this embodiment, the material of the second sidewall material layer 240 is silicon nitride.

[0077] Please refer to Figure 9 The first sidewall material layer 220, the sacrificial material layer 230, and the second sidewall material layer 240 are etched back until the top surface of the dummy gate structure 210 is exposed, so that the first sidewall material layer 220 forms the first sidewall 221, the sacrificial material layer 230 forms the sacrificial sidewall 231, and the second sidewall material layer 240 forms the second sidewall 241.

[0078] The first sidewall 221, the second sidewall 241, and the third sidewall located between the first sidewall 221 and the second sidewall 241 constitute a sidewall structure (not shown in the figure), located on the sidewall surfaces of the pseudo gate structure 210.

[0079] The sacrificial sidewall 231 occupies space for the subsequent formation of a cavity.

[0080] Specifically, the top surface of the dummy gate structure 210 has a hard mask structure, and the first sidewall material layer 220, the sacrificial material layer 230 and the second sidewall material layer 240 are etched back until the etching stops on the surface of the hard mask structure.

[0081] Since the first sidewall material layer 220 forms the first sidewall 221, the sacrificial material layer 230 forms the sacrificial sidewall 231, and the second sidewall material layer 240 forms the second sidewall 241, the materials of the first sidewall 221 and the sacrificial sidewall 231 are different; the materials of the second sidewall 241 and the sacrificial sidewall 231 are also different. The material of the first sidewall 221 includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide; the material of the second sidewall 241 includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide; and the material of the sacrificial sidewall 231 includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.

[0082] In this embodiment, the method for forming the semiconductor structure further includes: after forming the second sidewall material layer 240, and before etching back the first sidewall material layer 220, the sacrificial material layer 230 and the second sidewall material layer 240, forming a sacrificial structure (not shown in the figure) on the substrate, the sacrificial structure covering the surface of the second sidewall material layer 240 on the substrate and exposing the top surface of the second sidewall material layer 240 on the top of the dummy gate structure 210.

[0083] In this embodiment, due to the formation of the sacrificial structure, during the process of etching back the first sidewall material layer 220, the sacrificial material layer 230, and the second sidewall material layer 240, the second sidewall material layer 240 and the first sidewall material layer 220 on the top of the dummy gate structure 210 are removed, while the first sidewall material layer 220 and the second sidewall material layer 230 on the substrate are retained. This allows the first sidewall material layer 220 and the second sidewall material layer 240 retained on the substrate to serve as stop layers for the subsequent formation of source and drain plugs.

[0084] Please refer to Figure 10 A first dielectric layer 250 is formed on the substrate, and the first dielectric layer 250 is located on the sidewall surface of the sidewall structure.

[0085] The material of the first dielectric layer 250 is different from that of the first sidewall 221; the materials of the first dielectric layer 250 and the second sidewall 241 are different.

[0086] In this embodiment, the first dielectric layer 250 and the sacrificial sidewall 231 are made of the same material, silicon oxide.

[0087] The method for forming the first dielectric layer 250 includes: forming a dielectric material layer (not shown in the figure) covering the dummy gate structure 210 and the sidewall structure on a substrate, wherein the entire surface of the dielectric material layer is higher than the top surface of the dummy gate structure 210; and removing the dielectric material layer higher than the top surface of the dummy gate structure 210 to form the first dielectric layer 250.

[0088] In this embodiment, during the process of removing the dielectric material layer above the top surface of the dummy gate structure 210, the hard mask structure located on the top surface of the dummy gate structure 210 and the sidewall structure above the top of the dummy gate structure 210 are also removed, and the top surface of the remaining sidewall structure is flush with the top surface of the dummy gate structure 210.

[0089] Please refer to Figure 11 After forming the sidewall structure, the pseudo-gate structure 210 is removed, and a pseudo-gate opening 260 is formed in the first dielectric layer 250.

[0090] The process for removing the dummy gate structure 210 includes one or a combination of wet etching and dry etching.

[0091] In this embodiment, the process for removing the dummy gate structure 210 is a wet etching process, which can remove the dummy gate structure 210 quickly, thereby improving production efficiency.

[0092] Please refer to Figure 12 A gate structure 261 is formed within the pseudo-gate opening 260.

[0093] The method for forming a gate structure 261 within the dummy gate opening 260 includes: forming an interface layer (not shown in the figure) on the bottom surface of the dummy gate opening 261; forming a high-K dielectric material film (not shown in the figure) on the bottom and sidewall surfaces of the dummy gate opening 261 and on the surface of the first dielectric layer 250, wherein the high-K dielectric material film is located on the interface layer surface; forming a power function material film (not shown in the figure) on the surface of the high-K dielectric material film; forming a gate material film (not shown in the figure) on the surface of the power function material film; planarizing the high-K dielectric material film, the power function material film, and the gate material film until the surface of the first dielectric layer 250 is exposed, thereby forming a high-K dielectric layer (not shown in the figure) from the high-K dielectric material film, forming a power function layer (not shown in the figure) from the power function material film, and forming a gate layer (not shown in the figure) from the gate material film, thereby forming a gate structure 261 within the dummy gate opening 260.

[0094] The high-k dielectric layer is made of one or more of the following materials: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, or aluminum oxide. In this embodiment, the high-k dielectric layer is made of hafnium oxide.

[0095] The gate layer is made of a metal, including one or more of copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride. In this embodiment, the gate layer is made of tungsten.

[0096] The materials of the work function layer include: N-type work function layer and P-type work function layer.

[0097] The interface layer is made of silicon dioxide. The interface layer can effectively reduce interface defects between the fins and the gate dielectric layer, thereby improving the interface state and improving the performance of the formed semiconductor structure.

[0098] Next, a plug opening and a source / drain plug located within the plug opening are formed in the first dielectric layer 250, and the plug opening exposes the sidewall surface of the second sidewall 241.

[0099] In this embodiment, the top surface of the source / drain plug is higher than the top surface of the gate structure 261. For details on the formation of the plug opening and the source / drain plug, please refer to [reference needed]. Figures 13 to 14 .

[0100] Please refer to Figure 13 A second dielectric layer 270 is formed on the surface of the first dielectric layer 250 and the surface of the gate structure 261; a plug opening 280 is formed in the first dielectric layer 250 and the second dielectric layer 270.

[0101] In this embodiment, the plug opening 280 exposes not only the sidewall surface of the second sidewall 241, but also the surface of the source / drain doped region 204.

[0102] The material of the second dielectric layer 270 is different from that of the first sidewall 221; the materials of the second dielectric layer 270 and the second sidewall 241 are different.

[0103] In this embodiment, the material of the second dielectric layer 270 and the material of the sacrificial sidewall 231 are the same, both being silicon oxide.

[0104] The method for forming the plug opening 280 includes: forming a patterned layer (not shown in the figure) on the surface of the second dielectric layer 270, the patterned layer exposing the surface 270 of the second dielectric layer on the source / drain doped region 204; using the patterned layer as a mask, etching the first dielectric layer 250 and the second dielectric layer 270 until the surface of the source / drain doped region 204 is exposed, thereby forming the plug opening 280 in the first dielectric layer 250 and the second dielectric layer 270.

[0105] Specifically, during the etching of the first dielectric layer 250 and the second dielectric layer 270, a portion of the first sidewall material layer 220 remaining on the substrate surface is also etched. Figure 9 (as shown) and the second sidewall material layer 240 ( Figure 9 (as shown in the figure) until the surface of the source / drain doped region 204 is exposed.

[0106] During the etching process of the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer, the sacrificial structure allows the first sidewall material layer 220 and the second sidewall material layer 240 on the substrate to be retained. This allows the first sidewall material layer 220 and the second sidewall material layer 240 on the substrate to serve as stop layers for the etching process when the plug opening 280 is formed. This results in a better morphology of the formed plug opening 280 and less damage to the source / drain doped regions 204, thereby improving the performance of the formed semiconductor structure.

[0107] Please refer to Figure 14 A source / drain plug 281 is formed within the plug opening 280.

[0108] The source / drain plug 281 is located on the surface of the source / drain doped region 204.

[0109] The method for forming the source / drain plug 281 includes: forming a source / drain plug material layer (not shown in the figure) inside the plug opening 280 and on the surface of the second dielectric layer 270; planarizing the source / drain plug material layer until the surface of the second dielectric layer 270 is exposed; and forming the source / drain plug 281 inside the plug opening 280.

[0110] Since the plug opening 280 exposes the sidewall surface of the second sidewall 241, the source / drain plug 281 located in the plug opening 280 is located on the sidewall surface of the second sidewall 241. The second sidewall 241 can protect the source / drain plug 281, reducing damage to the sidewall of the source / drain plug 281 in subsequent processes, thus improving the performance of the source / drain plug 281.

[0111] Specifically, the method for forming the source / drain plug material layer includes: forming a plug blocking material film on the bottom and sidewall surfaces of the plug opening 280 and on the surface of the second dielectric layer 270; forming a plug conductive material film on the surface of the plug blocking material film, wherein the plug conductive material film fills the plug opening.

[0112] The plug blocking material film is used to increase the adhesion between the plug conductive material film and the second dielectric layer 270 and the first dielectric layer 220.

[0113] Please refer to Figure 15 After forming the source drain plug 281, the sacrificial sidewall 230 is removed, and a cavity 290 is formed between the first sidewall 220 and the second sidewall 240.

[0114] Specifically, before removing the sacrificial sidewall 230, the second medium layer 270 is removed to expose the sacrificial sidewall 230; after removing the sacrificial sidewall 230, a cavity 290 is formed between the first sidewall 220 and the second sidewall 240.

[0115] In this embodiment, the second dielectric layer 270 and the sacrificial sidewall 230 are made of the same material, and the second dielectric layer 270 and the sacrificial sidewall 230 can be removed by the same etching process, thereby saving process steps and process time.

[0116] By replacing the dummy gate structure 210 with the gate structure 261, and removing the sacrificial sidewall 231 on the sidewall surface of the first sidewall 221, the cavity 290 is formed between the first sidewall 221 and the second sidewall 231. Since the sidewall surface of the gate structure 261 has the first sidewall 221, the first sidewall 221 can protect the gate structure 261, reducing damage to the sidewalls of the gate structure 261 in subsequent processes, thus improving the performance of the gate structure 261. Simultaneously, the cavity 290 between the first sidewall 221 and the second sidewall 241, with the first sidewall 221 located on the sidewall surface of the gate structure 261, results in a cavity 290 that is open and filled with air. This cavity has a low dielectric constant, which helps reduce parasitic capacitance between the gate structure 261 and other devices, thereby improving the performance of the semiconductor structure.

[0117] Along the direction perpendicular to the sidewall of cavity 290, the size of cavity 290 ranges from 5 nanometers to 10 nanometers.

[0118] The depth of the cavity 290 ranges from 10 nanometers to 40 nanometers.

[0119] The depth refers to the dimension along the direction perpendicular to the substrate surface.

[0120] Along the direction perpendicular to the sidewall of cavity 290, the size of cavity 290 ranges from 5 nanometers to 10 nanometers. If the size is less than 5 nanometers, the isolation effect of the small cavity 290 is weak, resulting in an insignificant effect on reducing the parasitic capacitance between gate structure 261 and other devices. If the size is greater than 10 nanometers, it is not conducive to sealing the top of cavity 290 during the subsequent formation of the third dielectric layer, and it is also easy for some material to enter the cavity 290, causing the dielectric constant of cavity 290 to be affected by the material of the third dielectric layer, which is not conducive to reducing the parasitic capacitance between gate structure 261 and other devices.

[0121] Please refer to Figure 16 After the cavity 290 is formed, a third dielectric layer 291 is formed on the gate structure 261, and the third dielectric layer 291 closes the top of the cavity 290.

[0122] The method of forming the third dielectric layer 291 includes: forming a lower dielectric layer 2911 on the top of the gate structure 261, the top of the first sidewall 221, the top of the second sidewall 241, and the top surface and part of the sidewall surface of the source / drain plug 291, and the lower dielectric layer 2911 sealing the top of the cavity 290; and forming an upper dielectric layer 2912 on the surface of the lower dielectric layer 2911.

[0123] In this embodiment, the top surface of the upper dielectric layer 2912 is higher than the top surface of the source / drain plug 281.

[0124] The lower dielectric layer 2911 is formed by chemical vapor deposition, which includes ion-enhanced chemical vapor deposition (PECVD), high-concentration plasma deposition (HDP), or high aspect ratio deposition (HARP).

[0125] In this embodiment, the lower dielectric layer 2911 is formed using an ion-enhanced chemical vapor deposition process. The process has poor filling properties, which is beneficial for the film layer to be formed on the top of the cavity 290, thereby sealing the top of the cavity 290.

[0126] Accordingly, this invention also provides a semiconductor structure formed using the above method. Please refer to [link / reference needed]. Figure 15The device includes: a substrate having a gate structure 261 thereon; a sidewall structure located on the sidewall surface of the gate structure 261, the sidewall structure including: a first sidewall 221, a second sidewall 241 and a cavity 290 located between the first sidewall 221 and the second sidewall 241, wherein the first sidewall 221 is located on the sidewall surface of the gate structure 261, the top surface of the cavity 290 is higher than the top surface of the gate structure 261, and the bottom surface of the cavity 290 is flush with the bottom surface of the gate structure 261; and source / drain plugs 281 located on the substrates on both sides of the gate structure 261, wherein the source / drain plugs 281 are located on the sidewall surface of the second sidewall 241.

[0127] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a pseudo-gate structure thereon; the substrate includes: a substrate and fins located on the substrate; A sidewall structure is formed on the sidewall surface of the dummy gate structure. The sidewall structure includes a first sidewall, a second sidewall, and a sacrificial sidewall located between the first sidewall and the second sidewall, and the first sidewall is located on the sidewall surface of the dummy gate structure. A first dielectric layer is formed on the substrate, and the first dielectric layer is located on the sidewall surface of the sidewall structure; After forming the sidewall structure, the dummy gate structure is removed, and a dummy gate opening is formed in the first dielectric layer; A gate structure is formed within the pseudo-gate opening; A plug opening and a source / drain plug located within the plug opening are formed in the first dielectric layer, and the plug opening exposes the surface of the second sidewall, with the source / drain plug in contact with the surface of the second sidewall. After forming the source-drain plug, the sacrificial sidewall is removed, forming a cavity between the first sidewall and the second sidewall; The method for forming the sidewall structure includes: forming a first sidewall material layer on the top surface and sidewall surface of the dummy gate structure, and on the substrate surface; forming a sacrificial material layer on the sidewall surface of the first sidewall material layer, wherein the bottom surface of the sacrificial material layer contacts the top surface of the first sidewall material layer; forming a second sidewall material layer on the surface of the sacrificial material layer and the exposed surface of the first sidewall material layer; and etching back the first sidewall material layer, the sacrificial layer, and the second sidewall material layer until the top surface of the dummy gate structure is exposed, thereby forming the first sidewall material layer as the first sidewall, forming the sacrificial layer as the sacrificial sidewall, and forming the second sidewall material layer as the second sidewall. After forming the first sidewall material layer and before forming the sacrificial material layer, source / drain doped regions are formed in the substrate on both sides of the dummy gate structure; the method for forming the source / drain doped regions includes: removing the first sidewall material layer from the substrate surfaces on both sides of the dummy gate structure and the top surface of the dummy gate structure, forming source / drain doped openings in the substrate; forming source / drain doped regions in the source / drain doped openings; after forming the source / drain doped regions, forming supplementary sidewall material layers on the surface of the source / drain doped regions and the surface of the dummy gate structure, wherein the supplementary sidewall material layer and the first sidewall material layer located on the sidewall surface of the gate structure together serve as the first sidewall material layer for subsequent processes; The first sidewall covers the sidewall surface of the gate structure and a portion of the surface covering the source / drain doped region. The sidewall surface of the cavity is in contact with the surface of the first sidewall covering the sidewall surface of the gate structure, and the bottom surface of the cavity is in contact with the top surface of the first sidewall covering the source / drain doped region. The second sidewall is in contact with the sidewall surface of the cavity, and the bottom surface of the second sidewall is in contact with the top surface of the first sidewall covering the source / drain doped region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the sacrificial material layer includes: forming an initial sacrificial material film on the surface of the first sidewall material layer; and etching back the initial sacrificial material film until the top surface of the first sidewall material layer is exposed to form the sacrificial material layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After the second sidewall material layer is formed, and before the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer are etched back, a sacrificial structure is formed on the substrate. The sacrificial structure covers the surface of the second sidewall material layer on the substrate and exposes the top surface of the second sidewall material layer on top of the dummy gate structure. The process of etching back the first sidewall material layer, the sacrificial material layer, and the second sidewall material layer removes the second sidewall material layer and the first sidewall material layer on the top of the dummy gate structure, while retaining the first sidewall material layer and the second sidewall material layer on the substrate.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first sidewall and the sacrificial sidewall are made of different materials; the second sidewall and the sacrificial sidewall are made of different materials.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The material of the first sidewall includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide; the material of the second sidewall includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide; and the material of the sacrificial sidewall includes silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming a source / drain doped region within the source / drain doped opening includes: forming an epitaxial layer within the source / drain doped opening using an epitaxial growth process; and incorporating the source / drain ions into the epitaxial layer during the formation of the epitaxial layer using an in-situ doping process to form the source / drain doped region.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the source / drain plug is higher than the top surface of the gate structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: After the gate structure is formed but before the sacrificial sidewall is removed, a second dielectric layer is formed on the surface of the first dielectric layer and the surface of the gate structure. The plug opening is formed within the first and second dielectric layers.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the plug opening includes: forming a patterned layer on the surface of the second dielectric layer, the patterned layer exposing the surface of the second dielectric layer on the source / drain doped region; using the patterned layer as a mask, etching the first dielectric layer and the second dielectric layer until the surface of the source / drain doped region is exposed, thereby forming the plug opening in the first dielectric layer and the second dielectric layer.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the source / drain plug includes: forming a source / drain plug material layer inside the plug opening and on the surface of the second dielectric layer; planarizing the source / drain plug material layer until the surface of the second dielectric layer is exposed; and forming the source / drain plug inside the plug opening.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After the cavity is formed, a third dielectric layer is formed on the gate structure, and the third dielectric layer seals the top of the cavity.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the third dielectric layer includes: forming a lower dielectric layer on the top of the gate structure, the top of the first sidewall, the top of the second sidewall, and the top surface and part of the sidewall surface of the source / drain plug, wherein the lower dielectric layer seals the top of the cavity; and forming an upper dielectric layer on the surface of the lower dielectric layer, wherein the top surface of the upper dielectric layer is higher than the top surface of the source / drain plug.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The formation process of the lower dielectric layer is a chemical vapor deposition process, which includes: ion-enhanced chemical vapor deposition, high-concentration plasma deposition, or high aspect ratio deposition.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, Along the direction perpendicular to the cavity sidewall, the size of the cavity ranges from 5 nanometers to 10 nanometers.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a gate structure within the dummy gate opening includes: forming an interface layer on the bottom surface of the dummy gate opening; forming a high-K dielectric material film on the bottom and sidewall surfaces of the dummy gate opening and on the surface of a first dielectric layer, wherein the high-K dielectric material film is located on the interface layer surface; forming a power function material film on the surface of the high-K dielectric material film; forming a gate material film on the surface of the power function material film; planarizing the high-K dielectric material film, the power function material film, and the gate material film until the surface of the first dielectric layer is exposed, thereby forming a high-K dielectric layer from the high-K dielectric material film, forming a power function layer from the power function material film, and forming a gate layer from the gate material film, thereby forming a gate structure within the dummy gate opening.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes: a substrate and a fin and an isolation layer located on the surface of the substrate, wherein the isolation layer covers a portion of the sidewall surface of the fin; the dummy gate structure is located on the surface of the isolation layer and spans the fin.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the semiconductor structure forming method according to any one of claims 1 to 16.

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