Silicon carbide semiconductor devices and their fabrication methods

Abstract

This application discloses a silicon carbide semiconductor device and its fabrication method. The silicon carbide semiconductor device includes: a silicon carbide epitaxial layer having opposing first and second surfaces; the first surface includes a gate region and source regions located on both sides of the gate region; a first trench is formed within the surface of the gate region; a first voltage-resistant masking structure is formed within the silicon carbide epitaxial layer based on the first trench; a gate structure located within the first trench has a metal gate on its surface; a second voltage-resistant masking structure is formed within the surface of the source region; a metal source is formed on the surface of the source region; and a well region is formed within the first surface, located between the first trench and the second voltage-resistant masking structure. The silicon carbide semiconductor device has a first voltage-resistant masking structure formed within the silicon carbide epitaxial layer based on the first trench, and a second voltage-resistant masking structure formed within the surface of the source region. This improves the voltage withstand capability of the bottom corner region of the first trench and solves the problem of breakdown easily occurring in areas of concentrated electric field.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a silicon carbide (SiC) semiconductor device and a method for fabricating the same. Background Technology

[0002] With the continuous development of science and technology, more and more electronic devices are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] Integrated circuits are the main structure that enables various functions of electronic devices, and semiconductor devices are important electronic components of integrated circuits. Due to their excellent characteristics in high-power applications, silicon carbide semiconductor devices have become a major development direction in the semiconductor field.

[0004] However, in high-power applications, silicon carbide semiconductor devices are prone to breakdown in areas of concentrated electric field due to the presence of a high electric field. Summary of the Invention

[0005] In view of this, this application provides a silicon carbide semiconductor device and a method for fabricating the same, as follows:

[0006] A silicon carbide semiconductor device, the silicon carbide semiconductor device comprising:

[0007] A silicon carbide epitaxial layer having opposing first and second surfaces, the first surface including a gate region and source regions located on both sides of the gate region;

[0008] The gate region has a first trench in its surface;

[0009] A first voltage-resistant masking structure is formed within the silicon carbide epitaxial layer based on the first trench;

[0010] The gate structure located within the first trench;

[0011] The surface of the gate structure has a metal gate;

[0012] The source region has a second voltage-resistant masking structure within its surface.

[0013] The surface of the source region has a metal source electrode;

[0014] The first surface has a well region located between the first trench and the second pressure-resistant shielding structure.

[0015] Preferably, in a silicon carbide semiconductor device, in the depth direction of the first trench, the first voltage-resistant masking structure is located on the side of the well region facing the second surface and is not in contact with the well region.

[0016] Preferably, in a silicon carbide semiconductor device, the first trench is a first double-step trench;

[0017] The gate structure includes polysilicon filling the first trench, and a first insulating dielectric layer is provided between the first trench and the filled polysilicon.

[0018] The first withstand voltage shielding structure includes the sidewall of the first primary trench facing the second surface of the first double-step trench and the doped region within the bottom surface.

[0019] Preferably, in a silicon carbide semiconductor device, the depth of the well region relative to the first surface is less than the depth of the step between the two trenches in the first double-step trench, and the first voltage-resistant masking structure is located on the side of the step between the two trenches in the first double-step trench facing the second surface.

[0020] Preferably, in the silicon carbide semiconductor device, the first trench is a first double-step trench; the first double-step trench is filled with polysilicon, and a first insulating dielectric layer is present between the first double-step trench and the filled polysilicon.

[0021] The thickness of the insulating dielectric layer at the bottom of the first double-step trench is greater than the thickness of the insulating dielectric layer on the sidewall of each level of the first double-step trench, and greater than the thickness of the insulating dielectric layer on the step between two adjacent trenches.

[0022] Preferably, in the silicon carbide semiconductor device, the surface of the source region has a multi-level stepped trench; the multi-level stepped trench is filled with polysilicon, and a second insulating dielectric layer is provided between the multi-level stepped trench and the filled polysilicon.

[0023] The second withstand voltage masking structure includes a doped region formed within the silicon carbide epitaxial layer based on the multi-level stepped trenches.

[0024] Preferably, in a silicon carbide semiconductor device, the first trench is a first double-step trench; the multi-step trench is a second double-step trench, and the first double-step trench and the second double-step trench have the same depth.

[0025] Preferably, in a silicon carbide semiconductor device, the first trench is a first double-step trench;

[0026] The multi-level stepped groove is a three-level stepped groove, and the depth of the three-level stepped groove is greater than the depth of the first two-level stepped groove.

[0027] Preferably, in a silicon carbide semiconductor device, the second breakdown voltage masking structure includes a doped region within a silicon carbide epitaxial layer located on the sidewalls, steps, bottom, and around the opening of the multi-step trench.

[0028] Preferably, in a silicon carbide semiconductor device, the thickness of the second insulating dielectric layer at the bottom of the multi-level stepped trench is greater than the thickness of the second insulating dielectric layer on the sidewall of each level of the multi-level stepped trench, and greater than the thickness of the second insulating dielectric layer on the step between two adjacent levels of trench.

[0029] Preferably, in a silicon carbide semiconductor device, the second breakdown voltage masking structure is an ion implantation region formed in the source region.

[0030] Preferably, in a silicon carbide semiconductor device, the implantation depth of the ion implantation region is not less than the depth of the first trench.

[0031] This application also provides a method for fabricating the silicon carbide semiconductor device according to any one of the above claims, the method comprising:

[0032] An epitaxial wafer is provided, the epitaxial wafer including a silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first surface and a second surface opposite to each other, the first surface including a gate region and source regions located on both sides of the gate region;

[0033] A first trench is formed in the gate region;

[0034] Based on the first trench, a first voltage-resistant masking structure is formed in the silicon carbide epitaxial layer;

[0035] A gate structure is formed within the first trench;

[0036] A metal gate is formed on the surface of the gate structure, and a metal source is formed on the surface of the source region;

[0037] The source region has a second withstand voltage shielding structure within its surface; the first surface has a well region located between the first trench and the second withstand voltage shielding structure.

[0038] Preferably, in the manufacturing method, the first groove is a first double-step groove;

[0039] Multi-level stepped trenches are formed within the surface of the source region;

[0040] The method for fabricating the first and second voltage-resistant shielding structures includes:

[0041] Based on the first double-step trench and the dielectric layer of the first double-step trench near the first surface first-level trench sidewall, ion implantation is performed on the sidewall and bottom of the first double-step trench near the second surface first-level trench to form the first voltage-resistant masking structure in the silicon carbide epitaxial layer of the first double-step trench near the second surface first-level trench sidewall and bottom.

[0042] Based on the multi-level stepped trench, ion implantation is performed at the bottom of the multi-level stepped trench, the steps of each level of the trench, and the sidewalls to form the second voltage-resistant masking structure within the silicon carbide epitaxial layer at the bottom of the multi-level stepped trench, the steps of each level of the trench, and the sidewalls.

[0043] Preferably, in the fabrication method, the first trench is a first double-stepped trench; a multi-stepped trench is formed within the surface of the source region; both the first double-stepped trench and the multi-stepped trench are filled with polysilicon; the gate structure includes the polysilicon filled within the first double-stepped trench.

[0044] An insulating dielectric layer is present between the first double-step trench and the filled polysilicon, and between the multi-step trench and the filled polysilicon; the gate structure includes the polysilicon filled in the first double-step trench.

[0045] The metal gate is located on the surface of the polysilicon filled by the first double-step trench; the metal source is located on the surface of the polysilicon filled by the multi-step trench.

[0046] Preferably, in the manufacturing method, the thickness of the insulating dielectric layer at the bottom of the first double-step trench is greater than the thickness of the insulating dielectric layer on the sidewall of each level of the first double-step trench, and greater than the thickness of the insulating dielectric layer on the step between two adjacent trenches.

[0047] The thickness of the insulating dielectric layer at the bottom of the multi-level stepped trench is greater than the thickness of the insulating dielectric layer on the sidewall of each level of the multi-level stepped trench, and greater than the thickness of the insulating dielectric layer on the step between two adjacent levels of trench.

[0048] Preferably, in the manufacturing method, the multi-level stepped groove is a second double-level stepped groove, and the second double-level stepped groove has the same depth as the first double-level stepped groove; or, the multi-level stepped groove is a three-level stepped groove, and the depth of the three-level stepped groove is greater than the depth of the first double-level stepped groove.

[0049] Preferably, in the manufacturing method, the method for forming the second pressure-resistant shielding structure includes:

[0050] An ion implantation region is formed in the source region by ion implantation, serving as the second breakdown voltage masking structure.

[0051] The implantation depth of the ion implantation region is not less than the depth of the first trench.

[0052] As described above, the silicon carbide semiconductor device and its fabrication method provided in this application include: a silicon carbide epitaxial layer having a first surface and a second surface opposite to each other; the first surface including a gate region and source regions located on both sides of the gate region; a first trench within the surface of the gate region; a first voltage-resistant masking structure formed within the silicon carbide epitaxial layer based on the first trench; a gate structure located within the first trench; a metal gate on the surface of the gate structure; a second voltage-resistant masking structure within the surface of the source region; a metal source on the surface of the source region; and a well region within the first surface, located between the first trench and the second voltage-resistant masking structure. The silicon carbide semiconductor device forms a first voltage-resistant masking structure within the silicon carbide epitaxial layer based on the first trench, and a second voltage-resistant masking structure within the surface of the source region, improving the voltage withstand performance of the bottom corner region of the first trench and solving the problem of breakdown easily occurring in areas of concentrated electric field. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0054] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0055] Figure 1 This is a schematic diagram of a DMOSFET structure;

[0056] Figure 2 This is a schematic diagram of a UMOSFET structure;

[0057] Figure 3This is a schematic diagram of the structure of a silicon carbide semiconductor device provided in an embodiment of this application;

[0058] Figure 4 This is a schematic diagram of another silicon carbide semiconductor device provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the structure of another silicon carbide semiconductor device provided in the embodiments of this application;

[0060] Figure 6 This is a schematic diagram of the structure of another silicon carbide semiconductor device provided in the embodiments of this application;

[0061] Figures 7-29 This is a schematic flowchart illustrating a method for fabricating a silicon carbide semiconductor device, as provided in an embodiment of this application. Detailed Implementation

[0062] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0063] Due to its excellent properties, SiC material is highly attractive for high-power applications, making it one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and UMOSFETs with vertical gate trench structures.

[0064] like Figure 1 As shown, Figure 1 This is a schematic diagram of a DMOSFET structure, including: an n+ (heavily n-type doped) substrate 2; an n- (lightly n-type doped) drift region 3 disposed on the surface of the substrate 2; a p-type well region 4 located within the drift region 3; and a source region 5 located within the p-type well region, the source region 5 including an n+ doped region 51 and a p+ (heavily p-type doped) doped region 52. A gate dielectric layer 7 is disposed on the surface of the drift region 3, and a gate 8 is disposed on the surface of the gate dielectric layer 7. A drain 1 is disposed on the side of the substrate 2 opposite to the drift region 3.

[0065] The DMOSFET structure employs planar diffusion technology, using a refractory material, such as a polysilicon gate, as a mask. The edges of the polysilicon gate define the p-base region and the n+ source region. The name DMOS originates from this double-diffusion process. The surface channel region is formed by utilizing the lateral diffusion difference between the p-type base region and the n+ source region.

[0066] like Figure 2 As shown, Figure 2This is a schematic diagram of a UMOSFET structure, and Figure 1 The difference in the structure shown is that the UMOSFET has a U-shaped trench, the surface of which is covered by a gate dielectric layer 7, and the gate 8 is filled within the U-shaped trench. The vertical gate trench structure of the UMOSFET derives its name from the U-shaped trench structure. This U-shaped trench structure is formed in the gate region using reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the active region channel width), which significantly reduces the on-state characteristic resistance of the device.

[0067] After years of research in the industry, some manufacturers have already launched commercial products of planar SiC MOSFETs. For the conventional lateral DMOSFET structure, modern technological advancements have reached a point where shrinking the MOSFET cell size no longer reduces the on-resistance. This is mainly due to the limitation of the JFET neck resistance; even with smaller photolithography dimensions, it is difficult to reduce the on-resistance per unit area to 2 mΩ·cm. 2 A trench structure can effectively solve this problem. A U-shaped trench structure, such as... Figure 2 As shown, it employs trench etching technology in the manufacturing process of memory storage capacitors, changing the conductive channel from horizontal to vertical. Compared with the ordinary structure, it eliminates the neck resistance of JFET, greatly increases the cell density, and improves the current handling capability of power semiconductors.

[0068] However, several problems still exist in the actual fabrication and application of SiC UMOSFETs:

[0069] 1) The high electric field in the SiC drift region leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, resulting in rapid breakdown of the gate dielectric layer under high drain voltage. It also has poor electrostatic effects in harsh environments and poor tolerance to high voltage spikes in the circuit.

[0070] 2) The limited ion implantation depth makes it difficult to implement many targeted trench gate protection structures and surge protection designs from a process perspective.

[0071] 3) Due to the material properties of SiC itself, the thickness of the silicon dioxide layer at the bottom of the single rectangular or U-shaped gate trench is often too thin during the high-temperature furnace tube oxidation process, which reduces the withstand voltage at the bottom of the trench and the reliability of the device.

[0072] To address the aforementioned issues, this application provides a silicon carbide semiconductor device with a first withstand voltage masking structure formed within the silicon carbide epitaxial layer based on a first trench, and a second withstand voltage masking structure formed within the surface of the source region. This improves the withstand voltage performance of the bottom corner region of the first trench, solves the problem of breakdown easily occurring in areas of concentrated electric field, and enhances the device's electrostatic discharge tolerance to harsh environments and its ability to withstand high-voltage spikes in circuits. Furthermore, the formation of the first withstand voltage masking structure based on the first trench increases the ion implantation depth during its formation, facilitating the implementation of various trench gate protection structures and surge protection designs. Moreover, a thick insulating dielectric layer can be formed at the bottom of the trench, solving the problem that conventional high-temperature furnace tube oxidation processes cannot form a thick silicon dioxide layer in the trench, further improving the withstand voltage at the bottom of the trench and the reliability of the device.

[0073] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] like Figure 3 As shown, Figure 3 This application provides a schematic diagram of the structure of a silicon carbide semiconductor device, which includes:

[0075] A silicon carbide epitaxial layer 11 has a first surface and a second surface opposite to each other, the first surface including a gate region and source regions located on both sides of the gate region;

[0076] The gate region has a first trench 12 in its surface;

[0077] A first voltage-resistant masking structure 13 is formed within the silicon carbide epitaxial layer 11 based on the first trench 12;

[0078] The gate structure g is located within the first trench 12;

[0079] The surface of the gate structure has a metal gate G;

[0080] The source region has a second voltage-resistant masking structure 14 within its surface.

[0081] The surface of the source region has a metal source electrode S;

[0082] The first surface has a well region W, which is located between the first trench 12 and the second pressure-resistant shielding structure 14.

[0083] The silicon carbide semiconductor device has a first withstand voltage masking structure 13 formed within the silicon carbide epitaxial layer 11 based on a first trench 12, and a second withstand voltage masking structure 14 formed within the surface of the source region. This improves the withstand voltage performance in the bottom corner region of the first trench 12, solves the problem of breakdown easily occurring in areas of concentrated electric field, and enhances the device's electrostatic discharge tolerance to harsh environments and its ability to withstand high voltage spikes in the circuit. Furthermore, the first withstand voltage masking structure 13 can be formed based on the first trench 12, increasing the ion implantation depth during its formation and facilitating the implementation of various trench gate protection structures and surge protection designs.

[0084] Furthermore, a thick insulating dielectric layer can be formed at the bottom of the trench, solving the problem that conventional high-temperature furnace tube oxidation processes cannot form a thick silicon dioxide layer in the trench, further improving the withstand voltage at the bottom of the trench and the reliability of the device.

[0085] Optionally, the silicon carbide epitaxial layer 11 is formed on the surface of the semiconductor substrate 10, with the second surface facing the semiconductor substrate 10. A metal drain D is disposed on the side of the semiconductor substrate 10 opposite to the silicon carbide epitaxial layer 11. The metal source S and the metal drain D can be Ti or Al, etc., and the metal drain D can be one or a composite metal layer of Ni, Ti, Al or Ag.

[0086] The silicon carbide epitaxial layer 11 and the semiconductor substrate 10 have the same doping type. The well region W, the first breakdown voltage masking structure 13, and the second breakdown voltage masking structure 14 have the same doping type, but opposite to the doping type of the epitaxial layer 11. P-type doping and N-type doping are opposite types of doping. The silicon carbide epitaxial layer 11 near the first surface of the well region W has an ion implantation region 17 with the opposite doping type to that of the well region W. When the well region W is P-type doped, this ion implantation region 17 can be an N+ ion implantation region.

[0087] In this embodiment, the semiconductor substrate 10 can be an N+ (heavily doped N-type) silicon carbide substrate; the epitaxial layer 11 is an N- (lightly doped N-type) silicon carbide epitaxial layer, serving as the drift region of the semiconductor device; and the well region W is a P-type well region. The first breakdown voltage masking structure 13 and the second breakdown voltage masking structure 14 include P+ (heavily doped P-type) ion implantation regions. It should be noted that, in the embodiments of this application, the doping type of each region of the device is not limited to that described in the embodiments, and its doping type can be set according to requirements to form a PMOS or NMOS structure.

[0088] In the depth direction of the first trench, the first pressure-resistant shielding structure 13 is located on the side of the well region W facing the second surface and is not in contact with the well region W, that is to say, in Figure 3In the vertical direction, the first pressure-resistant shielding structure 13 is located below the trap region W and is not in contact with the trap region W.

[0089] exist Figure 3 In the illustrated configuration, the first trench 12 is a first double-stepped trench; the gate structure g includes polysilicon filling the first trench 12, and a first insulating dielectric layer 151 is provided between the first trench 12 and the filled polysilicon; the first breakdown voltage masking structure 13 includes doped regions located within the sidewall surface and bottom surface of the first-stage trench facing the second surface of the first double-stepped trench. The first insulating dielectric layer 151 is a gate oxide layer, which can be silicon dioxide.

[0090] The first double-stage stepped trench has two stages of trenches and a stepped structure between them. One stage of the first double-stage stepped trench is close to the first surface, and the other stage is close to the second surface. The opening of the first stage trench close to the first surface is larger than the opening of the first stage trench close to the second surface. Based on the sacrificial layer of the sidewall of the first stage trench close to the first surface, ion implantation is performed on the first double-stage stepped trench to form a first breakdown voltage masking structure 13. This prevents ion implantation on the sidewall of the first stage trench close to the first surface due to ion scattering during ion implantation. The first breakdown voltage masking structure 13 is located below the well region W, preventing contact between the two and thus avoiding abnormal channel opening problems in the semiconductor device, ensuring normal device operation.

[0091] The first insulating dielectric layer 151 extends to the outside of the first trench 12 and covers the first surface. The first insulating dielectric layer 151 has an opening on the first surface for providing a metal ohmic contact layer 18, through which the source metal S is connected to the silicon carbide epitaxial layer 11.

[0092] The depth of the well region W relative to the first surface is less than the depth of the step between the two levels of the first double-step trench, and the first pressure-resistant shielding structure 13 is located on the side of the step between the two levels of the first double-step trench facing the second surface.

[0093] exist Figure 3 In the illustrated configuration, the surface of the source region has a multi-level stepped trench 16; the multi-level stepped trench 16 is filled with polysilicon, and a second insulating dielectric layer 152 is provided between the multi-level stepped trench 16 and the filled polysilicon; the second withstand voltage masking structure 14 includes a doped region formed in the silicon carbide epitaxial layer 11 based on the multi-level stepped trench.

[0094] The first insulating dielectric layer 151 on the surface of the first trench 12 and the second insulating dielectric layer 152 on the surface of the multi-step trench 16 are made of the same material and are formed simultaneously. The polycrystalline silicon filling the first trench 12 is formed simultaneously with the polycrystalline silicon filling the multi-step trench 16.

[0095] The second withstand voltage masking structure 14 includes a doped region located in the silicon carbide epitaxial layer 11 around the sidewalls, steps, bottom, and opening of the multi-level stepped trench 16. In other words, the second withstand voltage masking structure 14 is provided in the silicon carbide epitaxial layer around the sidewalls, steps, bottom, and opening of the multi-level stepped trench 16.

[0096] exist Figure 3 In the illustrated configuration, the first groove 12 is a first double-step groove; the multi-step groove 16 is a second double-step groove. The first double-step groove and the second double-step groove have the same depth and can be prepared in the same process.

[0097] In this embodiment, the multi-level stepped trench 16 is not limited to a two-level stepped trench, but can also be a stepped trench with more than two levels. The number of trench steps in the multi-level stepped trench 16 can be set based on the device thickness parameters and ion implantation depth requirements.

[0098] In this embodiment of the application, the silicon carbide semiconductor device can be a silicon carbide MOSFET device. Figure 3 In the illustrated configuration, a trench gate is formed in the gate region based on a first trench 12, and trench sources are formed in the source regions on both sides of the gate region based on multi-level stepped trenches 16. Both the first trench 12 and the multi-level stepped trenches 16 can be double-level stepped trenches, thus forming a silicon carbide MOSFET device with a double-level stepped trench structure.

[0099] like Figure 4 As shown, Figure 4 This is a schematic diagram of another silicon carbide semiconductor device provided in an embodiment of this application, based on... Figure 3 As shown, Figure 4 In the illustrated configuration, the first groove 12 is a first double-step groove; the multi-step groove 16 is a three-step groove, and the depth of the three-step groove is greater than the depth of the first double-step groove.

[0100] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of another silicon carbide semiconductor device provided in an embodiment of this application. Figure 5In the silicon carbide semiconductor device shown, the first trench 12 is a first double-stepped trench; the first double-stepped trench is filled with polysilicon, and the gate structure g includes polysilicon filled with the first double-stepped trench, with a first insulating dielectric layer 151 between the first double-stepped trench and the filled polysilicon. Figure 3 Based on the method shown, Figure 5 In the silicon carbide semiconductor device shown, the thickness of the first insulating dielectric layer 151 at the bottom of the first double-step trench is greater than the thickness of the first insulating dielectric layer 151 on the sidewall of each level of the first double-step trench, and greater than the thickness of the first insulating dielectric layer 151 on the step between two adjacent trenches.

[0101] exist Figure 5 In the illustrated configuration, the thickness of the second insulating dielectric layer 152 at the bottom 16 of the multi-level stepped trench is greater than the thickness of the second insulating dielectric layer 152 on the sidewalls of each level of the multi-level stepped trench 16, and greater than the thickness of the second insulating dielectric layer 152 on the step between two adjacent levels of trenches. The second insulating dielectric layer 152 and the first insulating dielectric layer 151 are the same insulating dielectric layer 15.

[0102] Obviously, it is also possible to... Figure 4 Based on the arrangement shown, the first insulating dielectric layer 151 and the second insulating dielectric layer 152 are both located at the bottom of the trench and have a thickness greater than that of other areas of the trench.

[0103] The silicon carbide semiconductor device described in this application embodiment can form a trench gate based on a first trench 12 in the gate region, and form trench sources based on multi-level stepped trenches 16 in the source regions on both sides of the gate region. A first breakdown voltage masking structure 13 is formed at the bottom of the first trench 12 by ion implantation, and a second breakdown voltage masking structure 14 is formed in the silicon carbide epitaxial layer 11 at the bottom, sidewalls, and steps between the two trenches of the multi-level stepped trenches 16 by ion implantation. Both the first breakdown voltage masking structure 13 and the second breakdown voltage masking structure 14 can be P+ (P-type heavily doped) regions.

[0104] Based on the first trench 12 and the multi-level stepped trench 16, a first withstand voltage masking structure 13 and a second withstand voltage masking structure 14 are formed in the silicon carbide epitaxial layer 11 by ion implantation. This solves the problems of difficulty in forming a deep P+ masking layer in silicon carbide material and damage caused by high-dose, high-energy P+ ion implantation, improving the reliability of the device and providing better shielding and protection for the gate trench. After ion activation to form the first withstand voltage masking structure 13 and the second withstand voltage masking structure 14, silicon dioxide layers are grown on the surfaces of the first trench 12 and the multi-level stepped trench 16 as the first insulating dielectric layer 151 and the second insulating dielectric layer 152. Then, polysilicon is filled in the first trench 12 and the multi-level stepped trench 16, and after forming metal electrodes, the silicon carbide MOSFET device with a double-level stepped trench structure is completed.

[0105] like Figure 6 As shown, Figure 6 This is a schematic diagram of another silicon carbide semiconductor device provided in an embodiment of this application. The second breakdown voltage masking structure 14 is an ion-implanted region formed in the source region. This method eliminates the need to form trenches in the source region; instead, it directly forms an ion-implanted region of a set depth through an ion implantation process, serving as the second breakdown voltage masking structure 14. Figure 6 In the illustrated configuration, to achieve better pressure-resistant masking, the implantation depth of the ion implantation region is not less than the depth of the first trench 12.

[0106] Based on the above embodiments, another embodiment of this application provides a method for fabricating a silicon carbide semiconductor device, used to fabricate the silicon carbide semiconductor device described in the above embodiments. The fabrication method can be as follows: Figures 7-29 As shown.

[0107] refer to Figures 7-29 As shown, Figures 7-29 This is a schematic flowchart illustrating a method for fabricating a silicon carbide semiconductor device according to an embodiment of this application. The method includes:

[0108] Step S11: As Figure 7 As shown, an epitaxial wafer is provided, the epitaxial wafer including a silicon carbide epitaxial layer 11, the silicon carbide epitaxial layer 11 having a first surface and a second surface opposite to each other, the first surface including a gate region and source regions located on both sides of the gate region.

[0109] The silicon carbide semiconductor device can be fabricated using an N+ silicon carbide semiconductor substrate 10 having an N-silicon carbide epitaxial layer 11. The second surface of the silicon carbide epitaxial layer 11 faces the semiconductor substrate 10.

[0110] Step S12: As Figures 8-16 As shown, a first trench 12 is formed in the gate region.

[0111] Before forming the first trench 12, a well region W, an ion implantation region 17, and an electric field buffer 19 are formed within the silicon carbide epitaxial layer 11 by ion implantation on the first surface. The ion implantation region 17 and the electric field buffer 19 are located within the surface of the source region and within the well region W.

[0112] This fabrication method is illustrated using a multi-level stepped trench 16 in the source region as an example. Subsequent processes form a second breakdown voltage masking structure 14 based on the multi-level stepped trench 16. The electric field buffer 19 solves the leakage and breakdown problems at the opening of the multi-level stepped trench 16 due to the thinness of the second breakdown voltage masking structure 14, thus enhancing the manufacturability and reliability of the device. The electric field buffer 19 and the second breakdown voltage masking structure 14 have the same doping type, such as both being N+ doped. The ion implantation region 17 has the opposite doping type to the second breakdown voltage masking structure 14; the ion implantation region 17 can be an N+ doped region.

[0113] Taking the first groove 12 as the first double-step groove and the multi-step groove 16 as the second double-step groove as an example, the second double-step groove can be formed at the same time as the first double-step groove. The specific process of forming the first double-step groove and the second double-step groove is as follows:

[0114] Step S121: As Figure 8 As shown, a well region W, an ion implantation region 17, and an electric field buffer zone 19 are formed on the first surface by ion implantation.

[0115] For silicon carbide materials, ion implantation is generally performed at 500-600℃ using a high-temperature ion implantation device to reduce damage to the silicon carbide lattice.

[0116] Step S122: As Figure 12 As shown, the first-stage trench etching is performed on the first surface.

[0117] Plasma dry etching processes, such as RIE or ICP etching, can be used to form the first-stage trenches. The etching principle for silicon carbide materials is as follows: Figures 9-11 As shown. First, as Figure 9 As shown, SiO2 is deposited on silicon carbide material as a mask layer using deposition processes such as CVD. Photoresist (PR) is then spin-coated onto the mask layer surface. The desired pattern of the photoresist is formed through exposure and development. Then, as shown... Figure 10 As shown, based on the patterned photoresist PR, the mask layer is etched to form a patterned mask layer, and finally as... Figure 11 As shown, based on a patterned mask layer, silicon carbide material is etched to form trenches on its surface. Subsequent processes will not describe in detail the common semiconductor processes such as photolithography and etching.

[0118] like Figure 12 As shown, when etching to form the first-stage trench, a layer of SiO2 can be deposited as a mask layer 21 by CVD. Gases containing F groups, such as CF4 and SF6, or gases containing Cl groups, such as chlorine, and a mixture of Ar and oxygen are used. The silicon carbide epitaxial layer 11 is etched in the gate region and the source regions on both sides using plasma etching equipment such as ICP or RIE to form the first-stage trenches in the gate and source regions respectively. The depth of the first-stage trench is 10nm-3μm. Further, the depth of the first-stage trench can be set to 800nm-1μm to improve device performance.

[0119] Step S123: As Figure 13 As shown, a SiO2 dielectric layer 22 is filled in the first-stage trench. The SiO2 dielectric layer 22 can be deposited using a CVD process, and the SiO2 dielectric layer 22 fills the first-stage trench and covers it with a mask layer 21.

[0120] Step S124: As Figure 14 As shown, the mask 23 for the second-level trench is aligned.

[0121] Photoresist is spin-coated onto the surface of the SiO2 dielectric layer 22, and then exposed and developed using a photomask 23 to pattern the photoresist. Figure 14 The photoresist is not shown in the image.

[0122] The photomask 23 has a first cutout region and a second cutout region. The first cutout region is used to form a second-level trench in the gate region for forming a trench gate, and the second cutout region is used to form a second-level trench in the source region for forming a trench source. In the photomask 23, the opening of the first cutout region is smaller than the opening of the first-level trench in the gate region, and the opening of the second cutout region is larger than the opening of the first-level trench in the source region.

[0123] Step S125: As Figure 15 As shown, based on the photoresist on the surface of the SiO2 dielectric layer 22, etching is performed to form second-level trenches on the basis of the first-level trenches in the gate region and the source region.

[0124] Using gases containing F groups such as CF4 and SF6, or gases containing Cl groups such as chlorine, or a mixture of Ar and oxygen, plasma etching equipment (ICP or RIE) is used to etch the silicon carbide epitaxial layer 11 in the gate region and the source regions on both sides to form second-level trenches in the gate region and the source region, respectively. The etching depth of the second-level trench is 100nm-3um; furthermore, the etching depth of the second-level trench can be set to 300-500nm to improve the device performance.

[0125] Because the opening of the first cutout region is smaller than the opening of the first-level trench in the gate region, a second-level trench with a greater depth can be etched at the bottom of the first-level trench in the gate region, thus forming a first double-stage stepped trench. Based on this method, while forming the first double-stage stepped trench in the gate region, a SiO2 dielectric layer 22 can be retained on the first-level trench sidewall near the first surface as a sacrificial layer. This prevents ion scattering on the first-level trench sidewall near the first surface during subsequent processes to form the first breakdown voltage masking structure 13, thus resolving the resulting channel opening abnormality problem, ensuring normal device operation, and improving device reliability.

[0126] Because the opening of the second hollow region is larger than the opening of the first-level trench in the source region, the size of the upper part of the first-level trench increases and the depth of the lower part increases during downward etching, thereby forming a second double-stage stepped trench. Based on this method, the SiO2 dielectric layer 22 on the sidewalls, steps, and bottom surface of the second double-stage stepped trench can be removed. After forming the second double-stage stepped trench in the source region, ion implantation is performed to form a second withstand voltage masking structure 14 in the sidewalls, steps, and bottom silicon carbide epitaxial layer 11 of the second double-stage stepped trench.

[0127] like Figure 16 As shown, Figure 16 The image shows a SEM image of a double-step trench formed in the source and gate regions using the fabrication method described in the embodiments of this application. Based on this SEM image, it can be seen that the fabrication method described in the embodiments of this application can form well-shaped double-step trenches in the gate and source regions, respectively.

[0128] Step S13: As Figures 17-20 As shown, a first voltage-resistant masking structure 13 is formed within the silicon carbide epitaxial layer based on the first trench.

[0129] The source region has a second withstand voltage shielding structure 14 on its surface; the first surface has a well region W, which is located between the first trench 12 and the second withstand voltage shielding structure 14.

[0130] The first trench 12 is a first double-step trench; a multi-step trench 16 is formed in the surface of the source region; the method for fabricating the first withstand voltage masking structure 13 and the second withstand voltage masking structure 14 includes: based on the first double-step trench and the dielectric layer 22 of the first double-step trench near the first surface, performing ion implantation on the sidewall and bottom of the first first-level trench of the first double-step trench near the second surface, forming the first withstand voltage masking structure 13 in the silicon carbide epitaxial layer of the first first-level trench sidewall and bottom of the first double-step trench near the second surface; based on the multi-step trench 16, performing ion implantation on the bottom of the multi-step trench 16, the steps of each level of trench and the sidewall, forming the second withstand voltage masking structure 14 in the silicon carbide epitaxial layer of the bottom of the multi-step trench, the steps of each level of trench and the sidewall.

[0131] The multi-level stepped groove 16 can be configured as a second double-level stepped groove, with the second double-level stepped groove having the same depth as the first double-level stepped groove; in other configurations, the multi-level stepped groove 16 can also be configured as a three-level stepped groove, with the depth of the three-level stepped groove being greater than the depth of the first double-level stepped groove.

[0132] In step S13, firstly as follows Figure 17 As shown, ion implantation is performed based on the patterned mask layer 21 and dielectric layer 22 to form a first pressure-resistant masking structure 13 and a second pressure-resistant masking structure 14. A high-temperature ion implantation device can be used to implant P+ ions into the trench sidewalls and bottom at 500-600℃ to form the first pressure-resistant masking structure 13 and the second pressure-resistant masking structure 14, and then... Figure 18 As shown, the mask layer 21 and dielectric layer 22 can be removed by using a buffered HF wet process to remove the silicon dioxide mask, thereby removing the mask layer 21 and dielectric layer 22.

[0133] For P+ ion implantation in silicon carbide devices, the typical implanted ion is Al ion; the ion implantation energy can range from several hundred keV to several MeV, and the dose is 1E12cm. -2 -1E16cm -2 The injection depth ranges from several hundred nm to several micrometers.

[0134] In particular, because the first double-step trench has a dielectric layer 22 with a thickness of tens to hundreds of nanometers or even micrometers on the sidewall of the first-level trench near the first surface, the first double-step trench, as the trap region W of the channel region, will not be affected by P+ ion implantation during ion implantation.

[0135] like Figure 19 As shown, Figure 19To obtain SEM images of the first withstand voltage shielding structure 13 and the second withstand voltage shielding structure 14 after fabrication using the method described in this application, based on Figure 19 It can be seen that after P+ ion implantation is completed, the well region W, which serves as the channel region, will not be affected by P+ ion implantation, thus improving the reliability and stability of the device.

[0136] like Figure 20 As shown, Figure 20 The images show SEM images of the source region before and after P+ ion implantation using the method described in this application. The left image is the SEM image of the region corresponding to the second double-step trench before P+ ion implantation. The right image is the SEM image of the region corresponding to the second double-step trench after P+ ion implantation. The area with lower grayscale in the right image is the SEM slice image formed after Al ion implantation.

[0137] As described above, the trench gate adopts a first double-step trench. Based on the method of this application, while forming the first double-step trench, a dielectric layer 22 is retained on the sidewall of the first-level trench near the first surface. Therefore, when performing ion implantation on the first double-step trench, P+ ion implantation can be performed on the bottom and sidewall of the first-level trench near the second surface, while avoiding P+ ion scattering doping on the sidewall of the first-level trench near the first surface, thus solving the problem of abnormal channel opening of the subsequent trench MOSFET.

[0138] Step S14: As Figures 21-23 As shown, a gate structure g is formed in the first trench;

[0139] The first trench 12 is a first double-stepped trench; multiple-stepped trenches 16 are formed within the surface of the source region; both the first double-stepped trench and the multiple-stepped trenches are filled with polysilicon; the gate structure g includes the polysilicon filled within the first double-stepped trench; an insulating dielectric layer 15 is provided between the first double-stepped trench and the filled polysilicon, and between the multiple-stepped trench 16 and the filled polysilicon; the gate structure g includes the polysilicon filled within the first double-stepped trench. The portion of the insulating dielectric layer 15 located within the first trench 12 is the first insulating dielectric layer 151, serving as the gate dielectric layer for the trench gate, and the portion located within the multiple-stepped trench 16 is the second insulating dielectric layer 152.

[0140] In step S14, firstly as follows Figure 21As shown, an insulating dielectric layer 15 is formed covering the first surface, the first trench 12, and the multi-step trench 16. The insulating dielectric layer within the first trench 12 serves as the gate dielectric layer of the trench gate. Optionally, the insulating dielectric layer 15 is a SiO2 layer. The insulating dielectric layer 15 can be grown in a high-temperature furnace tube. Oxygen can be introduced into the high-temperature furnace tube at 1100℃-1350℃ to oxidize and grow SiO2 on the surfaces of the first surface, the first trench 12, and the multi-step trench 16, forming the insulating dielectric layer 15. The thickness of the insulating dielectric layer 15 can be 40-70 nm.

[0141] Then, as Figure 22 As shown, after forming the insulating dielectric layer 15, polycrystalline silicon is filled into the first trench 12 and the multi-step trench 16. At 540℃-800℃, silane or DCS gas, Ar, and doped gases containing phosphorus or B, such as phosphine or borane, are introduced into the LPCVD furnace tube; after a chemical pyrolysis reaction, polycrystalline silicon is generated, with a thickness ranging from 400nm to several μm.

[0142] In such Figure 23 As shown, a mixture of HBr, chlorine and oxygen is used to etch polycrystalline silicon to remove the polycrystalline silicon from the first surface.

[0143] Step S15: As Figure 24 , Figure 25 As shown, a metal gate is formed on the surface of the gate structure g, and a metal source is formed on the surface of the source region, forming as shown in the figure. Figure 3 The silicon carbide semiconductor device shown.

[0144] The metal gate G is located on the surface of the polysilicon filled by the first double-step trench; the metal source S is located on the surface of the polysilicon filled by the multi-step trench 16.

[0145] In step S15, firstly as follows Figure 24 As shown, the insulating dielectric layer 15 on the first surface is etched to form an opening exposing the first surface. F-based gases such as CHF3 and CF4, or chlorine-based gases containing Cl, can be used to etch the first insulating dielectric layer 15 in a predetermined area on the source region surface to form the desired opening.

[0146] Then as Figure 25As shown, a metal ohmic contact layer 18 is formed in the opening region of the first insulating dielectric layer 15 to reduce the contact impedance between the metal source S and the first surface. A single-layer Ni PVD deposition or a multi-layer metal PVD deposition such as Ti / Ni / Al can be performed in the source region, and the metal outside the source region can be stripped or etched away. Then, rapid thermal annealing is performed at 900℃-1100℃ for 30 seconds to 5 minutes to form the metal ohmic contact layer 18.

[0147] Finally, a metal gate G is formed on the trench gate surface, a metal source S is formed on the trench source surface, and a metal drain D is formed on the side of the semiconductor substrate 10 facing away from the silicon carbide epitaxial layer 11, forming a structure as shown below. Figure 3 The silicon carbide semiconductor device shown is illustrated. The subsequent metal processing for the gate and source electrodes, the passivation layer and polyimide (PI) adhesive, and the metal processing for the back drain electrode are all conventional methods and will not be described in detail.

[0148] exist Figures 7-25 In the method shown, the first trench 12 is a first double-stepped trench, and the source region has a second double-stepped trench as an example for illustration. This method can be used to fabricate... Figure 3 The silicon carbide semiconductor device shown is an example of this method. In this method, when P+ ion implantation is performed on the bottom of the first double-step trench, the problem of P+ ion implantation on the upper sidewall of the trench due to scattering by the mask and trench sidewalls during P+ ion implantation in conventional single-level trench designs is avoided. This would cause the breakdown masking structure and the well region W, which serves as the channel region, to connect, resulting in abnormal channel opening.

[0149] based on Figures 7-25 The method shown can form a silicon carbide MOSFET device with a double-stage stepped trench structure, whereby double-stage stepped trenches can be formed in both the gate region and the source regions on both sides. Specifically, the gate region has a first double-stage stepped trench for forming a trench gate, and the source region has a second double-stage stepped trench for forming a trench source. A first breakdown voltage masking structure 13 is formed in the bottom and sidewalls of the first-stage trench near the second surface of the first double-stage stepped trench, and in the silicon carbide epitaxial layer 11 of each step. A second breakdown voltage masking structure 14 is formed in the bottom, sidewalls of each stage of the second double-stage stepped trench, and in the silicon carbide epitaxial layer 11 of each step. Based on the two double-stage stepped trenches, the problem of difficulty in forming a deep P+ masking layer in silicon carbide material is solved, and the high-dose, high-energy P+ ion implantation damage and the resulting reliability problems are solved, achieving better shielding and protection of the trench gate.

[0150] Simply using high-energy and high-dose ion implantation to depths of 1-2 μm or more can easily cause severe ion implantation damage to the silicon carbide material, leading to reliability issues in the long-term operation of subsequent devices. In this application, a trench source structure is formed based on a double-step trench in the source region. This allows for easy implantation of a P+ electric field masking structure with a depth of 1-2 μm or more in the source region, effectively shielding and protecting the trench gate sidewalls and bottom, thus enhancing the gate reliability of the silicon carbide MOSFET device.

[0151] Meanwhile, for trench gates with a first double-step trench, when P+ ion implantation is performed on the bottom of the first double-step trench, the problem of P+ ion implantation on the trench sidewalls due to scattering by the mask and trench sidewalls, which is present in the existing single-level trench trench preparation method in the industry, is avoided, which leads to abnormal opening of the trench MOSFET channel.

[0152] In this embodiment, the silicon carbide semiconductor device and fabrication process with a double-step trench structure can also be extended to a multi-step trench structure to achieve a deeper P+ ion implantation depth and better electric field masking protection for the gate region, as well as to form a semi-superjunction structure. Therefore, in order to form a newer P+ ion implantation in the source region and thus a deeper second breakdown voltage masking structure 14, a three-step trench can be formed in the source region to create a deeper P+ masking protection structure, thereby fabricating... Figure 4 The silicon carbide semiconductor device shown. (Example) Figure 26 As shown, Figure 26 SEM image of a three-step trench provided in an embodiment of this application.

[0153] In other methods, the formation of the second withstand voltage masking structure 14 includes: forming an ion implantation region in the source region using an ion implantation method, serving as the second withstand voltage masking structure 14; the implantation depth of the ion implantation region is not less than the depth of the first trench. This method can form a structure such as... Figure 6 The silicon carbide semiconductor device shown is an example of a method where a double-stepped trench structure is formed only in the gate region. The source region is directly implanted with high-energy, high-dose P+ ions to form a second breakdown voltage masking structure 14, which provides electric field shielding and protection for the trench gate. The fabrication method can be found in [reference needed]. Figure 3 The process flow of the device structure shown is not repeated in the embodiments of this application.

[0154] In other methods, the thickness of the insulating dielectric layer 15 at the bottom of the first double-step trench can be set to be greater than the thickness of the insulating dielectric layer 15 on the sidewalls of each level of the first double-step trench, and greater than the thickness of the insulating dielectric layer 15 on the step between adjacent two levels of trenches; the thickness of the insulating dielectric layer 15 at the bottom of the multi-step trench 16 can be greater than the thickness of the insulating dielectric layer 15 on the sidewalls of each level of the multi-step trench 16, and greater than the thickness of the insulating dielectric layer 15 on the step between adjacent two levels of trenches, thereby forming such a Figure 5 The silicon carbide semiconductor device shown.

[0155] It is possible Figures 7-25 Based on the method shown, further selectively optimized processes and structures are employed. After ion implantation and high-temperature activation to form the first and second breakdown voltage masking structures 13 and 14, CVD is first used to form SiO2 trenches to fill the gate and source regions. Then, a gas ICP or RIE plasma etching process with a high selectivity for SiO2:SiC is used to etch back the SiO2 in the trenches and on the first surface, removing the SiO2 in the first surface, the first double-step trench, and the first-level trench near the first surface, as well as the SiO2 at the bottom of the first and second double-step trenches. Next, SiO2 is grown on the sidewalls of the high-temperature furnace tube, followed by polysilicon filling. This allows for the formation of a thicker insulating dielectric layer at the bottom of the first and second double-step trenches, further increasing the breakdown voltage of the gate dielectric layer at the bottom of the trench gate and improving device reliability.

[0156] This process can be as follows: Figures 27-29 As shown, the specific method is as follows:

[0157] First, such as Figure 27 As shown, in Figure 18 Based on the structure shown, a SiO2 layer 31 is filled in both the gate region and the source region within the double-step trench. A relatively dense furnace tube thermal oxidation process, such as TEOS or HTO thermal oxidation silicon dioxide process, can be used to deposit a relatively dense SiO2 layer 31 on the surface of the double-step trench by reacting SiH4 or DCS gas with NO or O2.

[0158] Then, as Figure 28 As shown, the SiO2 layer 31 on the first surface and the SiO2 layer 31 in the double-step trench are etched away, while the SiO2 layer 31 of a predetermined thickness in the primary trench near the second surface is retained. Plasma etching can be used, selecting a gas with a high etching selectivity for SiO2:SiC, such as C4F8, to perform the etching back, retaining the SiO2 layer 31 of a predetermined thickness at the bottom of the primary trench near the second surface.

[0159] In such Figure 29 As shown, SiO2 layers are grown on the first surface and the surfaces of the two double-step trenches. Oxygen is introduced into the high-temperature furnace tube at 1100℃-1350℃ to grow SiO2 with a thickness of 40-70nm. This SiO2 layer, together with the SiO2 layer 31 previously retained at the bottom of the trench, forms an insulating dielectric layer 15.

[0160] use Figures 27-29 The method shown can form a thick insulating dielectric layer 15 at the bottom of the trench, which can further increase the withstand voltage at the bottom of the trench gate of the device and further improve the reliability of the device.

[0161] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0162] It should be noted that, in the description of this application, the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0163] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0164] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0165] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A silicon carbide semiconductor device, characterized in that, The silicon carbide semiconductor device includes: A silicon carbide epitaxial layer having opposing first and second surfaces, the first surface including a gate region and source regions located on both sides of the gate region; The surface of the gate region has a first trench, which is a first double-step trench. A first voltage-resistant masking structure is formed within the silicon carbide epitaxial layer based on the first trench; The gate structure located within the first trench; The surface of the gate structure has a metal gate; The source region has a second voltage-resistant masking structure within its surface. The surface of the source region has a metal source electrode; The first surface has a well region located between the first trench and the second pressure-resistant shielding structure; In this configuration, along the depth direction of the first trench, the first voltage-resistant masking structure is located on the side of the well region facing the second surface and is not in contact with the well region; the depth of the well region relative to the first surface is less than the depth of the step between the two trenches in the first double-step trench; the first voltage-resistant masking structure is located on the side of the step between the two trenches in the first double-step trench facing the second surface; the first voltage-resistant masking structure includes doped regions located within the surface of the first-level trench sidewall facing the second surface and within the bottom surface of the first double-step trench; based on the sacrificial layer of the first-level trench sidewall near the first surface, ion implantation is performed on the first double-step trench to form the first voltage-resistant masking structure.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The gate structure includes polysilicon filling the first trench, and a first insulating dielectric layer is provided between the first trench and the filled polysilicon.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The first trench is a first double-stepped trench; the first double-stepped trench is filled with polysilicon, and a first insulating dielectric layer is present between the first double-stepped trench and the filled polysilicon. The thickness of the insulating dielectric layer at the bottom of the first double-step trench is greater than the thickness of the insulating dielectric layer on the sidewall of each level of the first double-step trench, and greater than the thickness of the insulating dielectric layer on the step between two adjacent trenches.

4. The silicon carbide semiconductor device according to claim 1, characterized in that, The source region has multi-level stepped trenches on its surface; the multi-level stepped trenches are filled with polysilicon, and a second insulating dielectric layer is present between the multi-level stepped trenches and the filled polysilicon. The second withstand voltage masking structure includes a doped region formed within the silicon carbide epitaxial layer based on the multi-level stepped trenches.

5. The silicon carbide semiconductor device according to claim 4, characterized in that, The multi-level stepped groove is a second double-level stepped groove, and the first double-level stepped groove and the second double-level stepped groove have the same depth.

6. The silicon carbide semiconductor device according to claim 4, characterized in that, The multi-level stepped groove is a three-level stepped groove, and the depth of the three-level stepped groove is greater than the depth of the first two-level stepped groove.

7. The silicon carbide semiconductor device according to claim 4, characterized in that, The second withstand voltage masking structure includes a doped region within the silicon carbide epitaxial layer located on the sidewalls, steps, bottom, and around the opening of the multi-step trench.

8. The silicon carbide semiconductor device according to claim 4, characterized in that, The thickness of the second insulating dielectric layer at the bottom of the multi-level stepped trench is greater than the thickness of the second insulating dielectric layer on the sidewall of each level of the multi-level stepped trench, and greater than the thickness of the second insulating dielectric layer on the step between two adjacent levels of trench.

9. The silicon carbide semiconductor device according to claim 1, characterized in that, The second withstand voltage shielding structure is an ion implantation region formed in the source region.

10. The silicon carbide semiconductor device according to claim 9, characterized in that, The implantation depth of the ion implantation region is not less than the depth of the first trench.

11. A method for fabricating a silicon carbide semiconductor device as described in any one of claims 1-10, characterized in that, The manufacturing method includes: An epitaxial wafer is provided, the epitaxial wafer including a silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first surface and a second surface opposite to each other, the first surface including a gate region and source regions located on both sides of the gate region; A first trench is formed in the gate region, wherein the first trench is a first double-stepped trench; Based on the first trench, a first voltage-resistant masking structure is formed in the silicon carbide epitaxial layer; A gate structure is formed within the first trench; A metal gate is formed on the surface of the gate structure, and a metal source is formed on the surface of the source region; The source region has a second voltage-resistant masking structure within its surface; the first surface has a well region located between the first trench and the second voltage-resistant masking structure. In this configuration, along the depth direction of the first trench, the first voltage-resistant masking structure is located on the side of the well region facing the second surface and is not in contact with the well region; the depth of the well region relative to the first surface is less than the depth of the step between the two trenches in the first double-step trench; the first voltage-resistant masking structure is located on the side of the step between the two trenches in the first double-step trench facing the second surface; the first voltage-resistant masking structure includes doped regions located within the surface of the first-level trench sidewall facing the second surface and within the bottom surface of the first double-step trench; based on the sacrificial layer of the first-level trench sidewall near the first surface, ion implantation is performed on the first double-step trench to form the first voltage-resistant masking structure.

12. The manufacturing method according to claim 11, characterized in that, Multi-level stepped trenches are formed within the surface of the source region; The method for fabricating the first and second voltage-resistant shielding structures includes: Based on the first double-step trench and the dielectric layer of the first double-step trench near the first surface first-level trench sidewall, ion implantation is performed on the sidewall and bottom of the first double-step trench near the second surface first-level trench to form the first voltage-resistant masking structure in the silicon carbide epitaxial layer of the first double-step trench near the second surface first-level trench sidewall and bottom. Based on the multi-level stepped trench, ion implantation is performed at the bottom of the multi-level stepped trench, the steps of each level of the trench, and the sidewalls to form the second voltage-resistant masking structure within the silicon carbide epitaxial layer at the bottom of the multi-level stepped trench, the steps of each level of the trench, and the sidewalls.

13. The manufacturing method according to claim 11, characterized in that, Multiple stepped trenches are formed within the surface of the source region; both the first double-stepped trench and the multiple stepped trenches are filled with polysilicon; the gate structure includes polysilicon filled within the first double-stepped trench. An insulating dielectric layer is present between the first double-step trench and the filled polysilicon, and between the multi-step trench and the filled polysilicon; the gate structure includes the polysilicon filled in the first double-step trench. The metal gate is located on the surface of the polysilicon filled by the first double-step trench; the metal source is located on the surface of the polysilicon filled by the multi-step trench.

14. The manufacturing method according to claim 13, characterized in that, The thickness of the insulating dielectric layer at the bottom of the first double-step trench is greater than the thickness of the insulating dielectric layer on the sidewall of each level of the first double-step trench, and greater than the thickness of the insulating dielectric layer on the step between two adjacent trenches. The thickness of the insulating dielectric layer at the bottom of the multi-level stepped trench is greater than the thickness of the insulating dielectric layer on the sidewall of each level of the multi-level stepped trench, and greater than the thickness of the insulating dielectric layer on the step between two adjacent levels of trench.

15. The manufacturing method according to claim 14, characterized in that, The multi-level stepped groove is a second double-level stepped groove, and the second double-level stepped groove has the same depth as the first double-level stepped groove. Alternatively, the multi-level stepped groove may be a three-level stepped groove, and the depth of the three-level stepped groove may be greater than the depth of the first two-level stepped groove.

16. The manufacturing method according to claim 11, characterized in that, The method for forming the second pressure-resistant shield structure includes: An ion implantation region is formed in the source region by ion implantation, serving as the second breakdown voltage masking structure. The implantation depth of the ion implantation region is not less than the depth of the first trench.

Images