Signal Sampling Circuit and Method

Abstract

The present invention relates to a signal sampling circuit and method. The signal sampling circuit includes: a pre-sampling module, a sampling control module, and a data sampling module. The pre-sampling module is configured to: in response to a first sampling valid signal, sample the signal to be sampled and output a pre-sampled signal. The sampling control module is configured to: generate a synthesized clock according to a sampling clock, and in response to the synthesized clock, sample the first sampling valid signal to obtain a second sampling valid signal; and output a sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock. The data sampling module is respectively connected to the pre-sampling module and the sampling control module, and is configured to: in response to the sampling clock and the sampling control signal, sample the pre-sampled signal and output a sampled signal. The above signal sampling circuit can avoid sampling errors in the sampling circuit when the frequency of the sampling clock is exactly twice the frequency of the signal to be sampled.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a signal sampling circuit and method. Background Art

[0002] When using a sampling circuit to sample a signal to be sampled, it is usually required that the frequency of the sampling clock is twice or more than twice the frequency of the signal to be sampled. Moreover, if the frequency of the sampling clock is exactly twice the frequency of the signal to be sampled, it is required that the phase of the sampling clock is slightly offset from the phase of the signal to be sampled.

[0003] However, when the signal to be sampled is output by an analog circuit inside the chip or other circuits outside the chip, it is difficult to accurately determine the phase relationship between the sampling clock and the signal to be sampled. Based on this, when sampling the signal to be sampled according to the sampling clock, the signal to be sampled may be exactly in a changing state, resulting in a problem of sampling error.

[0004] Therefore, how to avoid sampling errors in the sampling circuit when the frequency of the sampling clock is exactly twice the frequency of the signal to be sampled is an urgent problem to be solved. Summary of the Invention

[0005] Based on this, it is necessary to provide a signal sampling circuit and method for solving the problem of how to avoid sampling errors in the sampling circuit when the frequency of the sampling clock is exactly twice the frequency of the signal to be sampled.

[0006] A signal sampling circuit includes: a pre-sampling module, a sampling control module, and a data sampling module. The pre-sampling module is configured to: in response to a first sampling valid signal, sample the signal to be sampled and output a pre-sampled signal. The sampling control module is configured to: generate a synthesized clock according to the sampling clock, and in response to the synthesized clock, sample the first sampling valid signal to obtain a second sampling valid signal; and, output a sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock. The data sampling module is respectively connected to the pre-sampling module and the sampling control module, and is configured to: in response to the sampling clock and the sampling control signal, sample the pre-sampled signal and output a sampled signal.

[0007] In the above signal sampling circuit, the pre-sampling module samples the signal to be sampled in response to the first valid signal and outputs a pre-sampled signal, so as to strictly control the change of the pre-sampled signal at the level change of the first sampling valid signal. Moreover, the sampling control module can generate a synthesized clock according to the sampling clock, sample the first sampling valid signal in response to the synthesized clock to obtain a second sampling valid signal, and output a sampling control signal according to the second sampling valid signal, the synthesized clock and the sampling clock. In this way, the second sampling valid signal obtained by the sampling control module takes into account the uncertainties caused by the clock domain inconsistency between the first sampling valid signal and the sampling clock, and can have a periodic and stable output. On this basis, the sampling control module outputs a sampling control signal according to the second sampling valid signal, the synthesized clock and the sampling clock, which can ensure a relatively fixed phase delay between the sampling control signal and the first sampling valid signal when it is difficult to accurately determine the phase relationship between the sampling clock and the signal to be sampled. Thus, the data sampling module samples the pre-sampled signal in response to the sampling clock and the sampling control signal provided by the sampling control module to output a sampling signal, and can ensure sampling in the non-changing state of the pre-sampled signal when the frequency of the sampling clock is twice the frequency of the signal to be sampled, so as to obtain an accurate sampling signal and effectively avoid sampling errors.

[0008] It can be seen that the signal sampling circuit in the present application can achieve accurate sampling without determining the phase relationship between the sampling clock and the signal to be sampled, and can effectively improve the signal sampling efficiency and yield.

[0009] In some embodiments, the sampling control module includes: a clock synthesis circuit, a synchronous sampling circuit, a level detection circuit, and a sampling controller. The clock synthesis circuit is configured to: generate a synthesized clock according to the sampling clock. The synchronous sampling circuit is connected to the clock synthesis circuit and is configured to: sample the first sampling valid signal in response to the synthesized clock to output a second sampling valid signal. The level detection circuit is respectively connected to the clock synthesis circuit and the synchronous sampling circuit and is configured to: sample the second sampling valid signal in response to the synthesized clock and detect the level state of the second sampling valid signal to obtain a first detection signal; and sample the first detection signal in response to the sampling clock and detect the level state of the first detection signal to obtain a second detection signal. The sampling controller is connected to the level detection circuit and is configured to: output a sampling control signal according to the second detection signal and the period of the sampling clock.

[0010] In some embodiments, the clock synthesis circuit includes: a clock delay circuit and a clock generation circuit. The clock delay circuit is configured to: delay the period of the sampling clock by a preset duration to output a delayed clock. The clock generation circuit is connected to the clock delay circuit and is configured to: perform a logical operation on the sampling clock and the delayed clock to output a synthesized clock.

[0011] In some embodiments, the clock generation circuit includes: a first clock generation circuit, a second clock generation circuit, and a synthesis circuit. The first clock generation circuit is configured to perform a logical AND operation on the sampling clock and the delayed clock to output a first clock. The second clock generation circuit is configured to first perform a logical OR operation on the sampling clock and the delayed clock, and then perform a logical NOT operation on the result of the logical OR operation to output a second clock. The synthesis circuit is connected to the first clock generation circuit and the second clock generation circuit respectively, and is configured to perform a logical OR operation on the first clock and the second clock to output a synthesized clock.

[0012] In some embodiments, the level detection circuit includes: a first detection circuit and a second detection circuit. The first detection circuit is connected to the clock synthesis circuit and the synchronous sampling circuit respectively, and is configured to sample the second sampling valid signal in response to the synthesized clock and detect the rising edge state of the second sampling valid signal to output a first detection signal. The second detection circuit is connected to the first detection circuit, and is configured to sample the first detection signal in response to the sampling clock and detect the rising edge state of the first detection signal to output a second detection signal. Wherein, the sampling controller is connected to the second detection circuit, and is configured to: after receiving the first rising edge of the second detection signal, count according to the period of the sampling clock and output a count value; the sampling control signal is the count value.

[0013] In the above signal sampling circuit, the first detection circuit can detect the rising edge state of the second sampling valid signal and output a first detection signal. The second detection circuit can sample and detect the rising edge state of the first detection signal based on the sampling clock and output a second detection signal. In this way, the rising edge of the second detection signal can be in the clock domain of the sampling clock. Moreover, after the sampling controller receives the first rising edge of the second detection signal, it will count according to the period of the sampling clock and output a count value, that is, the sampling control signal, so that the counting time period can avoid the moment when the pre-sampled signal changes. In this way, the subsequent data sampling module can sample the pre-sampled signal according to this count value to avoid sampling errors.

[0014] Based on the same inventive concept, an embodiment of the present application further provides a signal sampling method, which can be applied to the signal sampling circuit in some of the foregoing embodiments.

[0015] The signal sampling method includes the following steps. In response to the first sampling valid signal, sample the signal to be sampled and output a pre-sampled signal. Generate a synthesized clock according to the sampling clock, and sample the first sampling valid signal in response to the synthesized clock to obtain a second sampling valid signal. Output a sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock. In response to the sampling clock and the sampling control signal, sample the pre-sampled signal and output a sampled signal.

[0016] The technical effects achievable by the signal sampling circuit in some of the foregoing embodiments can also be achieved by this signal sampling method, and will not be elaborated herein one by one.

[0017] In some embodiments, outputting a sampling control signal according to a second sampling valid signal, a synthesized clock, and a sampling clock includes the following steps. Sampling the second sampling valid signal in response to the synthesized clock, and detecting the level state of the second sampling valid signal to obtain a first detection signal. Sampling the first detection signal in response to the sampling clock, and detecting the level state of the first detection signal to obtain a second detection signal. Outputting the sampling control signal according to the period of the sampling clock and the second detection signal.

[0018] In some embodiments, outputting a sampling control signal according to the period of the sampling clock and the second detection signal includes: after receiving the first rising edge of the second detection signal, counting according to the period of the sampling clock and outputting a count value; the sampling control signal is the count value.

[0019] In some embodiments, generating a synthesized clock according to the sampling clock includes the following steps. Delaying the period of the sampling clock by a preset duration to obtain a delayed clock. Performing a logical operation on the sampling clock and the delayed clock to obtain the synthesized clock.

[0020] In some embodiments, performing a logical operation on the sampling clock and the delayed clock to obtain the synthesized clock includes the following steps. Performing a logical AND on the sampling clock and the delayed clock to obtain a first clock. Performing a logical OR on the sampling clock and the delayed clock, and then performing a logical NOT on the operation result of the logical OR to obtain a second clock. Performing a logical OR on the first clock and the second clock to obtain the synthesized clock. Description of the Drawings

[0021] Figure 1 is a timing diagram of each signal in a sampling circuit in the prior art;

[0022] Figure 2 is a timing diagram of each signal in another sampling circuit in the prior art;

[0023] Figure 3 is a structural block diagram of a signal sampling circuit provided by an embodiment of the present application;

[0024] Figure 4 is a timing diagram of each signal in a signal sampling circuit provided by an embodiment of the present application;

[0025] Figure 5 is a structural block diagram of a sampling control module provided by an embodiment of the present application;

[0026] Figure 6 is a structural block diagram of a clock synthesis circuit provided by an embodiment of the present application;

[0027] Figure 7 The structural block diagram of a level detection circuit provided by an embodiment of the present application;

[0028] Figure 8 The schematic flowchart of a signal sampling method provided by an embodiment of the present application.

[0029] Explanation of reference numerals:

[0030] 100 - pre - sampling module; 200 - sampling control module; 210 - clock synthesis circuit;

[0031] 211 - clock delay circuit; 212 - clock generation circuit; 2121 - first clock generation circuit;

[0032] 2122 - second clock generation circuit; 2123 - synthesis circuit; 220 - synchronous sampling circuit;

[0033] 230 - level detection circuit; 231 - first detection circuit; 232 - second detection circuit;

[0034] 300 - data sampling module. Detailed implementation manners

[0035] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] When using "including", "having", and "comprising" described herein, unless a clear limiting term is used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, terms in the singular form can include the plural form and should not be construed as having a quantity of one.

[0038] In a digital circuit, a sampling circuit can only sample a signal to be sampled that is generated using the same clock as the sampling circuit. In some cases, the signal to be sampled is the output of a circuit outside the digital circuit, such as the output of an analog circuit within a chip or a circuit outside the chip. Although the clock of the signal to be sampled and the clock of the sampling circuit are of the same origin, since they are not both inside the digital circuit, the phase relationship between the clock of the signal to be sampled and the clock of the sampling circuit is uncertain. Thus, when using the sampling circuit for sampling, if the signal to be sampled is changing exactly at that time, sampling errors will occur. In addition, it is also necessary to ensure that the sampling clock and the main clock of the digital circuit are in the same clock domain so that the sampled signal can be processed by the digital circuit.

[0039] The following uses specific examples to illustrate the above problems.

[0040] In one example, as Figure 1 shown, assume that the signal to be sampled D changes at the falling edge of the valid flag SA of the signal to be sampled. Then sampling the signal to be sampled D at the rising edge of the valid flag SA of the signal to be sampled will not result in sampling errors because this sampling will avoid the moment when the signal to be sampled D changes. However, if the valid flag SA of the signal to be sampled is used as the sampling clock and its rising edge is used to sample the signal to be sampled D, there will still be a problem, that is, the clock domain of the sampled result output after sampling is not the clock domain where the sampling clock is located. Since the sampling clock and the main clock of the digital circuit are in the same clock domain, the sampled result after sampling cannot be processed subsequently by the digital circuit.

[0041] In another example, as Figure 2 shown, the frequency of the sampling clock CLK_S is twice the frequency of the signal to be sampled D. Assume that the sampling circuit samples the signal to be sampled D at the rising edge of the sampling clock CLK_S. Then when the sampling circuit samples, the signal to be sampled D may be changing, which will cause sampling error problems. Moreover, the sampled output OUT of the signal valid flag will continuously be in a low-level state, so it is impossible to determine when it is appropriate to sample the signal to be sampled D.

[0042] In existing methods, sampling errors can be avoided by slightly offsetting the phase of the sampling clock and the signal to be sampled. However, it is quite difficult to control the phase relationship between a signal outside the digital circuit and the clock inside the digital circuit because their phase relationship is not determined and this phase relationship is affected by environmental temperature, fabrication process, and voltage in the circuit.

[0043] Based on this, this application hopes to provide a solution that can solve the above technical problems, and its detailed content will be elaborated in subsequent embodiments.

[0044] Please refer to Figure 3, an embodiment of the present application provides a signal sampling circuit, including: a pre-sampling module 100, a sampling control module 200, and a data sampling module 300.

[0045] The pre-sampling module 100 is configured to: in response to a first sampling valid signal SA1, sample a signal D to be sampled and output a pre-sampled signal Pre_D.

[0046] It should be noted that for the signal D to be sampled, due to delays at the chip level or outside the chip, the signal D to be sampled cannot change strictly at the rising edge or falling edge of the first sampling valid signal SA1, which is not conducive to subsequent processing.

[0047] In some examples, as Figure 4 shown, the signal D to be sampled and the first sampling valid signal SA1 have the same period, and the frequency of the sampling clock CLK_S is twice the frequency of the signal D to be sampled. The signal D to be sampled changes at the falling edge of the first sampling valid signal SA1. The pre-sampling module 100 can sample the signal D to be sampled at the rising edge of the first sampling valid signal SA1 (the values of the signal D to be sampled at different times are, for example, D0, D1, and D2) to output the pre-sampled signal Pre_D. In this way, the pre-sampled signal Pre_D will change strictly at the rising edge of the first sampling valid signal SA1.

[0048] The sampling control module 200 is configured to: generate a synthesized clock according to the sampling clock CLK_S, and sample the first sampling valid signal SA1 in response to the synthesized clock to obtain a second sampling valid signal SA2; and output a sampling control signal SC according to the second sampling valid signal SA2, the synthesized clock, and the sampling clock CLK_S.

[0049] The data sampling module 300 is respectively connected to the pre-sampling module 100 and the sampling control module 200, and is configured to: sample the pre-sampled signal Pre_D in response to the sampling clock CLK_S and the sampling control signal SC and output a sampled signal SF.

[0050] In the above signal sampling circuit, the pre-sampling module 100 samples the signal to be sampled D in response to the first valid signal SA1 and outputs a pre-sampled signal Pre_D, so as to strictly control the pre-sampled signal Pre_D at the level change of the first sampling valid signal SA1. Moreover, the sampling control module 200 can generate a synthesized clock according to the sampling clock CLK_S, sample the first sampling valid signal SA1 in response to the synthesized clock to obtain a second sampling valid signal SA2, and output a sampling control signal SC according to the second sampling valid signal SA2, the synthesized clock, and the sampling clock CLK_S. In this way, the second sampling valid signal SA2 obtained by the sampling control module 200 takes into account the uncertainties caused by the inconsistent clock domains of the first sampling valid signal SA1 and the sampling clock CLK_S and can have a periodic and stable output. On this basis, the sampling control module 200 outputs the sampling control signal SC according to the second sampling valid signal SA1, the synthesized clock, and the sampling clock CLK_S, which can ensure a relatively fixed phase delay between the sampling control signal SC and the first sampling valid signal SA1 when it is difficult to accurately determine the phase relationship between the sampling clock CLK_S and the signal to be sampled D. Thus, the data sampling module 300 samples the pre-sampled signal Pre_D in response to the sampling clock CLK_S and the sampling control signal SC provided by the sampling control module 200 and outputs a sampling signal SF. When the frequency of the sampling clock CLK_S is twice the frequency of the signal to be sampled D, it can ensure sampling in the non-changing state of the pre-sampled signal Pre_D, thereby obtaining an accurate sampling signal SF to effectively avoid sampling errors.

[0051] It can be seen that the signal sampling circuit in the present application can achieve accurate sampling without determining the phase relationship between the sampling clock CLK_S and the signal to be sampled D, and can effectively improve the signal sampling efficiency and yield.

[0052] In some embodiments, please refer to Figures 4 to 7 for understanding that the sampling control module 200 includes: a clock synthesis circuit 210, a synchronous sampling circuit 220, a level detection circuit 230, and a sampling controller 240.

[0053] The clock synthesis circuit 210 is configured to: generate a synthesized clock CLK_C according to the sampling clock CLK_S. Figure 4 Here, Time1 is the rising edge time a~h of the synthesized clock CLK_C, and Time2 is the rising edge time i~k of the sampling clock CLK_S.

[0054] Exemplarily, please refer to Figure 6 . The clock synthesis circuit 210 includes: a clock delay circuit 211 and a clock generation circuit 212.

[0055] The clock delay circuit 211 is configured to: delay the period of the sampling clock CLK_S by a preset duration to output a delayed clock CLK_D. The preset duration can be selected and set according to actual requirements. Optionally, as Figure 4 shown, the preset duration is 1 / 4 of the period of the sampling clock CLK_S.

[0056] The clock generation circuit 212 is connected to the clock delay circuit 211 and is configured to: perform a logical operation on the sampling clock CLK_S and the delayed clock CLK_D to output a synthesized clock CLK_C.

[0057] In some examples, please continue to refer to Figure 4 and Figure 6 , the clock generation circuit 212 includes: a first clock generation circuit 2121, a second clock generation circuit 2122, and a synthesis circuit 2123.

[0058] The first clock generation circuit 2121 is configured to: perform a logical AND on the sampling clock CLK_S and the delayed clock CLK_D to output a first clock CLK1.

[0059] The second clock generation circuit 2122 is configured to: first perform a logical OR on the sampling clock CLK_S and the delayed clock CLK_D, and then perform a logical NOT on the result of the logical OR operation to output a second clock CLK2.

[0060] The synthesis circuit CLK_C is connected to the first clock generation circuit 2121 and the second clock generation circuit 2122 respectively, and is configured to: perform a logical OR on the first clock CLK1 and the second clock CLK2 to output a synthesized clock CLK_C.

[0061] The synchronous sampling circuit 220 is connected to the clock synthesis circuit 210 and is configured to: sample the first sampling valid signal SA1 in response to the synthesized clock CLK_C to output a second sampling valid signal SA2.

[0062] As Figure 4 shown, since the clock domain of the synthesized clock CLK_C is inconsistent with the clock domain of the first sampling valid signal SA1, when the first sampling valid signal SA1 changes, the result obtained is an uncertain value. Figure 4 The x in the second sampling valid signal SA2 in

[0063] The level detection circuit 230 is respectively connected to the clock synthesis circuit 210 and the synchronous sampling circuit 220, and is configured to: sample the second sampling valid signal SA2 in response to the synthesized clock CLK_C, and detect the level state of the second sampling valid signal SA2 to obtain a first detection signal T1; and sample the first detection signal T1 in response to the sampling clock CLK_S, and detect the level state of the first detection signal T1 to obtain a second detection signal T2.

[0064] The sampling controller 240 is connected to the level detection circuit 230, and is configured to: output a sampling control signal SC according to the period of the second detection signal T2 and the sampling clock CLK_S.

[0065] In some embodiments, refer to Figure 7 , the level detection circuit 230 includes: a first detection circuit 231 and a second detection circuit 232.

[0066] The first detection circuit 231 is respectively connected to the clock synthesis circuit 210 and the synchronous sampling circuit 220, and is configured to: sample the second sampling valid signal SA2 in response to the synthesized clock CLK_C, and detect the rising edge state of the second sampling valid signal SA2 to output a first detection signal T1.

[0067] The second detection circuit 232 is connected to the first detection circuit 231, and is configured to: sample the first detection signal T1 in response to the sampling clock CLK_S, and detect the rising edge state of the first detection signal T1 to output a second detection signal T2.

[0068] Moreover, the sampling controller 240 is connected to the second detection circuit 232, and is configured to: after receiving the first rising edge of the second detection signal T2, count according to the period of the sampling clock CLK_S and output a count value; the sampling control signal SC is the count value.

[0069] In the above signal sampling circuit, the first detection circuit 231 can detect the rising edge state of the second sampling valid signal SA2 and output a first detection signal T1. The second detection circuit 232 can sample and detect the rising edge state of the first detection signal T1 based on the sampling clock CLK_S and output a second detection signal T2. In this way, the rising edge or falling edge of the second detection signal T2 can be in the clock domain of the sampling clock CLK_S. Moreover, after the sampling controller 240 receives the first rising edge of the second detection signal T2, it will count according to the period of the sampling clock CLK_S and output a count value, that is, output a sampling control signal SC, so that the counting time period can avoid the moment when the pre-sampling signal Pre_D changes. In this way, the subsequent data sampling module 300 can sample the pre-sampling signal according to this count value to avoid sampling errors.

[0070] The following is combined with Figure 4 the examples in Figure 4 to illustrate the first detection circuit 231, the second detection circuit 232, and the sampling controller 240.

[0071] As Figure 4 shown, due to the existence of the uncertain value x, the first detection signal T1 will also have two cases ( Figure 4 T1-1 or T1-2 in Figure 4 ). For example, at the rising edge c of the synthesized clock CLK_C, the first detection signal T1 may be at a low level (such as Figure 4 T1-1 in Figure 4 ), or may be at a high level (such as Figure 4 T1-2 in Figure 4 ). Regardless of which case the first detection signal T1 is in, the output result of the second detection signal T2 is the same, and the rising edge of the second detection signal T2 is in the clock domain of the sampling clock CLK_S. In addition, the delay between the rising edge of the second detection signal T2 and the first sampling valid flag SA1 is relatively fixed. For any relative phase relationship between the sampling clock CLK_S and the first sampling valid flag SA1, the difference in this delay is within half a period of the sampling clock CLK_S.

[0072] After receiving the first rising edge of the second detection signal T2, the sampling controller 240 counts once every 2 cycles according to the sampling clock CLK_S and outputs a count value. The period of the count value is fixed, and the sampling controller 240 will output 1 or 2 as the count value.

[0073] Next, the data sampling module 300 can sample the pre-sampled signal Pre_D based on the sampling clock CLK_S at a fixed count value and output a sampling signal SF. In this way, the sampling signal SF can be synchronized to the sampling clock CLK_S. Among them, the fixed count value can be set based on the delay between the rising edge of the aforementioned second detection signal T2 and the first sampling valid flag SA1. In the Figure 4 example shown, the fixed count value is the count value output by the sampling controller 240 at 1. Since the difference in the above delay is within half a period of the sampling clock CLK_S, so Figure 4 the time period corresponding to the count value of 1 in Figure 4 avoids the moment when the pre-sampled signal Pre_D changes, thereby avoiding sampling errors.

[0074] Based on the same inventive concept, the embodiment of the present application also provides a signal sampling method, which can be applied to the signal sampling circuit in some of the foregoing embodiments.

[0075] Please refer to Figure 8 , the signal sampling method includes steps S10 to S40.

[0076] S10. In response to a first sampling valid signal, sample the signal to be sampled and output a pre-sampled signal.

[0077] S20. Generate a synthesized clock according to a sampling clock, and sample the first sampling valid signal in response to the synthesized clock to obtain a second sampling valid signal.

[0078] S30. Output a sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock.

[0079] S40. In response to the sampling clock and the sampling control signal, sample the pre-sampled signal and output a sampled signal.

[0080] The technical effects achievable by the signal sampling circuit in some of the foregoing embodiments can also be achieved by this signal sampling method, and will not be elaborated herein one by one.

[0081] In some embodiments, generating a synthesized clock according to a sampling clock includes steps S21 and S22.

[0082] S21. Delay the period of the sampling clock by a preset duration to obtain a delayed clock.

[0083] S22. Perform a logical operation on the sampling clock and the delayed clock to obtain a synthesized clock.

[0084] In some embodiments, step S22 includes steps S221 to S223.

[0085] S221. Perform a logical AND on the sampling clock and the delayed clock to obtain a first clock.

[0086] S222. Perform a logical OR on the sampling clock and the delayed clock, and then perform a logical NOT on the operation result of the logical OR to obtain a second clock.

[0087] S223. Perform a logical OR on the first clock and the second clock to obtain a synthesized clock.

[0088] In some embodiments, step S30 includes steps S31 to S33.

[0089] S31. Sample the second sampling valid signal in response to the synthesized clock, and detect the level state of the second sampling valid signal to obtain a first detection signal.

[0090] S32. Sample the first detection signal in response to the sampling clock, and detect the level state of the first detection signal to obtain a second detection signal.

[0091] S33. Output a sampling control signal according to the period of the sampling clock and the second detection signal.

[0092] In some embodiments, step S33 includes: after receiving the first rising edge of the second detection signal, counting according to the period of the sampling clock and outputting a count value; the sampling control signal is the count value.

[0093] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0094] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A signal sampling circuit, characterized in that, Comprising: A pre-sampling module, configured to: sample a signal to be sampled in response to a first sampling valid signal and output a pre-sampled signal; A sampling control module, configured to: generate a synthesized clock according to a sampling clock, and sample the first sampling valid signal in response to the synthesized clock to obtain a second sampling valid signal; And output a sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock; A data sampling module, connected to the pre-sampling module and the sampling control module respectively, configured to: sample the pre-sampled signal in response to the sampling clock and the sampling control signal and output a sampled signal; The generating the synthesized clock according to the sampling clock includes: delaying the period of the sampling clock by a preset duration to obtain a delayed clock; performing a logical operation on the sampling clock and the delayed clock to obtain the synthesized clock; Outputting the sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock includes: Sampling the second sampling valid signal in response to the synthesized clock, and detecting the level state of the second sampling valid signal to obtain a first detection signal; Sampling the first detection signal in response to the sampling clock, and detecting the level state of the first detection signal to obtain a second detection signal; Outputting the sampling control signal according to the period of the sampling clock and the second detection signal.

2. The signal sampling circuit according to claim 1, wherein The sampling control module includes: A clock synthesis circuit, configured to: generate a synthesized clock according to a sampling clock; A synchronous sampling circuit, connected to the clock synthesis circuit, configured to: sample the first sampling valid signal in response to the synthesized clock to output a second sampling valid signal; A level detection circuit, connected to the clock synthesis circuit and the synchronous sampling circuit respectively, configured to: sample the second sampling valid signal in response to the synthesized clock, and detect the level state of the second sampling valid signal to obtain a first detection signal; and sample the first detection signal in response to the sampling clock and detect the level state of the first detection signal to obtain a second detection signal; A sampling controller, connected to the level detection circuit, configured to: output the sampling control signal according to the second detection signal and the period of the sampling clock.

3. The signal sampling circuit according to claim 2, wherein The clock synthesis circuit includes: A clock delay circuit, configured to: delay the period of the sampling clock by a preset duration to output a delayed clock; A clock generation circuit, connected to the clock delay circuit, configured to: perform a logical operation on the sampling clock and the delayed clock to output the synthesized clock.

4. The signal sampling circuit according to claim 3, wherein The clock generation circuit includes: A first clock generation circuit, configured to: perform a logical AND on the sampling clock and the delayed clock to output a first clock; A second clock generation circuit, configured to: first perform a logical OR on the sampling clock and the delayed clock, and then perform a logical NOT on the operation result of the logical OR to output a second clock; A synthesis circuit, connected to the first clock generation circuit and the second clock generation circuit respectively, is configured to: perform a logical OR operation on the first clock and the second clock to output the synthesized clock.

5. The signal sampling circuit according to claim 2, wherein The level detection circuit includes: A first detection circuit, connected to the clock synthesis circuit and the synchronous sampling circuit respectively, is configured to: sample the second sampling valid signal in response to the synthesized clock and detect the rising edge state of the second sampling valid signal to output the first detection signal; A second detection circuit, connected to the first detection circuit, is configured to: sample the first detection signal in response to the sampling clock and detect the rising edge state of the first detection signal to output the second detection signal; Wherein, the sampling controller is connected to the second detection circuit and is configured to: after receiving the first rising edge of the second detection signal, count according to the period of the sampling clock and output a count value; the sampling control signal is the count value.

6. A signal sampling method, characterized in that, It includes: Sampling the signal to be sampled in response to the first sampling valid signal and outputting a pre-sampled signal; Generating a synthesized clock according to the sampling clock, and sampling the first sampling valid signal in response to the synthesized clock to obtain a second sampling valid signal; Outputting a sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock; Sampling the pre-sampled signal in response to the sampling clock and the sampling control signal and outputting a sampled signal; The generating the synthesized clock according to the sampling clock includes: delaying the period of the sampling clock by a preset duration to obtain a delayed clock; performing a logical operation on the sampling clock and the delayed clock to obtain the synthesized clock; Outputting the sampling control signal according to the second sampling valid signal, the synthesized clock, and the sampling clock includes: Sampling the second sampling valid signal in response to the synthesized clock and detecting the level state of the second sampling valid signal to obtain a first detection signal; Sampling the first detection signal in response to the sampling clock and detecting the level state of the first detection signal to obtain a second detection signal; Outputting the sampling control signal according to the period of the sampling clock and the second detection signal.

7. The signal sampling method according to claim 6, wherein The outputting the sampling control signal according to the period of the sampling clock and the second detection signal includes: After receiving the first rising edge of the second detection signal, counting according to the period of the sampling clock and outputting a count value; the sampling control signal is the count value.

8. The signal sampling method according to claim 6, characterized in that, The performing a logical operation on the sampling clock and the delayed clock to obtain the synthesized clock includes: Performing a logical AND operation on the sampling clock and the delayed clock to obtain a first clock; Performing a logical OR operation on the sampling clock and the delayed clock, and then performing a logical NOT operation on the operation result of the logical OR to obtain a second clock; Performing a logical OR operation on the first clock and the second clock to obtain the synthesized clock.

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