A radio frequency pulse signal source generation circuit

Abstract

The present application relates to the technical fields of radio frequency pulse signal source generating circuit, and particularly relates to a radio frequency pulse signal source generating circuit, comprising a frequency source module, a radio frequency switch module, a voltage-controlled gain adjustable module, a digital control attenuation module and a main control module, the main control module is electrically connected with the frequency source module and the digital control attenuation module, the voltage-controlled gain adjustable module is electrically connected with the radio frequency switch module and the digital control attenuation module, the frequency source module communicates with the main control module to obtain corresponding frequency setting code, and the frequency source module sets the corresponding register of the frequency source module according to the data obtained from the main control module; the radio frequency switch module and the voltage-controlled gain adjustable module are set to realize pulse modulation of signals, the signals modulated by the radio frequency switch module are continuously sent to the voltage-controlled gain adjustable module, finally the modulated radio frequency signals are sent to the digital control attenuation module, the purpose of controllable power of the signals sent to the receiver is realized, and then high suppression degree of continuous wave is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency pulse signal source generating circuit, in particular to a radio frequency pulse signal source generating circuit. BACKGROUND

[0002] The prior art uses a variable gain amplifier with three-stage negative voltage control for pulse modulation, which requires first inverting the pulse modulation, and is not only complex in circuit, but also insufficient in modulation depth. SUMMARY

[0003] The present application aims to provide a radio frequency pulse signal source generating circuit, and achieve high suppression of continuous wave.

[0004] To solve the above technical problems, the present application adopts the technical scheme of:

[0005] A radio frequency pulse signal source generating circuit, comprising a frequency source module, a radio frequency switch module, a voltage-controlled gain adjustable module, a digital control attenuation module and a master control module, the master control module is electrically connected with the frequency source module and the digital control attenuation module, the voltage-controlled gain adjustable module is electrically connected with the radio frequency switch module and the digital control attenuation module, and the radio frequency switch module is electrically connected with the frequency source module.

[0006] The present application has the advantages of:

[0007] The frequency source module is electrically connected with the master control module, and the frequency source module communicates with the master control module to obtain a corresponding frequency setting code, the frequency source module sets a corresponding register of the frequency source module according to the data obtained from the master control module, and the frequency source module can generate a corresponding frequency to set a continuous wave signal within a certain range of power size; the radio frequency switch module and the voltage-controlled gain adjustable module are set to realize pulse modulation of the signal, the periodic pulse signal enters the radio frequency switch module to realize time-sharing on-off of the interrogation signal, the signal modulated by the radio frequency switch module is continuously sent to the voltage-controlled gain adjustable module to adjust the output waveform, isolate the continuous wave, adjust the modulation depth, and finally send the modulated radio frequency signal to the digital control attenuation module to realize the purpose of controlling the power size of the signal sent to the receiver, and further realize high suppression of the continuous wave. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 The module connection block diagram of the radio frequency pulse signal source generating circuit according to the present application;

[0009] Figure 2 The circuit principle diagram of the frequency source module of the radio frequency pulse signal source generating circuit according to the present application;

[0010] Figure 3The circuit principle diagram of the RF switch module, the voltage-controlled gain adjustable module and the digital control attenuation module of a RF pulse signal source generating circuit according to the present application;

[0011] Figure 4 The circuit principle diagram of the main control module of a RF pulse signal source generating circuit according to the present application;

[0012] Label explanation:

[0013] 1, frequency source module; 2, RF switch module; 3, voltage-controlled gain adjustable module; 4, digital control attenuation module; 5, main control module. DETAILED DESCRIPTION

[0014] In order to explain the technical content, the purpose and the effect of the present application in detail, the following will be explained in combination with the embodiments and the drawings.

[0015] Please refer to Figure 1 The technical scheme provided by the present application:

[0016] A RF pulse signal source generating circuit, comprising a frequency source module, an RF switch module, a voltage-controlled gain adjustable module, a digital control attenuation module and a main control module, the main control module is electrically connected with the frequency source module and the digital control attenuation module respectively, the voltage-controlled gain adjustable module is electrically connected with the RF switch module and the digital control attenuation module respectively, and the RF switch module is electrically connected with the frequency source module.

[0017] From the above description, the beneficial effects of the present application are as follows:

[0018] The frequency source module is electrically connected with the main control module, the frequency source module communicates with the main control module to obtain the corresponding frequency setting code, the frequency source module sets the corresponding register of the frequency source module according to the data obtained from the main control module, and the frequency source module can generate the corresponding frequency to set the continuous wave signal within a certain range of power size; the RF switch module and the voltage-controlled gain adjustable module are set to realize the pulse modulation of the signal, the periodic pulse signal enters the RF switch module to realize the time-sharing on-off of the interrogation signal, the signal modulated by the RF switch module is continuously sent to the voltage-controlled gain adjustable module to adjust the output waveform, isolate the continuous wave, adjust the modulation depth, and finally send the modulated RF signal to the digital control attenuation module to realize the purpose of controlling the power size of the signal sent to the receiver, and further realize the high suppression degree of the continuous wave.

[0019] Further, the frequency source module comprises a chip N3, the model of the chip N3 is ADF4350, and the twelfth pin of the chip N3 and the thirteenth pin of the chip N3 are electrically connected with the RF switch module respectively.

[0020] As can be known from the above description, the frequency source module realizes fractional N frequency division phase-locked loop (PLL) frequency synthesis by combining the external loop filter and the external reference frequency through the chip N3. The external reference frequency adopts a 13MHz active crystal oscillator. The register parameters are set through the SPI interface.

[0021] Further, the radio frequency switch module includes a resistor R1, a resistor R2, a capacitor C1, a capacitor C6, a capacitor C7, a connector X2, a connector X4 and a chip S1, a second pin of the chip S1 is electrically connected with a third pin of the chip S1, and the second pin and the third pin of the chip S1 are grounded, a fifth pin of the chip S1 is electrically connected with one end of the capacitor C1, the other end of the capacitor C1 is electrically connected with the frequency source module, a sixth pin of the chip S1 is electrically connected with one end of the resistor R1, the other end of the resistor R1 is respectively electrically connected with one end of a capacitor C8 and the connector X2, a seventh pin of the chip S1 is electrically connected with one end of the resistor R2, the other end of the resistor R2 is electrically connected with the connector X4, an eighth pin of the chip S1 is electrically connected with one end of the capacitor C7, and the other end of the capacitor C7 is electrically connected with the voltage-controlled gain adjustable module.

[0022] As can be known from the above description, the radio frequency switch module includes a resistor R1, a resistor R2, a capacitor C1, a capacitor C6, a capacitor C7, a connector X2, a connector X4 and a chip S1, and the radio frequency switch module applies a pulse signal to switch control the continuous wave generated by the frequency source module.

[0023] Further, the voltage-controlled gain adjustable module comprises resistor R9, resistor R10, resistor R13, capacitor C9, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, inductor L1, inductor L2, connector X5 and chip N1, the first pin of the chip N1 is electrically connected with one end of the capacitor C9 and one end of the inductor L1 respectively, the other end of the inductor L1 is electrically connected with the ninth pin of the chip N1, the third pin of the chip N1 is electrically connected with one end of the resistor R9, the other end of the resistor R9 is electrically connected with one end of the resistor R13, one end of the capacitor C14, one end of the capacitor C15, one end of the capacitor C16 and one end of the inductor L2 respectively, the other end of the inductor L2 is electrically connected with one end of the capacitor C17 and the sixth pin of the chip N1 respectively, the other end of the capacitor C14 is electrically connected with the other end of the capacitor C15 and the other end of the capacitor C16 respectively and the other end of the capacitor C14, the other end of the capacitor C15 and the other end of the capacitor C16 are grounded, the other end of the capacitor C17 is electrically connected with the digital control attenuation module, the seventh pin of the chip N1 is electrically connected with one end of the resistor R10, the other end of the resistor R10 is electrically connected with one end of the capacitor C13 and the connector X5 respectively, the eighth pin of the chip N1 is electrically connected with the other end of the capacitor C13 and the eighth pin of the chip N1 and the other end of the capacitor C13 are grounded.

[0024] From the above description, the voltage-controlled gain adjustable module realizes the pulse modulation of the radio frequency power by applying the pulse signal on the seventh pin of the chip N1.

[0025] Further, the digital control attenuation module comprises resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R11, resistor R12, resistor R14, resistor R15, resistor R17, resistor R18, resistor R19, resistor R20, voltage stabilizing tube V1, voltage stabilizing tube V2, voltage stabilizing tube V3, voltage stabilizing tube V4, voltage stabilizing tube V5, voltage stabilizing tube V6, inverter D2D, inverter D2E, inverter D2F, inverter D2C, inverter D2B, inverter D2A, capacitor C10, capacitor C11, capacitor C18, connector XS1, chip D1 and chip D3.

[0026] The first pin of the chip D1 is respectively connected with one end of the resistor R3, the second pin of the chip D1, the fourth pin of the chip D1, the sixth pin of the chip D1 and the seventh pin of the chip D1, the third pin of the chip D1 is grounded, the fifth pin of the chip D1 is grounded, the other end of the resistor R3 is connected with the output end of the inverter D2D, the input end of the inverter D2D is connected with the anode of the stabilizing tube V1, the cathode of the stabilizing tube V1 is connected with the master control module, the ninth pin of the chip D1 is respectively connected with the tenth pin of the chip D1, the seventeenth pin of the chip D1 and one end of the resistor R11, the eleventh pin of the chip D1 is respectively connected with the other end of the resistor R11 and one end of the capacitor C12, the other end of the capacitor C12 is connected with the fourteenth pin of the chip D3, the twelfth pin of the chip D1 is connected with the thirteenth pin of the chip D1 and both are grounded, the fourteenth pin of the chip D1 is connected with one end of the capacitor C11, the other end of the capacitor C11 is respectively connected with one end of the resistor R6 and one end of the resistor R4, the other end of the resistor R4 is respectively connected with one end of the resistor R7 and one end of the capacitor C10, the other end of the capacitor C10 is connected with the first pin of the connector XS1, the second pin of the connector XS1, the third pin of the connector XS1, the fourth pin of the connector XS1 and the fifth pin of the connector XS1 are all grounded, the other end of the resistor R6 is connected with the other end of the resistor R7 and both are grounded, the fifteenth pin of the chip D1 is connected with the sixteenth pin of the chip D1 and both are grounded.

[0027] The first pin of the chip D3 is electrically connected with one end of the resistor R5, the other end of the resistor R5 is electrically connected with the output end of the inverter D2E, the input end of the inverter D2E is electrically connected with the anode of the stabilizing tube V2, the cathode of the stabilizing tube V2 is electrically connected with the master control module, the second pin of the chip D3 is electrically connected with one end of the resistor R8, the other end of the resistor R8 is electrically connected with the output end of the inverter D2F, the input end of the inverter D2F is electrically connected with the anode of the stabilizing tube V3, the cathode of the stabilizing tube V3 is electrically connected with the master control module, the third pin of the chip D3 is grounded, the fourth pin of the chip D3 is electrically connected with one end of the resistor R12, the other end of the resistor R12 is electrically connected with the output end of the inverter D2C, the input end of the inverter D2C is electrically connected with the anode of the stabilizing tube V4, the cathode of the stabilizing tube V4 is electrically connected with the master control module, the fifth pin of the chip D3 is grounded, the sixth pin of the chip D3 is electrically connected with one end of the resistor R14, the other end of the resistor R14 is electrically connected with the output end of the inverter D2B, the input end of the inverter D2B is electrically connected with the anode of the stabilizing tube V5, the cathode of the stabilizing tube V5 is electrically connected with the master control module, the seventh pin of the chip D3 is electrically connected with one end of the resistor R15, the other end of the resistor R15 is electrically connected with the output end of the inverter D2A, the input end of the inverter D2A is electrically connected with the anode of the stabilizing tube V6, the cathode of the stabilizing tube V6 is electrically connected with the master control module, the ninth pin of the chip D3 is respectively electrically connected with the tenth pin of the chip D3, the seventeenth pin of the chip D3 and one end of the resistor R19, and the ninth pin of the chip D3, the tenth pin of the chip D3, the seventeenth pin of the chip D3 and one end of the resistor R19 are all grounded, the eleventh pin of the chip D3 is respectively electrically connected with the other end of the resistor R19 and one end of the capacitor C18, the other end of the capacitor C18 is respectively electrically connected with one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R17 is respectively electrically connected with one end of the resistor R20 and the voltage-controlled gain adjustable module.

[0028] As can be seen from the above description, the numerical control attenuation module reverses the I / O level input by the master control module, and then applies it to the first pin, the second pin, the fourth pin, the sixth pin and the seventh pin of the chip D1 and the chip D3, so as to finally realize the adjustment of the output power value.

[0029] Further, the master control module comprises a chip N5, the model of the chip N5 is STM32F103, the fourteenth pin of the chip N5, the fifteenth pin of the chip N5, the sixteenth pin of the chip N5, the seventeenth pin of the chip N5 and the thirty-second pin of the chip N5 are electrically connected with the radio frequency switch module respectively, the twenty-fifth pin of the chip N5, the twenty-sixth pin of the chip N5, the twenty-seventh pin of the chip N5, the twenty-eighth pin of the chip N5 and the twenty-ninth pin of the chip N5 are electrically connected with the numerical control attenuation module respectively.

[0030] From the above description, the master control module sets the parameters of the frequency source module through the fourteenth pin, the fifteenth pin, the sixteenth pin and the seventeenth pin of the chip N5, and controls the attenuation amount of the numerical control attenuation module through the I / O interface.

[0031] Please refer to Figures 1 to 4 , the embodiment one of the application is:

[0032] Please refer to Figure 1 A radio frequency pulse signal source generating circuit, comprising a frequency source module 1, a radio frequency switch module 2, a voltage-controlled gain adjustable module 3, a numerical control attenuation module 4 and a master control module 5, the master control module 5 is electrically connected with the frequency source module 1 and the numerical control attenuation module 4 respectively, the voltage-controlled gain adjustable module 3 is electrically connected with the radio frequency switch module 2 and the numerical control attenuation module 4 respectively, and the radio frequency switch module 2 is electrically connected with the frequency source module 1.

[0033] Please refer to Figure 2 The frequency source module 1 comprises a chip N3, the model of the chip N3 is ADF4350, the twelfth pin of the chip N3 and the thirteenth pin of the chip N3 are electrically connected with the radio frequency switch module 2 respectively.

[0034] The frequency source module 1 further comprises a resistor R21 (2kΩ), a resistor R23 (2kΩ), a capacitor C33 (1μF), a capacitor C34 (0.01μF), a resistor R24 (0Ω), a capacitor C35 (1nF), a capacitor C36 (1nF), a connector N4, a capacitor C26 (0.1μF), a capacitor C25 (0.1μF), a capacitor C27 (10pF), a capacitor C28 (10pF), a resistor R22 (4.7kΩ), a resistor R25 (1kΩ), a light emitting diode H1, a resistor R27 (0Ω), a resistor R26 (330Ω), a resistor R28 (100Ω), a capacitor C37 (22nF), a capacitor C38 (680nF), a capacitor C39 (680pF), a resistor R29 (120Ω), a resistor R30 (0Ω), a capacitor C44 (10pF), a capacitor C45 (0.1μF), a capacitor C42 (10pF), a capacitor C43 (0.1μF), a capacitor C40 (10pF), a capacitor C41 (0.1μF), a capacitor C46 (2.2pF), an inductor L3 (12nH), an inductor L4 (12nH), an inductor L5 (39nH), a capacitor C49 (2.2pF), a capacitor C47 (10pF), a capacitor C48 (100pF), a capacitor C52 (10pF), a capacitor C55 (0.1μF), a capacitor C50 (10pF), a capacitor C53 (0.1μF), a capacitor C51 (10pF), and a capacitor C54 (0.1μF). The specific connection relationship among the components of the frequency source module 1 is shown in FIG. 1. Figure 2 ;

[0035] The specific connection relationship among the components of the frequency source module 1 is shown in FIG. 1. Figure 3, the radio frequency switch module 2 includes resistance R1 (resistance value is 0 Ω), resistance R2 (resistance value is 0 Ω), capacitor C1 (capacitance value is 330 pF), capacitor C6 (capacitance value is 1 nF), capacitor C7 (capacitance value is 330 pF), connector X2, connector X4 and chip S1 (model is HMC1055), the second pin of the chip S1 is electrically connected with the third pin of the chip S1 and both the second pin of the chip S1 and the third pin of the chip S1 are grounded, the fifth pin of the chip S1 is electrically connected with one end of the capacitor C1, the other end of the capacitor C1 is electrically connected with the frequency source module 1, the sixth pin of the chip S1 is electrically connected with one end of the resistance R1, the other end of the resistance R1 is respectively electrically connected with one end of the capacitor C8 and the connector X2, the seventh pin of the chip S1 is electrically connected with one end of the resistance R2, the other end of the resistance R2 is electrically connected with the connector X4, the eighth pin of the chip S1 is electrically connected with one end of the capacitor C7, the other end of the capacitor C7 is electrically connected with the voltage-controlled gain adjustable module 3.

[0036] Please refer to Figure 3 , the voltage-controlled gain adjustable module 3 includes resistance R9 (resistance value is 1 kΩ), resistance R10 (resistance value is 0 Ω), resistance R13 (resistance value is 0 Ω), capacitor C9 (capacitance value is 2.2 nF), capacitor C13 (capacitance value is 200 pF), capacitor C14 (capacitance value is 2.2 μF), capacitor C15 (capacitance value is 0.1 μF), capacitor C16 (capacitance value is 10 pF), capacitor C17 (capacitance value is 100 pF), inductor L1 (inductance value is 82 nH), inductor L2 (inductance value is 82 nH), connector X5 and chip N1 (model is ALM80110), the first pin of the chip N1 is respectively electrically connected with one end of the capacitor C9 and one end of the inductor L1, the other end of the inductor L1 is electrically connected with the ninth pin of the chip N1, the third pin of the chip N1 is electrically connected with one end of the resistance R9, the other end of the resistance R9 is respectively electrically connected with one end of the resistance R13, one end of the capacitor C14, one end of the capacitor C15, one end of the capacitor C16 and one end of the inductor L2, the other end of the inductor L2 is respectively electrically connected with one end of the capacitor C17 and the seventh pin of the chip N1, the other end of the capacitor C14 is respectively electrically connected with the other end of the capacitor C15 and the other end of the capacitor C16 and the other end of the capacitor C14, the other end of the capacitor C15 and the other end of the capacitor C16 are all grounded, the other end of the capacitor C17 is electrically connected with the digital control attenuation module 4, the seventh pin of the chip N1 is electrically connected with one end of the resistance R10, the other end of the resistance R10 is respectively electrically connected with one end of the capacitor C13 and the connector X5, the eighth pin of the chip N1 is electrically connected with the other end of the capacitor C13 and the eighth pin of the chip N1 and the other end of the capacitor C13 are all grounded.

[0037] Please refer to Figure 3 , the digital attenuation module 4 includes resistance R3 (resistance value is 100Ω), resistance R4 (resistance value is 5.6Ω), resistance R5 (resistance value is 100Ω), resistance R6 (resistance value is 910Ω), resistance R7 (resistance value is 910Ω), resistance R8 (resistance value is 100Ω), resistance R11 (resistance value is 4.7kΩ), resistance R12 (resistance value is 100Ω), resistance R14 (resistance value is 100Ω), resistance R15 (resistance value is 100Ω), resistance R17 (resistance value is 5.6kΩ), resistance R18 (resistance value is 910Ω), resistance R19 (resistance value is 4.7kΩ), resistance R20 (resistance value is 910Ω), voltage stabilizer V1, voltage stabilizer V2, voltage stabilizer V3, voltage stabilizer V4, voltage stabilizer V5, voltage stabilizer V6, inverter D2D (model number is SNJ54LSO4FK), inverter D2E (model number is SNJ54LSO4FK), inverter D2F (model number is SNJ54LSO4FK), inverter D2C (model number is SNJ54LSO4FK), inverter D2B (model number is SNJ54LSO4FK), inverter D2A (model number is SNJ54LSO4FK), capacitor C10 (capacitance value is 2200pF), capacitor C11 (capacitance value is 2200pF), capacitor C18 (capacitance value is 2200pF), connector XS1 (model number is SMA-KHD), chip D1 (model number is HMC307) and chip D3 (model number is HMC307);

[0038] The first pin of the chip D1 is respectively connected with one end of the resistor R3, the second pin of the chip D1, the fourth pin of the chip D1, the sixth pin of the chip D1 and the seventh pin of the chip D1, the third pin of the chip D1 is grounded, the fifth pin of the chip D1 is grounded, the other end of the resistor R3 is connected with the output end of the inverter D2D, the input end of the inverter D2D is connected with the anode of the stabilizing tube V1, the cathode of the stabilizing tube V1 is connected with the master control module 5, the ninth pin of the chip D1 is respectively connected with the tenth pin of the chip D1, the seventeenth pin of the chip D1 and one end of the resistor R11, the eleventh pin of the chip D1 is respectively connected with the other end of the resistor R11 and one end of the capacitor C12, the other end of the capacitor C12 is connected with the fourteenth pin of the chip D3, the twelfth pin of the chip D1 is connected with the thirteenth pin of the chip D1 and both are grounded, the fourteenth pin of the chip D1 is connected with one end of the capacitor C11, the other end of the capacitor C11 is respectively connected with one end of the resistor R6 and one end of the resistor R4, the other end of the resistor R4 is respectively connected with one end of the resistor R7 and one end of the capacitor C10, the other end of the capacitor C10 is connected with the first pin of the connector XS1, the second pin of the connector XS1, the third pin of the connector XS1, the fourth pin of the connector XS1 and the fifth pin of the connector XS1 are all grounded, the other end of the resistor R6 is connected with the other end of the resistor R7 and both are grounded, the fifteenth pin of the chip D1 is connected with the sixteenth pin of the chip D1 and both are grounded;

[0039] The first pin of the chip D3 is electrically connected with one end of the resistor R5, the other end of the resistor R5 is electrically connected with the output end of the inverter D2E, the input end of the inverter D2E is electrically connected with the anode of the stabilizing tube V2, the cathode of the stabilizing tube V2 is electrically connected with the master control module 5, the second pin of the chip D3 is electrically connected with one end of the resistor R8, the other end of the resistor R8 is electrically connected with the output end of the inverter D2F, the input end of the inverter D2F is electrically connected with the anode of the stabilizing tube V3, the cathode of the stabilizing tube V3 is electrically connected with the master control module 5, the third pin of the chip D3 is grounded, the fourth pin of the chip D3 is electrically connected with one end of the resistor R12, the other end of the resistor R12 is electrically connected with the output end of the inverter D2C, the input end of the inverter D2C is electrically connected with the anode of the stabilizing tube V4, the cathode of the stabilizing tube V4 is electrically connected with the master control module 5, the fifth pin of the chip D3 is grounded, the sixth pin of the chip D3 is electrically connected with one end of the resistor R14, the other end of the resistor R14 is electrically connected with the output end of the inverter D2B, the input end of the inverter D2B is electrically connected with the anode of the stabilizing tube V5, the cathode of the stabilizing tube V5 is electrically connected with the master control module 5, the seventh pin of the chip D3 is electrically connected with one end of the resistor R15, the other end of the resistor R15 is electrically connected with the output end of the inverter D2A, the input end of the inverter D2A is electrically connected with the anode of the stabilizing tube V6, the cathode of the stabilizing tube V6 is electrically connected with the master control module 5, the ninth pin of the chip D3 is respectively electrically connected with the tenth pin of the chip D3, the seventeenth pin of the chip D3 and one end of the resistor R19, and the ninth pin of the chip D3, the tenth pin of the chip D3, the seventeenth pin of the chip D3 and one end of the resistor R19 are all grounded, the eleventh pin of the chip D3 is respectively electrically connected with the other end of the resistor R19 and one end of the capacitor C18, the other end of the capacitor C18 is respectively electrically connected with one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R17 is respectively electrically connected with one end of the resistor R20 and the voltage-controlled gain adjustable module 3.

[0040] Please refer to Figure 4 , the master control module 5 comprises a chip N5 (model STM32F103), the model of the chip N5 is STM32F103, the fourteenth pin of the chip N5, the fifteenth pin of the chip N5, the sixteenth pin of the chip N5, the seventeenth pin of the chip N5 and the thirty-second pin of the chip N5 are all respectively electrically connected with the radio frequency switch module 2, the twenty-fifth pin of the chip N5, the twenty-sixth pin of the chip N5, the twenty-seventh pin of the chip N5, the twenty-eighth pin of the chip N5 and the twenty-ninth pin of the chip N5 are all respectively electrically connected with the digital control attenuation module 4.

[0041] The main control module 5 further comprises a capacitor C57 (22pF), a crystal oscillator N6 (12MHz), a capacitor C62 (22pF), a capacitor C61 (0.1μF), a capacitor C63 (0.1μF), a capacitor C64 (0.01μF), a capacitor C65 (0.1μF), a switch S2 (TD-13XAX-A00), a capacitor C58 (10μF), a capacitor C59 (0.1μF), a resistor R31 (10kΩ), a connector XS2, a capacitor C60 (0.1μF), a capacitor C67 (30pF), a capacitor C68 (30pF), a capacitor C69 (30pF), a capacitor C70 (30pF), a resistor R33 (10kΩ), a capacitor C66 (0.1μF), and a connector RN1, and the specific connection relationship among the components is shown in the following table. Figure 4 .

[0042] The digital control attenuation module 4 comprises a front-end resistance attenuation network, an inverter chip, a controllable attenuator chip, and an inter-stage resistance attenuation network, and uses two 5-bit controllable attenuator chips combined with the control signal of a microprocessor to realize the peak value adjustment of the radio frequency signal. The attenuation code of the controllable attenuator chip (i.e. chip D1 and chip D3) is provided by chip N5 of the main control module 5. Two HMC307 chips are used, one of which realizes 5-bit attenuation values of 16dB, 8dB, 4dB, 2dB, and 1dB, and the other realizes 5-bit cascaded attenuation values of 31dB, so that the maximum attenuation value range that can be realized is 62dB.

[0043] The scheme obtains the current required working frequency and signal size information from the host computer through serial communication, and converts them into corresponding frequency code and attenuation code, which are sent to the frequency synthesizer chip (i.e. chip N3) and the controllable attenuator chip (i.e. chip D1 and chip D3) respectively. The frequency synthesizer chip generates a continuous radio frequency signal of a certain frequency according to the frequency code, which is sent to the radio frequency switch chip (i.e. chip S1) controlled by the clock pulse, and then sent into the variable gain amplifier controlled by the clock pulse after switch modulation. After two-stage modulation, the signal is sent into the attenuator to control the output amplitude of the signal to generate an appropriate analog ranging interrogation signal.

[0044] The setting of the attenuation value of the controllable attenuator chip is also set by the chip N5 of the main control module 5, and when the frequency synthesizer chip (i.e. the chip N3) is used in combination with an external loop filter and an external reference frequency, a decimal N frequency division or an integer N phase-locked (PLL) frequency synthesizer can be realized. The reference frequency adopts a 13MHz active crystal oscillator. The RF N frequency divider in the chip can provide a frequency division ratio in the PLL feedback path, and the frequency division ratio is determined by the values of INT, FRAC and MOD constituting the frequency divider; the output of the frequency synthesizer chip (i.e. the chip N3) is in a differential structure, and a balun structure can be realized by using discrete inductive elements.

[0045] The index test table of the radio frequency pulse signal source generating circuit designed by the scheme is as shown in Table 1:

[0046]

[0047] Table 1

[0048] As can be seen from Table 1, the radio frequency pulse signal source generating circuit designed by the scheme has an output pulse signal amplitude adjustable between -70.5dBm and -8.4dBm, and the continuous wave suppression is greater than 70dB.

[0049] In summary, the radio frequency pulse signal source generating circuit provided by the scheme has the frequency source module electrically connected with the main control module, the frequency source module communicates with the main control module to obtain a corresponding frequency setting code, the frequency source module sets a corresponding register of the frequency source module according to the data obtained from the main control module, the frequency source module can generate a corresponding frequency, and a continuous wave signal can be set when the power size is within a certain range; the radio frequency switch module and the voltage-controlled gain adjustable module are set to realize pulse modulation of the signal, the periodic pulse signal enters the radio frequency switch module to realize time-sharing on-off of the interrogation signal, the signal modulated by the radio frequency switch module continues to be sent to the voltage-controlled gain adjustable module, the output waveform is adjusted, the continuous wave is isolated, the modulation depth is adjusted, and finally the modulated radio frequency signal is sent to the digital control attenuation module, so as to realize the purpose of controllable power size of the signal sent to the receiver, and then realize high suppression of the continuous wave.

[0050] The above only describes the embodiments of the present application, and does not limit the patent range of the present application, and any equivalent transformation or direct or indirect application in the related technical field by using the content of the specification and drawings of the present application is also included in the patent protection range of the present application.

Claims

1. A radio frequency pulsed signal source generation circuit, characterized by, The frequency source module, the radio frequency switch module, the voltage-controlled gain adjustable module, the digital control attenuation module and the main control module are included, the main control module is electrically connected with the frequency source module and the digital control attenuation module respectively, the voltage-controlled gain adjustable module is electrically connected with the radio frequency switch module and the digital control attenuation module respectively, and the radio frequency switch module is electrically connected with the frequency source module; The frequency source module communicates with the main control module to obtain corresponding frequency setting codes, the frequency source module sets the corresponding register of the frequency source module according to the data obtained from the main control module, and the frequency source module generates a continuous wave signal with a corresponding frequency and power size that can be set within a certain range; The radio frequency switch module and the voltage-controlled gain adjustable module are used to realize pulse modulation of signals, a periodic pulse signal enters the radio frequency switch module to realize time-sharing on-off of an interrogation signal, the signal modulated by the radio frequency switch module is continuously sent to the voltage-controlled gain adjustable module, the output waveform of the voltage-controlled gain adjustable module is adjusted, the continuous wave is isolated, the modulation depth is adjusted, and finally the modulated radio frequency signal is sent to the digital control attenuation module; The frequency source module includes a chip N3, the model of the chip N3 is ADF4350, the twelfth pin of the chip N3 is electrically connected with the radio frequency switch module, and the thirteenth pin of the chip N3 is electrically connected with the radio frequency switch module; The radio frequency switch module includes a resistor R1, a resistor R2, a capacitor C1, a capacitor C6, a capacitor C7, a connector X2, a connector X4 and a chip S1, the second pin of the chip S1 is electrically connected with the third pin of the chip S1 and grounded, the fifth pin of the chip S1 is electrically connected with one end of the capacitor C1, the other end of the capacitor C1 is electrically connected with the frequency source module, the sixth pin of the chip S1 is electrically connected with one end of the resistor R1, the other end of the resistor R1 is electrically connected with one end of the capacitor C8 and the connector X2 respectively, the seventh pin of the chip S1 is electrically connected with one end of the resistor R2, the other end of the resistor R2 is electrically connected with the connector X4, the eighth pin of the chip S1 is electrically connected with one end of the capacitor C7, and the other end of the capacitor C7 is electrically connected with the voltage-controlled gain adjustable module.

2. The radio frequency pulsed signal source generating circuit of claim 1, wherein, The voltage-controlled gain adjustable module comprises resistors R9, R10, R13, capacitors C9, C13, C14, C15, C16, C17, inductors L1, L2, a connector X5 and a chip N1, one end of the capacitor C9 and one end of the inductor L1 are electrically connected to the first pin of the chip N1, the other end of the inductor L1 is electrically connected to the ninth pin of the chip N1, the third pin of the chip N1 is electrically connected to one end of the resistor R9, the other end of the resistor R9 is electrically connected to one end of the resistor R13, one end of the capacitor C14, one end of the capacitor C15, one end of the capacitor C16 and one end of the inductor L2 respectively, the other end of the inductor L2 is electrically connected to one end of the capacitor C17 and the sixth pin of the chip N1 respectively, the other end of the capacitor C14 is electrically connected to the other end of the capacitor C15 and the other end of the capacitor C16 respectively, and the other end of the capacitor C14, the other end of the capacitor C15 and the other end of the capacitor C16 are all grounded, the other end of the capacitor C17 is electrically connected to a digital control attenuation module, the seventh pin of the chip N1 is electrically connected to one end of the resistor R10, the other end of the resistor R10 is electrically connected to one end of the capacitor C13 and the connector X5 respectively, and the eighth pin of the chip N1 is electrically connected to the other end of the capacitor C13, and the eighth pin of the chip N1 and the other end of the capacitor C13 are both grounded.

3. The radio frequency pulse signal source generating circuit of claim 1, wherein, The digital control attenuation module comprises resistors R3, R4, R5, R6, R7, R8, R11, R12, R14, R15, R17, R18, R19, R20, voltage stabilizing tubes V1, V2, V3, V4, V5, V6, inverters D2D, D2E, D2F, D2C, D2B, D2A, capacitors C10, C11, C18, a connector XS1, a chip D1 and a chip D3. The first pin of the chip D1 is electrically connected with one end of the resistor R3, the second pin of the chip D1, the fourth pin of the chip D1, the sixth pin of the chip D1 and the seventh pin of the chip D1 respectively, the third pin of the chip D1 is grounded, the fifth pin of the chip D1 is grounded, the other end of the resistor R3 is electrically connected with the output end of the inverter D2D, the input end of the inverter D2D is electrically connected with the anode of the stabilizing tube V1, the cathode of the stabilizing tube V1 is electrically connected with the master control module, the ninth pin of the chip D1 is electrically connected with the tenth pin of the chip D1, the seventeenth pin of the chip D1 and one end of the resistor R11 respectively, the eleventh pin of the chip D1 is electrically connected with the other end of the resistor R11 and one end of the capacitor C12 respectively, the other end of the capacitor C12 is electrically connected with the fourteenth pin of the chip D3, the twelfth pin of the chip D1 is electrically connected with the thirteenth pin of the chip D1 and both are grounded, the fourteenth pin of the chip D1 is electrically connected with one end of the capacitor C11, the other end of the capacitor C11 is electrically connected with one end of the resistor R6 and one end of the resistor R4 respectively, the other end of the resistor R4 is electrically connected with one end of the resistor R7 and one end of the capacitor C10 respectively, the other end of the capacitor C10 is electrically connected with the first pin of the connector XS1, the second pin of the connector XS1, the third pin of the connector XS1, the fourth pin of the connector XS1 and the fifth pin of the connector XS1 are all grounded, the other end of the resistor R6 is electrically connected with the other end of the resistor R7 and both are grounded, the fifteenth pin of the chip D1 is electrically connected with the sixteenth pin of the chip D1 and both are grounded. The first pin of the chip D3 is electrically connected with one end of the resistor R5, the other end of the resistor R5 is electrically connected with the output end of the inverter D2E, the input end of the inverter D2E is electrically connected with the anode of the stabilizing tube V2, the cathode of the stabilizing tube V2 is electrically connected with the master control module, the second pin of the chip D3 is electrically connected with one end of the resistor R8, the other end of the resistor R8 is electrically connected with the output end of the inverter D2F, the input end of the inverter D2F is electrically connected with the anode of the stabilizing tube V3, the cathode of the stabilizing tube V3 is electrically connected with the master control module, the third pin of the chip D3 is grounded, the fourth pin of the chip D3 is electrically connected with one end of the resistor R12, the other end of the resistor R12 is electrically connected with the output end of the inverter D2C, the input end of the inverter D2C is electrically connected with the anode of the stabilizing tube V4, the cathode of the stabilizing tube V4 is electrically connected with the master control module, the fifth pin of the chip D3 is grounded, the sixth pin of the chip D3 is electrically connected with one end of the resistor R14, the other end of the resistor R14 is electrically connected with the output end of the inverter D2B, the input end of the inverter D2B is electrically connected with the anode of the stabilizing tube V5, the cathode of the stabilizing tube V5 is electrically connected with the master control module, the seventh pin of the chip D3 is electrically connected with one end of the resistor R15, the other end of the resistor R15 is electrically connected with the output end of the inverter D2A, the input end of the inverter D2A is electrically connected with the anode of the stabilizing tube V6, the cathode of the stabilizing tube V6 is electrically connected with the master control module, the ninth pin of the chip D3 is respectively electrically connected with the tenth pin of the chip D3, the seventeenth pin of the chip D3 and one end of the resistor R19, and the ninth pin of the chip D3, the tenth pin of the chip D3, the seventeenth pin of the chip D3 and one end of the resistor R19 are all grounded, the eleventh pin of the chip D3 is respectively electrically connected with the other end of the resistor R19 and one end of the capacitor C18, the other end of the capacitor C18 is respectively electrically connected with one end of the resistor R17 and one end of the resistor R18, the other end of the resistor R17 is respectively electrically connected with one end of the resistor R20 and the voltage-controlled gain adjustable module.

4. The radio frequency pulse signal source generating circuit of claim 1, wherein, The master control module comprises a chip N5, the model number of the chip N5 is STM32F103, the fourteenth pin of the chip N5, the fifteenth pin of the chip N5, the sixteenth pin of the chip N5, the seventeenth pin of the chip N5 and the thirty-second pin of the chip N5 are all respectively electrically connected with the radio frequency switch module, the twenty-fifth pin of the chip N5, the twenty-sixth pin of the chip N5, the twenty-seventh pin of the chip N5, the twenty-eighth pin of the chip N5 and the twenty-ninth pin of the chip N5 are all respectively electrically connected with the numerical control attenuation module.

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