A phase-locked loop based on double improved adaptive notch filters

Abstract

The present invention discloses a phase-locked loop based on a double improved adaptive notch filter, relates to the technical field of power grid synchronization signal detection, designs an improved adaptive notch filter structure, and proposes a double improved adaptive notch filter with the ability to suppress DC offset and negative sequence voltage as an external filtering link of the phase-locked loop; a sliding average filter is incorporated into the synchronous reference coordinate system phase-locked loop as an internal filtering link to achieve a dual filtering design. The phase-locked loop disclosed by the present invention has the advantages of fast response speed and strong robustness, is suitable for solar power generation, wind power and other new energy grid-connected systems, and can be extended to other three-phase grid-connected inverter control methods and other places where grid synchronization signals need to be obtained.

Description

Technical Field

[0001] The invention relates to the field of phase-locked loop and power grid synchronization signal extraction, in particular to a phase-locked loop based on a double improved adaptive notch filter. Background Art

[0002] With the development of new energy technologies, more and more new energy sources such as wind power and solar power are connected to the grid to provide electric energy to the grid. Obtaining grid synchronization signals such as the frequency, phase and amplitude of the grid voltage is the premise and basis for completing grid-connected operation. The ideal grid phase-locked loop (PLL) technology can effectively detect the grid synchronization signal in real time and has been widely used. However, due to the access of a large number of power electronic loads such as uncontrolled rectification and reactive power compensation to the grid, voltage imbalance or harmonic distortion occurs in the grid. At the same time, the grid-connected generator is required to have a certain fault ride-through capability to maintain a synchronous connection with the grid under the conditions of grid imbalance and harmonics. This has put forward higher requirements for the acquisition of grid voltage synchronization signals.

[0003] Phase-locked loops can be divided into two categories: phase-locked loops based on stationary reference frames and phase-locked loops based on synchronous reference frames (SRF-PLL). SRF-PLL is the most basic phase-locked loop. It is widely concerned because of its simple structure and easy implementation. It can accurately and quickly detect the grid voltage frequency and phase under ideal grid conditions. However, the disadvantage is that in complex grid environments such as grid voltage imbalance, harmonic distortion, and DC bias, the presence of negative sequence components and harmonic components in the input voltage will cause the SRF-PLL to be unable to accurately and quickly extract the grid fundamental positive sequence components, resulting in poor PLL synchronization performance. The structures of many existing PLLs are based on SRF-PLL. The phase-locked loop based on the decoupled dual synchronous reference frame (DDSRF-PLL) can eliminate the influence of the fundamental negative sequence component, but the structure is relatively complex and the calculation is large. At the same time, the newly added low-pass filter will reduce the dynamic response speed. The phase-locked loop based on the sliding average filter (MAF-PLL) can improve the response speed of the phase-locked loop by reducing the window length of the MAF, but it reduces the ability to suppress harmonics and noise. The dual adaptive notch filter based phase-locked loop (DANF-PLL) utilizes the good filter capability of the adaptive notch filter to suppress the disturbance of the power grid and reduce the disturbance of harmonics on the output signal of the phase-locked loop. However, the adaptive notch filter has a weak ability to suppress DC offset. The DC offset will cause the phase and frequency obtained by the phase-locked loop to contain an AC component with the same frequency as the power frequency, and the amplitude of the AC component is related to the size of the DC component. Summary of the invention

[0004] In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a phase-locked loop based on a double improved adaptive notch filter, which has the characteristics of fast response speed and strong robustness.

[0005] The present invention is achieved through the following technical solutions:

[0006] A phase-locked loop based on a double improved adaptive notch filter is characterized by comprising a Clarke converter, an improved adaptive notch filter 1, an improved adaptive notch filter 2, a positive and negative sequence component calculation module (PNSC), a Park converter, a sliding average filter 1, a sliding average filter 2, an inverse tangent function converter, a proportional integral regulator (PI), an integral link, and a proportional link.

[0007] Grid voltage V abc After the Clarke converter, it is transformed into the two-phase stationary αβ coordinate system to obtain V α 、V β The first input terminal of the improved adaptive notch filter is connected to V α 、V β The output voltage at the output end is connected to the positive and negative sequence component calculation module to obtain the positive sequence voltage component V α + 、V β + The output of the Park converter is connected to the input of the positive and negative sequence component calculation module, V α + 、V β + Transform to the two-phase synchronous rotating coordinate system to obtain V d + 、V q + . V d + 、V q + After filtering out the harmonics through a sliding average filter, we get Using the amplitude normalization method, The deviation signal is obtained after calculation by the inverse tangent function converter. The input signal of the proportional integral regulator is the deviation signal, and the output signal is ff After adding, ω′ is obtained, and the ω′ signal is connected to the second input terminal of the improved adaptive notch filter to provide the improved adaptive notch filter with a grid angular frequency signal. The output signal of the proportional integral regulator is integrated by the integral link and connected to the Park converter to provide it with the grid phase signal required for conversion.

[0008] The beneficial effects of the present invention are as follows: the present invention is based on a phase-locked loop with dual improved adaptive notches, the improved adaptive notches and the positive and negative sequence component calculation module form a DIANF module, which acts as an outer-loop filtering link to suppress the DC offset and negative sequence component in the grid voltage; a sliding average filter is introduced as an inner-loop filtering link to suppress harmonic components, and a small MAF window length is set to enable the phase-locked loop to have a faster transient response. The phase-locked loop based on dual improved adaptive notches proposed in this paper has the advantages of good tracking effect and fast response speed, and is suitable for solar power generation, wind power and other new energy grid-connected systems and other places that need to obtain grid synchronization signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention is further described below with reference to the accompanying drawings and embodiments.

[0010] Figure 1 A schematic diagram of the structure of a phase-locked loop based on a double improved adaptive notch filter;

[0011] Figure 2 is a schematic diagram of the structure of the improved adaptive notch filter;

[0012] Figure 3 is a Bode diagram of the improved adaptive notch filter transfer function D′(s);

[0013] Figure 4 is a schematic diagram of the structure of the dual improved adaptive notch filter;

[0014] Figure 5 (a) is the amplitude-frequency response diagram of the sliding average filter;

[0015] Figure 5 (b) is the phase-frequency response diagram of the sliding average filter;

[0016] Figure 6 (a) is the grid voltage waveform when the grid voltage jumps by +40° phase;

[0017] Figure 6 (b) is the grid frequency detection waveform when the grid voltage jumps by +40° phase;

[0018] Figure 6 (c) is the grid phase detection waveform when the grid voltage jumps by +40°;

[0019] Figure 7 (a) is the grid voltage waveform when the grid voltage jumps to +3Hz frequency;

[0020] Figure 7 (b) is the grid frequency detection waveform when the grid voltage jumps to +3Hz frequency;

[0021] Figure 7 (c) is the grid phase detection waveform when the grid voltage jumps to +3Hz frequency;

[0022] Figure 8 (a) is the grid voltage waveform when a DC component is suddenly injected into the three-phase voltage of the grid;

[0023] Figure 8 (b) is the grid frequency detection waveform when the three-phase voltage of the grid is suddenly injected with a DC component;

[0024] Figure 8 (c) is the grid phase detection waveform when the three-phase voltage of the grid is suddenly injected with a DC component;

[0025] Fig. 9 (a) is the steady-state waveform of the grid voltage when a large amount of DC component is suddenly injected into the grid A phase voltage;

[0026] Fig. 9 (b) is the steady-state waveform diagram of the grid frequency detection when a large amount of DC component is suddenly injected into the grid A phase voltage;

[0027] Fig. 9 (c) is the steady-state waveform diagram of the grid phase detection when a large amount of DC component is suddenly injected into the grid A phase voltage;

[0028] Fig.10 (a) is the grid voltage waveform when the grid voltage is severely distorted;

[0029] Fig.10 (b) is the grid frequency detection waveform when the grid voltage is severely distorted;

[0030] Fig.10 (c) is the grid phase detection waveform when the grid voltage is severely distorted. DETAILED DESCRIPTION

[0031] The following is a further explanation of a phase-locked loop based on a dual improved adaptive notch filter according to the present invention with reference to the accompanying drawings.

[0032] The phase-locked loop mainly involves the improved adaptive notch filter link, the positive and negative sequence component calculation module, and the sliding average filter. The following is a detailed analysis of these three links.

[0033] The traditional adaptive notch filter can be described by a differential equation:

[0034]

[0035] In the formula, the input signal is u and the grid angular frequency signal ω′, ξ is a positive real number parameter, and the output signal is x and its derivative e represents the deviation of the input signal from the derivative of the output signal.

[0036]

[0037] Where D(s) and Q(s) are the output signals x and The frequency domain transfer function of ANF is: Let the resonant angular frequency ω′ of ANF be equal to the fundamental angular frequency ω of the power grid, and substitute s=jω into the above formula to obtain:

[0038]

[0039] From the above formula, we can see that the output signal x is always greater than The output signal x is lagging by 90°. In addition, the output signal The input signal u can be tracked without static error, and the output x has unit amplitude gain. Therefore, ANF can be used as an orthogonal signal generator to obtain accurate orthogonal components. Q(s) is a bandpass filter (BPF) with unity gain and no phase shift at the center frequency of 50Hz. Q(s) has a zero point at s=0, that is, there is a zero point at 0Hz, so Q(s) can filter out all DC components in the input signal u, so the output signal D(s) is a second-order low-pass filter (LPF). When the input signal u contains a DC component, the output x is easily affected by the DC voltage offset and produces an oscillation error, thereby affecting the locking of the grid synchronization signal.

[0040] Figure 2 It is a schematic diagram of the structure of the improved adaptive notch filter. Figure 2 In the αβ coordinate system, the voltage component V α (V β ) is the input grid voltage signal, ω′ is the resonant angular frequency of the notch filter. The output signal is V α ′(V β ′) and its orthogonal signal qV α ′(qV β ′), q is the 90° phase lag factor, e is the input signal V α (V β ) and the output signal V α ′(V β ′). If the input voltage V α (V β ) contains a DC component, and after the output signal V α ′(V β ′) After negative feedback, the deviation e contains the same α (V β ) with the same DC offset, the signal gain 2ξ is amplified and then subtracted from x′ to eliminate the output signal qV α ′(qVβ The DC component in ′). The improved adaptive notch filter transfer function is:

[0041]

[0042] Q'(s) is a bandpass filter (BPF) with unity gain and no phase shift at the center frequency of 50Hz. At the same time, Q'(s) has a zero point at s=0, that is, there is a zero point at 0Hz, so Q(s) can filter out all the DC components in the input signal u, so the output signal There is no DC component in it.

[0043] The Bode plot of the improved adaptive notch filter transfer function D′(s) is as follows: Figure 3 As shown, where ξ=0.707, f=50Hz. From equation (4), we can see that D′(s) has a zero point s=0, so the output signal V α ′(V β The DC component in ′ can be completely filtered out. Substituting s=jω into equation (4), we can get that the two output signals of the improved adaptive notch filter are orthogonal, so the improved adaptive notch filter can be used as an orthogonal signal generator.

[0044] The three-phase voltage in the unbalanced state of the power grid is transformed into the αβ stationary coordinate system. The positive sequence voltage component V α + 、V β + The relationship exists

[0045]

[0046] Wherein, q = exp(-jπ / 2), which represents the 90° phase lag factor.

[0047] Figure 4 The schematic diagram of the structure of the dual improved adaptive notch filter is shown in Figure 5. The positive and negative sequence component calculation module (PNSC) can be expressed by formula (5). The improved adaptive notch filter is used as an orthogonal signal generator, and the input signal is the three-phase voltage V abc The grid voltage V in the αβ coordinate system is obtained by Clarke transformer transformation α 、V β , the output signal is V α ′、V β ′ and the relative orthogonal signal qV α ′、qV β The input ends of the two improved adaptive notch filters are connected to the positive and negative sequence component calculation module, and the output signal is the positive sequence voltage component V α + 、Vβ + The dual improved adaptive notch filter can eliminate the DC offset and negative sequence components in the input voltage, but its ability to suppress high-order harmonics is insufficient.

[0048] The sliding average filter is a finite impulse response filter with a linear phase, and its output characteristics are similar to an ideal low-pass filter under certain circumstances. Assume that the input signal of the sliding average filter is r(t), the output signal is c(t), and the transfer function of the sliding average filter in the s domain is

[0049]

[0050] Where: T ω is the sliding average filter window length. Window length T ω It determines the filtering ability of the sliding average filter and the response speed of the system. The larger the window length, the stronger the filtering ability, but the longer the response time.

[0051] Although the three-phase grid voltage contains infinite harmonic components in theory, in practice, after Clarke transformation, the grid voltage V in the αβ coordinate system is α 、V β The main harmonic order is 6k±1, of which 6k+1 is the positive sequence component and 6k-1 is the negative sequence component. When transformed to the dq coordinate system, the 6k+1 harmonic positive sequence component is expressed as the 6k positive sequence harmonic, and the 6k-1 harmonic component is expressed as the 6k negative sequence harmonic.

[0052] Figure 5 is the amplitude-frequency response and phase-frequency response diagram of the sliding average filter, where T ω =T / 6=0.0033s. Figure 5 It can be seen that the sliding average filter can filter out ±3, ±6, ±9 and other harmonics, including the 6k harmonic.

[0053] In order to verify the superiority of the dual decoupling structure phase-locked loop, this embodiment simulates and analyzes the proposed dual improved adaptive notch filter based phase-locked loop (DIANF-PLL) in four situations: grid voltage phase jump, grid voltage frequency jump, grid voltage containing DC offset, and grid voltage severe distortion. It is compared with the dual adaptive notch filter based phase-locked loop (DANF-PLL) and the sliding average filter based phase-locked loop (MAF-PLL). The relevant simulation waveforms are shown in Figure 2. Figure 6 to Figure 10 The normal operation condition of the grid voltage is selected as follows: the three-phase voltage amplitude is normalized V abc =1p.u., grid voltage frequency f = 50Hz. The control parameters of the three phase-locked loops are shown in Table 1. p , ki are the proportional gain and integral gain of the PI controller respectively.

[0054] Table 1 Phase-locked loop control parameters

[0055]

[0056] (1) Grid voltage phase jump simulation

[0057] The power grid system operates normally from 0 to 1s, and the grid voltage phase jumps by +40° at t=1s. Figure 6 The simulation results are shown for a +40° phase jump in the grid voltage. At the moment of the phase mutation at t=1s, the phase errors of the three phase-locked loops all reached a maximum value of 40°, which is the same as the magnitude of the grid phase jump. At the same time, the frequency is increased to eliminate the phase deviation. Figure 6 It can be seen that the DIANF-PLL proposed in the present invention shows a high response speed. It takes 29ms, about 1.5 grid base frequency cycles, to reach zero steady-state error after phase mutation. In contrast, DANF-PLL and MAF-PLL have slow response speeds. The DANF-PLL 2% adjustment time is 47ms, about 2.5 base frequency cycles, while the MAF-based phase-locked loop has not been adjusted within 4 base frequency cycles, and the adjustment speed is the slowest. In terms of overshoot, the DIANF-PLL overshoot is slightly larger than that of MAF-PLL, but smaller than that of DANF-PLL.

[0058] (2) Grid voltage and frequency jump simulation

[0059] The power grid system operates normally from 0 to 1s, and the power grid voltage undergoes a +3Hz frequency step at t=1s. The simulation results are as follows: Figure 7 As shown. Figure 7 It can be seen that DIANF-PLL can quickly and stably track the frequency and phase of the grid voltage. The time for DIANF-PLL to reach steady state is 41ms, and it takes about 2 grid fundamental frequency cycles to reach zero error steady state; DANF-PLL has a medium response speed, and it takes about 2.5 fundamental frequency cycles to reach steady state; MAF-PLL has a very slow response speed, and it takes about 7.3 fundamental frequency cycles to reach steady state. Comparing the overshoot, the overshoot of DIANF-PLL is smaller than that of DANF-PLL and MAF-PLL. Under the condition of frequency mutation, the phase-locked loop disclosed in the present invention has better dynamics and stability.

[0060] (3) Grid voltage including DC offset simulation

[0061] The power grid system operates normally from 0 to 1s. At t = 1s, 0.1pu DC component is injected into phase A, -0.1pu is injected into phase B, and 0.2pu DC offset is injected into phase C. The simulation results are as follows: Figure 8 As shown. DANF-PLL is seriously affected by DC offset, and its frequency and phase still oscillate at one times the power frequency in steady state; MAF-PLL has the ability to suppress DC offset, but the response time becomes longer due to the long window length; the DIANF-PLL proposed in this article can completely eliminate DC offset, with the shortest adjustment time, reaching steady state within about 1.5 grid cycles. The power grid system operates normally at 0 to 1s. At t = 1s, a large amount of DC offset (0.5pu) is suddenly injected into phase A of the power grid, and the frequency jumps to 45Hz to verify the DC offset suppression capabilities of the two phase-locked loops at non-nominal frequencies. Fig. 9 The steady-state simulation results are shown in Figure 2. When the DC offset is too large, the MAF-PLL cannot completely suppress it, and the frequency and phase will oscillate periodically. The DIANF-PLL can also achieve zero-error frequency and phase tracking in the case of a large amount of DC offset and phase offset.

[0062] (4) Simulation of severe grid voltage distortion

[0063] A DC offset is injected into the three-phase grid voltage, with 0.1pu DC component injected into phase A, -0.1pu injected into phase B, and 0.2pu injected into phase C. At the same time, the main harmonic voltage components are mixed in, including 5% fundamental voltage negative sequence component, 6% 5th harmonic negative sequence component, and 5% 7th harmonic positive sequence component, making the total harmonic distortion rate (THD) of the grid reach 8.22%, which is much greater than the worst case specified by the national standard. In the case of severe grid distortion, the grid frequency jumps to +3Hz. The simulation results of severe grid voltage distortion are shown in the figure. Fig.10 As shown. DANF-PLL can eliminate high-order harmonics, but does not have the ability to suppress DC offset, and the frequency and phase produce periodic oscillations. The PLL proposed in the present invention can suppress both DC components and harmonic components, can quickly and accurately track phase and frequency under harsh working conditions, and the adjustment time is much shorter than MAF-PLL.

[0064] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A phase-locked loop based on a double improved adaptive notch filter, characterized in that: The phase-locked loop includes a Clarke converter, an outer-loop filter structure, a Park converter, an inner-loop filter structure, an inverse tangent function converter, a proportional-integral regulator PI, a first adder and a first integral link connected in series in sequence; The output end of the first adder is also connected to the Park converter and the out-of-loop filter structure; The out-of-loop filtering structure includes an improved adaptive notch filter 1, an improved adaptive notch filter 2 and a positive and negative sequence component calculation module PNSC; Grid voltage V abc After the Clarke transformer is used to transform, the voltage component V in the αβ coordinate system is obtained. α 、V β The two output ends of the Clarke converter are respectively connected to the first input ends of the improved adaptive notch filter 1 and the improved adaptive notch filter 2, and the voltage component V α 、V β The improved adaptive notch filter 1 and the improved adaptive notch filter 2 are respectively input, and the improved adaptive notch filter 1 outputs a signal V α ′ and the orthogonal signal qV α ', the improved adaptive notch filter output signal V β ′ and the orthogonal signal qV β ′, the output ends of the improved adaptive notch filter 1 and the improved adaptive notch filter 2 are both connected to the positive and negative sequence component calculation module PNSC, and V α ′ and qV α ′、V β ′ and qV β ' Input the positive and negative sequence component calculation module PNSC, the output end of the positive and negative sequence component calculation module PNSC outputs the positive sequence voltage component V α + 、V β + The two output ends of the positive and negative sequence component calculation module PNSC are connected to the Park converter to convert the positive sequence voltage component V α + 、V β + The Park converter is used to transform the voltage positive sequence component V in the dq coordinate system. d + 、V q + ; The in-loop filtering structure includes a sliding average filter 1 and a sliding average filter 2. The two output ends of the Park converter are respectively connected to the sliding average filter 1 and the sliding average filter 2. d + 、V q + After filtering out the harmonics using a sliding average filter, the voltage positive sequence component in the dq coordinate system is obtained after filtering. The output ends of the sliding average filter 1 and the sliding average filter 2 are both connected to the inverse tangent function converter, and the voltage positive sequence component Divide by After the amplitude is normalized, the phase deviation signal Δθ is input into the inverse tangent function converter, and the phase deviation signal Δθ is output. The phase deviation signal Δθ is input into the proportional integral regulator PI to obtain an output signal Δω. The output signal Δω of the proportional integral regulator PI is input into the first adder and the nominal angular frequency ω. ff After addition, the grid angular frequency signal ω′ is obtained. The output end of the first adder is also connected to the Park converter, and the grid angular frequency signal ω′ is input into the Park converter; the grid angular frequency signal ω′ is input into the first integral link, and after integration, the grid phase signal is output.

2. A phase-locked loop based on a double improved adaptive notch filter as claimed in claim 1, characterized in that: The second input terminals of the improved adaptive notch filter 1 and the improved adaptive notch filter 2 are connected to the output terminal of the first adder to provide the grid angular frequency signal ω′ for the improved adaptive notch filter 1 and the improved adaptive notch filter 2.

3. A phase-locked loop based on a double improved adaptive notch filter as claimed in claim 1, characterized in that: The improved adaptive notch filter 1 and the improved adaptive notch filter 2 both include a first adder-subtractor, a 2ξ proportional link, a first multiplier, a second adder-subtractor, and a second integral link connected in series in sequence, the output end of the second integral link is also connected to the first adder-subtractor and the third integral link, the third integral link is sequentially connected in series with a second multiplier, a third multiplier, and the second adder-subtractor, the output end of the second multiplier is also connected to the third adder-subtractor, the input end of the third adder-subtractor is also connected to the output end of the 2ξ proportional link, the input end of the third multiplier is also connected to the grid angular frequency signal ω′, and the grid angular frequency signal ω′ is also input to the first multiplier and the second multiplier; Voltage component V in αβ coordinate system α and signal V α ′、V β and signal V β ′ is obtained by subtracting the error signal e, which is multiplied by the grid angular frequency signal ω′ after passing through the 2ξ proportional link. The obtained signal is subtracted from the product of the signal x′ and the grid angular frequency signal ω′ and then passed through the integral link to obtain the orthogonal signal qV α ′ and qV β The derivative of ′ is the signal V α ′ and V β ′, after passing through the integral link, it is multiplied by the grid angular frequency signal ω′ to obtain the signal x′, and the signal x′ is subtracted from the deviation signal e after the 2ξ proportional link gain to obtain the orthogonal signal qV α ′ and qV β ′.

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