Chip, chip preparation method and solid-state nanopore microarray device

Abstract

The application discloses a chip, a chip preparation method and a solid-state nanopore microarray device. The chip preparation method comprises the following steps: S1, selecting and cleaning an SOI silicon wafer; S2, manufacturing mask layers on two surfaces of the SOI silicon wafer; S3, etching at least two track lines on the mask layers to expose silicon layers of the SOI silicon wafer, the track lines on the same mask layer are parallel, and the track lines on different mask layers intersect at a preset angle; S4, etching the exposed silicon layers on the two surfaces of the SOI silicon wafer respectively, and forming V-shaped grooves along the track lines to expose buried oxygen layers of the SOI; S5, etching the buried oxygen layers on the two surfaces of the SOI silicon wafer respectively to form nanopores at the intersection of the V-shaped grooves of the silicon layers on the two surfaces; and S6, slicing to form the chip. The application avoids the punching step of TEM / HIM, and reduces the cost. Moreover, the chip has multiple nanopores in an array, a plurality of test tasks can be completed at a time, and the test efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of gene detection, more particularly to a chip, a chip preparation method and a solid nanopore microarray device. BACKGROUND

[0002] In the process of hybridization DNA test, when the DNA with probe passes through the hole, the difference of different base physicochemical properties and the different current blocking effects of the hole are analyzed, and the sequence information of the base in the DNA molecule can be obtained by distinguishing the blocking current, so as to achieve the purpose of testing the DNA sequence.

[0003] At present, the chip is a single-hole chip, which can only test one DNA sequence at a time. According to the hybridization principle, only one type of base or base sequence can be detected. If the entire DNA test is to be completed, the corresponding number of DNA tests need to be performed according to the calculation results of the hybridization theory. One hole can only test one type of base at a time, which greatly reduces the test efficiency.

[0004] In addition, the preparation of a single-hole chip requires a complex process of photolithography, etching, corrosion, slicing, TEM punching, and high cost.

[0005] In summary, how to improve the DNA test efficiency and reduce the chip preparation cost is a problem to be solved by the technical personnel in the field. SUMMARY

[0006] Therefore, the first object of the present application is to provide a chip preparation method, which can improve the DNA test efficiency and reduce the chip preparation cost.

[0007] The second object of the present application is to provide a chip.

[0008] The third object of the present application is to provide a solid nanopore microarray device.

[0009] In order to achieve the above-mentioned first object, the present application provides the following technical scheme:

[0010] A chip preparation method comprises the following steps:

[0011] Step S1: selecting and cleaning an SOI silicon wafer;

[0012] Step S2: making a mask layer on both sides of the SOI silicon wafer;

[0013] Step S3: etching at least two track lines on the mask layers on both sides of the SOI silicon wafer to expose the silicon layer of the SOI silicon wafer, the track lines on the same mask layer are parallel, and the track lines on different mask layers intersect at a preset angle;

[0014] Step S4: etching the silicon layer exposed on both sides of the SOI silicon wafer respectively, and forming V-shaped grooves along the track lines to expose the buried oxygen layer of the SOI;

[0015] Step S5: etching the buried oxygen layer from both sides of the SOI silicon wafer respectively to form a nanopore at the intersection of the V-shaped grooves of the silicon layer on both sides;

[0016] Step S6: slicing to form a chip.

[0017] In another specific embodiment, the step S3 specifically comprises:

[0018] Step S31: forming a photoresist layer on both sides of the silicon wafer respectively through uniform coating, photoresist development, and obtaining preset lines;

[0019] Step S32: etching the mask layer exposed by the preset lines using a plasma etching machine or a metal dry etching machine to form the track lines and expose the silicon layer;

[0020] Step S33: removing the photoresist layer.

[0021] In another specific embodiment, in the step S33, the photoresist layer is removed by heating with acetone.

[0022] In another specific embodiment, in the step S4, the silicon layer on both sides of the SOI silicon wafer is etched by alkali solution using a single-side etching clamp.

[0023] In another specific embodiment, in the step S1, cleaning the SOI silicon wafer comprises cleaning the SOI silicon wafer with deionized water, acetone, alcohol, and deionized water respectively;

[0024] The step S2 specifically comprises depositing a silicon nitride film, a silicon oxide film, or a metal film on both sides of the SOI silicon wafer simultaneously using LPCVD, PECVD, or magnetron sputtering metal to form the mask layer;

[0025] In the step S5, the buried oxygen layer is etched using a BOE solution.

[0026] In another specific embodiment, between the step S5 and the step S6, there is further a step S7 of judging whether the size of the nanopore is greater than a preset size, if yes, turning to a step S8, and if no, turning to the step S6;

[0027] Step S8: reducing the nanopore to a preset size.

[0028] In another specific embodiment, in the step S8, the nanopore is irradiated with high-energy laser to expand the surface tension of the buried oxygen layer so as to reduce the nanopore to a preset size, and then turning to the step S6;

[0029] or

[0030] In the step S8, liquid curable polyimide is coated on the surface of the V-shaped groove, and sodium chloride coated with gold particles is placed near the nanopore, the sodium chloride crystals are slowly pressed against each other, so as to squeeze out the polymer extending into the nanopore, the polyimide is cured by ultraviolet light or heating, and then the sodium chloride is washed away, so as to obtain the nanopore reduced to the preset size, and the step S6 is turned to.

[0031] In another specific embodiment, the preset size is greater than or equal to 1 nm and less than or equal to 100 nm, and the number of the nanopores is greater than or equal to 2 and less than or equal to 40000;

[0032] The width of the buried oxide layer exposed by the V-shaped groove is greater than or equal to 1 nm and less than or equal to 100 nm;

[0033] The preset angle is 90°;

[0034] The metal film in the step S2 is an Al film, a Ni film, a Cu film, a Ti film or an Au film;

[0035] The alkali solution is a KOH solution or a TMAH solution.

[0036] The various embodiments according to the present application can be combined as needed, and the combinations of these embodiments are also within the scope of the present application and are part of the specific embodiments of the present application.

[0037] According to the above technical solution, the chip preparation method provided by the present application can be used to make mask layers on both sides of the SOI silicon wafer, and etch the preset track lines on the mask layers, so as to facilitate the subsequent obtaining of the V-shaped groove at the required position, and facilitate the accurate control of the distance between the nanopores. The buried oxide layer exposed by the V-shaped groove on both sides of the SOI silicon wafer is etched, and the nanopores are formed by etching through the buried oxide layer at the V-shaped groove on both sides of the SOI silicon wafer, so as to avoid the step of TEM / HIM punching, simplify the chip preparation steps, and reduce the cost. In addition, the chip prepared by the present application has an array with multiple nanopores, and the same microfluidic channel and patch clamp equipment can complete the test task that can be completed several times by a single-hole chip at one time, greatly improving the test efficiency and test throughput.

[0038] In order to achieve the above-mentioned second object, the present application provides the following technical solution:

[0039] A chip prepared by the chip preparation method according to any one of the above embodiments.

[0040] Since the chip disclosed by the application is prepared by using the chip preparation device, the array on the chip has a plurality of nanopores, the same microfluidic channel and patch clamp device can complete the test task that can be completed by a single-hole chip for several times, and the test efficiency and test throughput are greatly improved.

[0041] In order to achieve the third purpose, the application provides the following technical solutions.

[0042] A solid nanopore microarray device comprises a first microfluidic component, a second microfluidic component, a third microfluidic component, and the chip.

[0043] The first microfluidic component seals the bottom surface of the chip, the second microfluidic component seals the circumference of the chip, and the third microfluidic component seals the top surface of the chip.

[0044] A first preset first groove connecting port is formed on the first microfluidic component, and the first groove connecting port is in one-to-one correspondence with the V-shaped groove on the bottom surface silicon layer.

[0045] A second preset second groove connecting port is formed on the second microfluidic component, and the second groove connecting port is in one-to-one correspondence with the V-shaped groove on the top surface silicon layer.

[0046] According to the above technical solutions, the solid nanopore microarray device provided by the application has the following advantages: since each nanopore corresponds to one first groove connecting port and one second groove connecting port, the nanopore current data of the chip can be addressed and controlled. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0048] Fig. 1 The structure diagram of the SOI silicon wafer after etching by potassium hydroxide solution to form a V-shaped groove is provided for the application.

[0049] Fig. 2 The local structure diagram of the SOI silicon wafer after etching by BOE to form a nanopore is provided for the application.

[0050] Fig. 3 The structure diagram of the solid nanopore microarray device is provided for the application.

[0051] In Figs. 1-3In the description of the present application, it should be understood that the terms "upper", "lower", "top surface", "bottom surface" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the position or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0052] Buried oxygen layer 1, top surface silicon layer 2, bottom surface silicon layer 3, V-shaped groove 4, nanopore 5, first microfluidic component 6, second microfluidic component 7, third microfluidic component 8, first trench connection port 9, second trench connection port 10. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings of the embodiments of the present application. Figs. 1-3 The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings of the embodiments of the present application.

[0054] In the description of the present application, it should be understood that the terms "upper", "lower", "top surface", "bottom surface" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the position or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0055] The first aspect of the present application provides a chip preparation method, comprising the following steps:

[0056] Step S1: selecting and cleaning SOI silicon wafer.

[0057] Specifically, the SOI silicon wafer includes a buried oxygen layer 1 and two silicon layers, which are respectively arranged on the top surface and bottom surface of the buried oxygen layer 1. In order to distinguish the two silicon layers, the silicon layer arranged on the top surface of the buried oxygen layer 1 is named as the top surface silicon layer 2, and the silicon layer arranged on the bottom surface of the buried oxygen layer 1 is named as the bottom surface silicon layer 3.

[0058] Cleaning the SOI silicon wafer includes cleaning the SOI silicon wafer with deionized water, acetone, alcohol and deionized water respectively, and irradiating with light to remove dust particles on the surface of the SOI silicon wafer.

[0059] Step S2: making a mask layer on both sides of the SOI silicon wafer.

[0060] Specifically, the mask layer is made of a mask material that can be used as a subsequent etching process. In this embodiment, the mask layer is taken as a silicon nitride film as an example.

[0061] Step S3: etching at least two track lines on the mask layer on both sides of the SOI silicon wafer to expose the silicon layer of the SOI silicon wafer, the track lines on the same mask layer are parallel, and the track lines on different mask layers intersect at a preset angle.

[0062] Specifically, at least two track lines are etched on the mask layer on the top surface silicon layer 2 and the mask layer on the bottom surface silicon layer 3 respectively, and the width of the track line can be set according to the needs.

[0063] The setting of the track line can facilitate the accurate control of the position of the nanopore 5 subsequently.

[0064] Step S4: The silicon layers exposed on both sides of the SOI silicon wafer are etched respectively, and a V-shaped groove 4 is formed along the track line to expose the buried oxygen layer 1 of the SOI.

[0065] Specifically, the top surface silicon layer 2 and the bottom surface silicon layer 3 exposed at the bottom end of the track line are etched, and a V-shaped groove 4 with an inverted pyramid structure is formed due to the anisotropy of the etching rate along different crystal axes.

[0066] Step S5: The buried oxygen layer 1 on both sides of the SOI silicon wafer is etched respectively to form a nanopore 5 at the intersection of the V-shaped grooves 4 on both sides of the silicon layer.

[0067] It should be noted that the buried oxygen layer 1 can also be etched by plasma to obtain the same nanopore 5.

[0068] Specifically, taking the perpendicular of the V-shaped groove 4 on the top surface silicon layer 2 and the V-shaped groove 4 on the bottom surface silicon layer 3 as an example. The nanopores 5 are distributed in two directions X and Y in a two-dimensional plane, and the nanopores 5 can be distributed according to an arithmetic progression, can be distributed according to a geometric progression, or can be distributed according to different dimensions of arithmetic progression and geometric progression.

[0069] Step S6: Slicing to form a chip.

[0070] The chip preparation method provided by the application can facilitate the subsequent formation of the V-shaped groove 4 at the required position by making a mask layer on both sides of the SOI silicon wafer and etching a preset track line on the mask layer, so as to facilitate the accurate control of the distance between the nanopores 5. The buried oxygen layer 1 exposed by the V-shaped groove 4 on both sides of the SOI silicon wafer is etched respectively, and the nanopore 5 is formed by etching through the buried oxygen layer 1 at the V-shaped groove 4 on both sides of the SOI silicon wafer, which avoids the step of TEM / HIM punching, simplifies the chip preparation step, and reduces the cost. In addition, the chip prepared by the application has multiple nanopores 5 in the array, and the same microfluidic channel and patch clamp equipment can complete the test task that can be completed several times by a single-hole chip at one time, which greatly improves the test efficiency and improves the test throughput.

[0071] In some embodiments, step S3 specifically comprises:

[0072] Step S31: The silicon wafer is uniformly coated on both sides to form a photoresist layer, and the photoresist is developed to obtain a preset line.

[0073] Specifically, a spin coater is used to uniformly spin the photoresist on the mask layer of the top silicon layer 2 and the mask layer of the bottom silicon layer 3, and then the photoresist is baked, exposed, developed, and inspected by a microscope to determine whether the development is sufficient. Then, the photoresist is baked again to obtain the preset line.

[0074] Step S32: A plasma etching machine or a metal dry etching machine is used to etch the exposed mask layer of the preset line to form a track line and expose the silicon layer.

[0075] The mask layer is etched by the plasma etching machine mainly to etch the mask layer that is not covered by the photoresist to expose the top silicon layer 2 and the bottom silicon layer 3.

[0076] Step S33: The photoresist layer is removed.

[0077] Specifically, the photoresist is removed by heating with acetone.

[0078] In some embodiments, in step S4, a single-side etching clamp is used to etch the silicon layers on both sides of the SOI silicon wafer by an alkali solution.

[0079] Specifically, the alkali solution is a KOH solution or a TMAH solution.

[0080] When the SOI silicon wafer is exposed to the KOH solution, a V-shaped groove 4 in the shape of an inverted pyramid is formed due to the anisotropy of the etching rate along different crystal axes. Because the thickness of the top silicon layer 2 and the bottom silicon layer 3 of the SOI silicon wafer is significantly different, the top silicon layer 2 needs to be etched separately to avoid over-etching. The width of the exposed buried oxide layer 1 after etching the top silicon layer 2 and the bottom silicon layer 3 is controlled to be in the range of 2mm-100nm, and the width of the exposed buried oxide layer 1 determines the size of the nanopore 5.

[0081] In addition, the KOH solution does not etch the silicon dioxide of the buried oxide layer 1, which can well self-terminate the etching of the silicon and easily control the size of the nanopore 5.

[0082] In some embodiments, step S2 specifically includes depositing a silicon nitride film, a silicon oxide film, or a metal film on both sides of the SOI silicon wafer by using LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), or magnetron sputtering to form the mask layer.

[0083] Specifically, the metal film is an Al film, a Ni film, a Cu film, a Ti film, or an Au film, etc.

[0084] In some embodiments, in step S5, the buried oxide layer 1 is etched by using a BOE solution.

[0085] Since the BOE solution and the silicon layer do not react, the buried oxygen layer 1 is vertically etched, the buried oxygen layer 1 is simultaneously etched from the two silicon layers, and a nanopore 5 is formed when the two silicon layers intersect.

[0086] In some embodiments, between the step S5 and the step S6, there is further a step S7 of judging whether the size of the nanopore 5 is greater than a preset size, if yes, the step S8 is performed, and if no, the step S6 is performed.

[0087] Specifically, the preset size is greater than or equal to 1 nm and less than or equal to 100 nm. It should be noted that the preset size can also be set as required.

[0088] The step S8 is to reduce the nanopore 5 to the preset size.

[0089] Specifically, the method of reducing the nanopore 5 to the preset size can be that a high-energy laser is used to irradiate the nanopore 5, so that the surface tension of the buried oxygen layer 1 is expanded to reduce the nanopore 5 to the preset size. The method of reducing the nanopore 5 to the preset size can also be other methods, for example, liquid solidifiable polyimide is coated on the surface of the V-shaped groove 4, and sodium chloride coated with gold particles is placed near the nanopore 5, the sodium chloride crystals slowly extrude each other, so as to squeeze out the polymer extending into the nanopore 5, the polyimide is solidified by ultraviolet light or heating, and then the sodium chloride is washed away, so as to obtain the nanopore 5 reduced to the preset size.

[0090] Specifically, the number of the nanopores 5 is greater than or equal to 2 and less than or equal to 40,000.

[0091] The width of the buried oxygen layer 1 exposed by the V-shaped groove 4 is greater than or equal to 1 nm and less than or equal to 100 nm.

[0092] Further, the preset angle is 90°, so as to realize that the V-shaped groove 4 on the top surface silicon layer 2 and the V-shaped groove 4 on the bottom surface silicon layer 3 are perpendicular, and then the nanopore 5 is vertical. It should be noted that the preset angle can also be slightly less than or slightly greater than 90°.

[0093] As shown in FIG. 2, the second aspect of the present application provides a chip prepared by the chip preparation method in any one of the above embodiments. Figs. 1-2

[0094] The chip includes an SOI silicon wafer and a mask layer.

[0095] The SOI silicon wafer includes a buried oxygen layer 1, a top surface silicon layer 2 and a bottom surface silicon layer 3, and the top surface silicon layer 2 and the bottom surface silicon layer 3 are respectively arranged on the top surface of the buried oxygen layer 1 and the bottom surface of the buried oxygen layer 1.

[0096] ​Specifically, the SOI silicon wafer is cleaned, and the SOI silicon wafer can be cleaned by deionized water, acetone, alcohol and deionized water respectively, and irradiated by light to remove dust particles on the surface of the SOI silicon wafer.

[0097] The mask layers are deposited on the top surface silicon layer 2 and the bottom surface silicon layer 3 respectively. Specifically, the mask layer is made of a mask material that can be used as a mask for subsequent etching process. In this embodiment, the mask layer is taken as a silicon nitride film as an example.

[0098] The track lines exposing the top surface silicon layer 2 and the bottom surface silicon layer 3 are etched on the mask layer respectively, and the number of track lines on each mask layer is at least two. The track lines on the same mask layer are parallel, and the track lines on different mask layers intersect at a preset angle.

[0099] It should be noted that the width of the track line can be set as needed.

[0100] Along the track lines, the V-shaped grooves 4 exposing the buried oxygen layer 1 are etched on the top surface silicon layer 2 and the bottom surface silicon layer 3 respectively, the V-shaped grooves 4 on the top surface silicon layer 2 are arranged in parallel, the V-shaped grooves 4 on the bottom surface silicon layer 3 are arranged in parallel, and the V-shaped grooves 4 of the top surface silicon layer 2 and the V-shaped grooves 4 of the bottom surface silicon layer 3 are arranged at a preset angle.

[0101] The nano-pores 5 are etched on the buried oxygen layer 1 at the intersection of the V-shaped grooves 4 of the top surface silicon layer 2 and the bottom surface silicon layer 3.

[0102] It should be noted that the buried oxygen layer 1 can also be etched by plasma to obtain the same nano-pores 5.

[0103] Specifically, taking the vertical of the V-shaped grooves 4 on the top surface silicon layer 2 and the V-shaped grooves 4 on the bottom surface silicon layer 3 as an example. The nano-pores 5 are distributed in two directions X and Y in the two-dimensional plane, and the nano-pores 5 can be distributed according to an arithmetic progression, an equal ratio progression, or both according to different dimensions.

[0104] The chip provided by the application has the advantages that the mask layers are made on the top surface silicon layer 2 and the bottom surface silicon layer 3 of the SOI silicon wafer respectively, the preset track lines are etched on the mask layers, and the V-shaped grooves 4 are etched along the track lines. The arrangement of the V-shaped grooves 4 can be controlled, and the positions of the nano-pores 5 can be accurately controlled. The nano-pores 5 on the chip are formed by etching the buried oxygen layer 1 at the intersection of the V-shaped grooves 4 of the top surface silicon layer 2 and the V-shaped grooves 4 of the bottom surface silicon layer 3, avoiding the step of TEM / HIM punching, simplifying the chip preparation steps and reducing the cost. In addition, there are multiple nano-pores 5 on the chip, and the same microfluidic channel and patch clamp equipment can complete the test task that can be completed several times by a single-hole chip at one time, greatly improving the test efficiency and test throughput.

[0105] In some embodiments, the mask layer is formed by depositing a silicon nitride film, a silicon oxide film or a metal film on the top silicon layer 2 and the bottom silicon layer 3 simultaneously by LPCVD or PECVD.

[0106] It should be noted that the metal film is an Al film, a Ni film, a Cu film, a Ti film or an Au film, etc.

[0107] In some embodiments, the track line is formed by etching along the preset line, which is formed by baking, exposing and developing a photoresist layer coated on the mask layer.

[0108] Specifically, the photoresist is uniformly coated on the mask layer of the top silicon layer 2 and the mask layer of the bottom silicon layer 3 by using a spin coater, and then the photoresist is baked, exposed, developed and inspected by a microscope to determine whether the development is sufficient, and then the photoresist is baked again to obtain the preset line.

[0109] Further, the track line is formed by etching through a plasma etching machine or a metal dry etching machine. The mask layer is etched by using the plasma etching machine mainly to etch the mask layer not covered by the photoresist, so as to expose the top silicon layer 2 and the bottom silicon layer 3.

[0110] In some embodiments, the V-shaped groove 4 is formed by etching after removing the photoresist layer. Specifically, the photoresist is removed by heating acetone.

[0111] Further, the V-shaped groove 4 is formed by immersing the top silicon layer 2 and the bottom silicon layer 3 into KOH solution or TMAH solution respectively through a single-side etching clamp.

[0112] When the SOI silicon wafer is exposed to the KOH solution, a V-shaped groove 4 in the shape of an inverted pyramid is formed due to the anisotropy of the etching rate along different crystal axes. Because the thickness difference between the top silicon layer 2 and the bottom silicon layer 3 of the SOI silicon wafer is large, the top silicon layer 2 is etched separately to avoid over-etching, and the width of the exposed buried oxide layer 1 after etching the top silicon layer 2 and the bottom silicon layer 3 is strictly controlled to be in the range of 1 mm-100 nm, and the width of the exposed buried oxide layer 1 determines the size of the nanometer hole 5.

[0113] In some embodiments, further, the application discloses etching the buried oxide layer 1 by using a BOE solution.

[0114] Because the BOE solution does not react with the silicon layer, it will etch the buried oxide layer 1 longitudinally, and when the two silicon layers etch the buried oxide layer 1 at the same time, a nanometer hole 5 is formed when they meet.

[0115] In some embodiments, the preset angle is 90°, so as to achieve the verticality of the V-shaped groove 4 on the top silicon layer 2 and the V-shaped groove 4 on the bottom silicon layer 3, and thus the vertical nanometer hole 5. Specifically, the preset angle is greater than or equal to 85° and less than or equal to 95°. It should be noted that the preset angle can also be set to other values slightly less than or slightly greater than 90°.

[0116] The diameter of the nanometer hole 5 is greater than or equal to 1 nm and less than or equal to 100 nm. It should be noted that the preset size can also be set as needed.

[0117] The number of nanometer holes 5 is greater than or equal to 2 and less than or equal to 40,000.

[0118] Since the on-chip array disclosed in the present application has multiple nanometer holes 5, the same microfluidic channel and patch clamp device can complete the test task that can be completed several times by a single-hole chip at one time, greatly improving the test efficiency and improving the test throughput.

[0119] As shown in Fig. 3 The third aspect of the present application provides a solid-state nanopore microarray device, which comprises a first microfluidic component 6, a second microfluidic component 7, a third microfluidic component 8, and a chip as in any one of the above embodiments.

[0120] The first microfluidic component 6 seals the bottom surface of the chip, the second microfluidic component 7 seals the circumference of the chip, and the third microfluidic component 8 seals the top surface of the chip. That is, the first microfluidic component 6, the second microfluidic component 7, and the third microfluidic component 8 realize the complete sealing of the chip.

[0121] The first microfluidic component 6 is provided with a first preset number of first groove connection ports 9, and the first groove connection ports 9 are one-to-one correspondingly and in conduction with the V-shaped grooves 4 on the bottom silicon layer 3.

[0122] The third microfluidic component 8 is provided with a second preset number of second groove connection ports 10, and the second groove connection ports 10 are one-to-one correspondingly and in conduction with the V-shaped grooves 4 on the top silicon layer 2.

[0123] The solid-state nanopore microarray device provided by the present application has one first groove connection port 9 and one second groove connection port 10 corresponding to each nanometer hole 5, so that the nanometer hole 5 current data of the chip can be addressed and controlled.

[0124] In the process of preparing the chip, the distribution of the solid nanopore 5 is arranged in an array manner, the number of the nanopores 5 of a single chip is increased, the microfluidic channel is connected with the membrane clamp, and the addressable test of all the nanopores 5 is realized. In this way, when the microarray chip is used to test the DNA, the electric signals of several DNA nanopores can be obtained at the same time, and the problem of low test efficiency of a single nanopore is solved. Meanwhile, the nanopore 5 can be obtained by using BOE etching or plasma etching, so that the production cost of the nanopore 5 is greatly reduced.

[0125] In some embodiments, the first microfluidic component 6 is provided with the first microfluidic channel by microfluidic technology, and the first microfluidic channel leads the first groove connecting port 9 and the V-shaped groove 4 on the bottom silicon layer 3.

[0126] Further, the third microfluidic component 8 is provided with the second microfluidic channel by microfluidic technology, and the second microfluidic channel leads the second groove connecting port 10 and the V-shaped groove 4 on the top silicon layer 2.

[0127] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0128] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0129] In the description of the specification, the description of the terms "one embodiment", "example", "specific example" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0130] The preferred embodiments of the application disclosed above are only to facilitate the elucidation of the application. The preferred embodiments do not describe all the details of the application and limit the application to the specific embodiments described. Obviously, many modifications and variations can be made in light of the teachings above. The description is chosen and described in order to best explain the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application and get the best results from the application. The application is only limited by the claims and their full scope and equivalents.

Claims

1. A method of preparing a chip, characterized by, The application relates to a method for manufacturing a nano-pore chip. The method comprises the following steps: S1: selecting and cleaning an SOI silicon wafer; S2: manufacturing mask layers on two surfaces of the SOI silicon wafer respectively; S3: etching at least two track lines on the mask layers on the two surfaces of the SOI silicon wafer respectively to expose the silicon layer of the SOI silicon wafer, the track lines on the same mask layer are parallel, and the track lines on different mask layers intersect at a preset angle; S4: etching the exposed silicon layer on the two surfaces of the SOI silicon wafer respectively and forming V-shaped grooves along the track lines to expose the buried oxygen layer of the SOI; S5: etching the buried oxygen layer on the two surfaces of the SOI silicon wafer respectively to form nano-pores at the intersection of the V-shaped grooves of the silicon layer on the two surfaces; S6: slicing to form a chip; The method further comprises the following step S7 between the step S5 and the step S6: judging whether the size of the nano-pore is greater than a preset size, if yes, turning to the step S8, and if no, turning to the step S6; 2. The method of claim 1, wherein S8: reducing the nano-pore to the preset size. The step S3 specifically comprises the following steps: S31: uniformly coating photoresist layers on the two surfaces of the silicon wafer respectively, photoresist developing, and obtaining preset lines; S32: using a plasma etching machine or a metal dry etching machine to etch the mask layers exposed by the preset lines to form the track lines and expose the silicon layer; 3. The method of claim 2, wherein the chip preparation method is characterized by, S33: removing the photoresist layers.

4. The method of claim 1, wherein In the step S33, acetone is used for heating to remove the photoresist layers.

5. The method of claim 4, wherein the chip preparation method is characterized by, In the step S4, a single-side etching clamp is used to etch the silicon layer on the two surfaces of the SOI silicon wafer by using an alkali solution respectively. In the step S1, the cleaning of the SOI silicon wafer comprises cleaning the SOI silicon wafer by using deionized water, acetone, alcohol and deionized water respectively; In the step S2, the mask layers are formed by simultaneously depositing silicon nitride films, silicon oxide films or metal films on the two surfaces of the SOI silicon wafer by using LPCVD, PECVD or magnetron sputtering metal; 6. The method of claim 5, wherein the chip preparation method is characterized by, In the step S5, the buried oxygen layer is etched by using a BOE solution. In the step S8, high-energy laser is used to irradiate the nano-pore, so that the surface tension of the buried oxygen layer is expanded to reduce the nano-pore to the preset size, and the step S6 is turned to; Or 7. The method according to claim 6, wherein In the step S8, liquid solidifiable polyimide is coated on the surface of the V-shaped groove, sodium chloride with gold particles is placed near the nano-pore, the sodium chloride crystals slowly extrude each other, so that the polymer extending into the nano-pore is squeezed out, the polyimide is solidified by ultraviolet light or heating, then the sodium chloride is washed away, the nano-pore reduced to the preset size is obtained, and the step S6 is turned to. The preset size is greater than or equal to 1 nm and less than or equal to 100 nm; The number of the nano-pores is greater than or equal to 2 and less than or equal to 40000; The width of the buried oxygen layer exposed by the V-shaped groove is greater than or equal to 1 nm and less than or equal to 100 nm; The preset angle is 90 degrees; The metal film in the step S2 is an Al film, a Ni film, a Cu film, a Ti film or an Au film; The alkali solution is a KOH solution or a TMAH solution.

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