A high-performance approximate multiplier based on operand clipping and its calculation method

Abstract

The present invention discloses a high-performance approximate multiplier based on operand clipping and a calculation method thereof. The approximate multiplier comprises: a partial product generation module, a partial product tree compression module, a carry adder module, and a shift module. The partial product generation module comprises an operand clipping module and a bit product module. The operand clipping module performs a clipping operation on the multiplier and the multiplicand to obtain an approximate operand, and the bit product module obtains the corresponding partial product. The partial product tree compression module is used to obtain two addends for the final summation. The carry adder module is used to add the two addends, and the shift module is used to shift the output of the carry adder module to obtain the desired binary result. The present invention can greatly reduce the area, delay, and power consumption of a multi-bit multiplier while also maintaining good accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-performance multiplier and a calculation method based on operand clipping. Background Art

[0002] In recent years, with the rapid development of big data, the amount of image information that needs to be processed has increased exponentially. Basic image processing includes image filtering, edge detection, and sharpening. Image filtering operations consume a large number of multiplication and addition units, but the accuracy requirements for the results during the filtering process are not very strict. Using precise multipliers would make the computing units too large, and the multipliers would frequently flip, making the power consumption of the image processing units a significant issue. Furthermore, since most edge computing terminals are mobile devices with limited power supply, the power consumption of these devices is particularly prominent. Therefore, low-power multipliers based on approximate computing have emerged. They have successfully achieved relatively good performance while significantly reducing multiplier power consumption by sacrificing a small amount of computational accuracy. Summary of the Invention

[0003] The present invention aims to address the deficiencies of the above-mentioned prior art and proposes a low-power, high-performance approximate multiplier based on operand clipping, in order to greatly improve the performance of the multiplier while reducing chip power consumption and area, and maintaining good accuracy.

[0004] In order to achieve the above-mentioned object, the present invention adopts the following technical solutions:

[0005] The high-performance approximate multiplier based on operand clipping of the present invention is characterized by comprising: a partial product generation module, a partial product tree compression module, a carry adder module and a shift module;

[0006] The partial product generation module includes an operand clipping module and a bit product module;

[0007] The operand clipping module sets a truncation interval k according to the number of bits n of operand A and generates an approximate flag Ac; selects whether to shift the operand A according to the approximate flag Ac, and then clips the operand A according to the truncation interval k, thereby generating an approximate operand Ap; the operand clipping module also processes the operand B in the same manner to obtain an approximate operand Bp;

[0008] The bit product module uses an AND gate array to perform an AND operation on each bit of the approximate operand Ap and each bit of the approximate operand Bp to generate a partial product tree;

[0009] The partial product tree compression module is composed of a full adder group and a half adder group, and is used to compress the partial product tree into the final two rows of addends;

[0010] The carry adder module is composed of 2n-2k-1 full adders and 2 half adders, and is used to add the final two addends to obtain an intermediate result;

[0011] The shift module is composed of two 2n-bit shift registers and is used to shift the intermediate result to obtain the required binary product.

[0012] The high performance approximate multiplier of the present invention is also characterized in that:

[0013] The operand clipping module includes two registers, a first n-2k-2 input OR gate, two two-input OR gates, a first shift register, a first two-to-one multiplexer, and 2k-1 two-input AND gates;

[0014] The input of the first register is operand A, and the output is the number of bits n of the operand;

[0015] The input end of the second register is connected to the output end of the first register, and the output of the second register is the interception interval k;

[0016] The first shift register input is operand A, and the output is the result A of operand A shifted left by two bits. 2_left ;

[0017] The first input end of the operand clipping module is the input end of the first shift register;

[0018] The second input end of the operand clipping module is the output end of the first register;

[0019] The third input terminal of the operand clipping module is the output terminal of the second register;

[0020] The output end of the operand clipping module is the output end of the first two-to-one multiplexer;

[0021] The inputs of the OR gate of the first n-2k-2 inputs are respectively the highest bit to the 2k+2th bit of the operand A, and the output is the approximate flag bit Ac;

[0022] The selection control terminal of the first two-to-one multiplexer is connected to the output terminal of the first n-2k-2 input OR gate, and the "0" input terminal of the first two-to-one multiplexer is connected to the output A of the first shift register. 2_left , the "1" input of the first two-to-one multiplexer is the input operand A, and the output of the first two-to-one multiplexer is the operand A' that has been selectively shifted but not clipped;

[0023] The first input ends of the 2k-2 two-input AND gates are sequentially connected to the 1st to k-1th bits and the k+1th to 2k-1th bits of the operand A'; the second input ends of the 2k-2 two-input AND gates are connected to a low level, and the outputs are all "0", which serve as the 1st to k-1th bits and the k+1th to 2k-1th bits output by the operand clipping module; the 0th bit, the kth bit, and the 2k+1th to the nth bits of the operand A' are sequentially used as the 0th bit, the kth bit, and the 2k+1th to the nth bits output by the operand clipping module;

[0024] The first input end of the 2k-1th two-input AND gate inputs the 2k-2th bit of operand A, and the second input end inputs the 2k-1th bit of operand A; the output end of the 2k-1th two-input AND gate is connected to the first input end of the first two-input OR gate, the second input end of the first two-input OR gate inputs the 2kth bit of operand A, and the output of the first two-input OR gate is the 2kth bit output by the operand clipping module.

[0025] Furthermore, the shift module is composed of a two-input AND gate, a two-input OR gate, two two-to-one multiplexers, and two shift registers, and is sequentially: a two-input 2kth AND gate, a two-input fourth OR gate, a second multiplexer and a third multiplexer, a second shift register, and a third shift register;

[0026] The first input of the shift module is the output P0 of the carry adder module;

[0027] The second input of the shift module is the output approximate flag Ac of the first OR gate;

[0028] The third input of the shift module is the output approximate flag bit Bc of the first OR gate;

[0029] The input of the second shift register is the output P0 of the carry adder module; the output is the result P of the carry adder module output shifted right by two bits. right ;

[0030] The input of the third shift register is the output of the second multiplexer, and the output is the result of the output of the second multiplexer shifted right by two bits. right ';

[0031] The first input of the 2kth AND gate is the output approximate flag bit Ac of the first OR gate, and the second input is the output approximate flag bit Bc of the first OR gate;

[0032] The input signal of the first input terminal of the fourth OR gate is the output approximate flag bit Ac of the first OR gate, and the input signal of the second input terminal is the output approximate flag bit Bc of the first OR gate;

[0033] The control end of the second multiplexer is the output end of the fourth OR gate, the input signal of the "0" input end is the output P0 of the carry adder module, and the "1" input end is the output end of the second shift register.

[0034] The control terminal of the third multiplexer is the output terminal of the 2kth AND gate, the "0" input terminal is connected to the output terminal of the second multiplexer; the "1" input terminal is the output terminal of the third shift register;

[0035] The output end of the shift module is the output end of the third multiplexer.

[0036] The calculation method of a high-performance approximate multiplier of the present invention is characterized by being performed according to the following steps:

[0037] Step 1: Obtain the interception interval k of operand A according to formula (1), and use the shift register to shift right by 2 bits to achieve:

[0038] (1)

[0039] In formula (1), n ​​is the number of operands, Indicates a round-down operation;

[0040] Step 2: Obtain the approximate flag Ac according to formula (2), and use an OR gate with n-2k-2 inputs to output the approximate flag Ac:

[0041] Ac=A n-1 +A n-2 +...+A 2k+3 +A 2k+2 (2)

[0042] In formula (2), An-1 is the highest bit of operand A, and the n-2k-2 bits are taken in sequence as the input of the n-2k-2 input OR gate. The output end of the n-2k-2 input OR gate is connected to the selection control end of the two-to-one multiplexer to decide whether to perform a shift operation on operand A. The output result is A';

[0043] Step 3: Interception of operand A:

[0044] Step 3.1: 2k-2 two-input AND gates intercept the 1st to k-1th and k+1th to 2k-1th bits of operand A' according to formula (3) to obtain the 1st to k-1th and k+1th to 2k-1th bits of the approximate operand.

[0045] A Pi =A i 0, when i=1, 2...k-1 or i=k+1, k+2...2k-1 (3)

[0046] Formula (3) represents the interception operation of bits 0 to 2k-1 of operand A, retaining bits 0 and k, and removing bits 1 to k-1 and bits k+1 to -2k-1;

[0047] Step 3.2: Update the 2kth bit A of the intercepted operand A using formula (4) 2k , thus obtaining the updated 2k-th bit A 2k ' :

[0048] (4)

[0049] Step 4: Bitwise product:

[0050] The corresponding bits of the n-2k+2-bit multiplier and the n-2k+2-bit multiplicand are ANDed together through an AND gate array to generate (n-2k+2)×(n-2k+2) partial products, which are arranged into a partial product tree with n-2k+2 rows and 2n-2k+1 columns.

[0051] Step 5: Compression and simplification of partial product trees:

[0052] The partial product tree is simplified using a combination of full adders and half adders to obtain an accurate simplified result.

[0053] Step 6: Generation of binary product:

[0054] A carry adder module composed of 2n-2k+1 full adders and 2 half adders adds and sums the precise simplified results, and then inputs the sum into a shift register for a corresponding shift operation, thereby obtaining the desired binary product.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] 1. Take the example of an operand with n=8 and a truncation interval of k=2. The partial product tree generated by the conventional exact multiplier has 8 rows and 15 columns. During partial product compression, the exact multiplier requires 6 full adders and 2 half adders. The approximate multiplier proposed in the present invention requires only 4 full adders and 5 half adders during compression, significantly fewer full adders than the exact multiplier. Therefore, the approximate multiplier of the present invention has an area advantage over the exact multiplier.

[0057] 2. Take, for example, an operand with n=8 and a truncation interval of k=2. The conventional precise multiplier requires 13 full adders and two half adders in the carry-add module. The approximate multiplier proposed in the present invention requires only 11 full adders and two half adders in the carry-add module. Therefore, the approximate multiplier of the present invention significantly outperforms the precise multiplier in terms of hardware overhead and power consumption.

[0058] 3. Take, for example, the number of operands n = 8 and the truncation interval k = 2. The existing precise multiplier requires seven steps to compress partial products, which consumes at least seven machine cycles. The approximate multiplier proposed in this invention requires only four steps, significantly reducing the critical path delay. Therefore, the approximate multiplier of this invention significantly outperforms the precise multiplier in terms of speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Schematic diagram of the structure of a high-performance approximate multiplier based on operand clipping according to the present invention;

[0060] Figure 2 This is a schematic diagram of the operand cutting module of the present invention;

[0061] Figure 3 is a schematic diagram of a shift module of the present invention;

[0062] Figure 4 It is the relationship diagram between the number of operands n and the interception interval k;

[0063] Figure 5 To update the 2k-bit operand A 2k Gate-level circuit diagram;

[0064] Figure 6 The truth table of a6, a5, a4 and the updated a6' when n = 10, k = 3 is shown below.

[0065] Figure 7 Schematic diagram of the partial product compression process of the exact multiplier when n=8;

[0066] Figure 8 Schematic diagram of the partial product compression process of the approximate multiplier based on operand clipping of the present invention when n=8;

[0067] Figure 9 This is a relationship diagram between the approximate flag bit and the number of shift bits in the present invention. DETAILED DESCRIPTION

[0068] In this embodiment, Figure 1 As shown in the figure, a high-performance approximate multiplier based on operand clipping is mainly used in fault-tolerant applications such as image processing and deep learning, as well as to cope with endurance challenges in extreme environments. It specifically includes: a partial product generation module, a partial product compression module, a carry adder module, and a shift module;

[0069] The partial product generation module consists of an operand clipping module and a bitwise product module. The operand clipping module sets the truncation interval k according to the number of bits n of operand A and generates an approximate flag Ac. Based on the approximate flag Ac, it selects whether to shift operand A and then clips it according to the truncation interval k to generate an approximate operand Ap. The operand clipping module also processes operand B in the same way to obtain an approximate operand Bp.

[0070] The bit product module uses an AND gate array to perform an AND operation on each bit of the approximate operand Ap and each bit of the approximate operand Bp, generating a total of (n-2k+2)*(n-2k+2) partial products, which are arranged into a partial product tree with n-2k+2 rows and 2n-2k+1 columns.

[0071] The partial product compression module uses a combination of full adders and half adders to compress and simplify the partial product tree to obtain the final two rows of binary data.

[0072] The carry adder module uses a combination of two half adders and 2n-2k+1 full adders to perform the final addition operation on the two rows of binary data obtained by the partial product compression module to obtain a binary result.

[0073] The shift module shifts the result generated by the carry adder module according to the approximate flags Ac and Bc to obtain the final binary result. The shift module is composed of two binary multiplexers. The control terminal of the first binary multiplexer is the result of the "OR" of the two approximate flags. If the result is 1, it means that at least one of the two approximate flags is 1, and the result is first shifted right by two positions. The control terminal of the second binary multiplexer is the result of the "AND" of the two approximate flags. If the result is 1, it means that both approximate flags are 1, and the result is again shifted right by two positions.

[0074] In this embodiment, Figure 2 As shown, the operand clipping module includes 2 registers, a first n-2k-2 input OR gate, 2 two-input OR gates, a first shift register, a first two-to-one multiplexer, and 2k-1 two-input AND gates;

[0075] The input of the first register is operand A, and the output is the number of bits n of the operand;

[0076] The input end of the second register is connected to the output end of the first register, and the output of the second register is the interception interval k;

[0077] The first shift register input is operand A, and the output is the result A of operand A shifted left by two bits. 2_left ;

[0078] The first input end of the operand clipping module is the input end of the first shift register;

[0079] The second input end of the operand clipping module is the output end of the first register;

[0080] The third input terminal of the operand clipping module is the output terminal of the second register;

[0081] The output of the operand clipping module is the output of the first two-to-one multiplexer;

[0082] The inputs of the first n-2k-2 input OR gate are the highest bit to the 2k+2th bit of operand A, and the output is the approximate flag bit Ac;

[0083] The selection control terminal of the first two-to-one multiplexer is connected to the output terminal of the first n-2k-2 input OR gate, and the "0" input terminal of the first two-to-one multiplexer is connected to the output A of the first shift register. 2_left , the "1" input of the first two-to-one multiplexer is the input operand A, and the output of the first two-to-one multiplexer is the operand A' that has been selectively shifted but not clipped. The first input ends of the 2k-2 two-input AND gates are connected to the 1st to k-1th bits and the k+1th to 2k-1th bits of A' in sequence; the second input ends of the 2k-2 two-input AND gates are connected to a low level, and the outputs are all 0, which are the 1st to k-1th bits and the k+1th to 2k-1th bits output by the operand clipping module. The 0th bit, the kth bit, and the 2k+1th to nth bits of A' are sequentially used as the 0th bit, the kth bit, and the 2k+1th to nth bits output by the operand clipping module;

[0084] The first input end of the 2k-1th two-input AND gate inputs the 2k-2th bit of operand A, and the second input end inputs the 2k-1th bit of operand A; the output end of the 2k-1th two-input AND gate is connected to the first input end of the first two-input OR gate, the second input end of the first two-input OR gate inputs the 2kth bit of operand A, and the output of the first two-input OR gate is the 2kth bit output by the operand clipping module.

[0085] In this embodiment, Figure 3 As shown, the shift module is composed of a two-input AND gate, a two-input OR gate, two two-to-one multiplexers, and two shift registers, which are: the 2kth two-input AND gate, the fourth two-input OR gate, the second multiplexer and the third multiplexer, the second shift register, and the third shift register.

[0086] The first input of the shift module is the output P0 of the carry adder module;

[0087] The second input of the shift module is the output approximate flag Ac of the first OR gate;

[0088] The third input of the shift module is the output approximate flag bit Bc of the first OR gate;

[0089] The input of the second shift register is the output P0 of the carry adder module; the output is the result P of the carry adder module output shifted right by two bits. right ;

[0090] The input end of the third shift register is the output of the second multiplexer, and the output end is the result P of the output of the second multiplexer shifted right by two bits. right ';

[0091] The first input terminal of the 2kth AND gate is the output approximate flag bit Ac of the first OR gate, and the second input terminal is the output approximate flag bit Bc of the first OR gate;

[0092] The input signal of the first input terminal of the fourth OR gate is the output approximate flag bit Ac of the first OR gate, and the input signal of the second input terminal is the output approximate flag bit Bc of the first OR gate;

[0093] The control end of the second multiplexer is the output end of the fourth OR gate, the input signal of the 0 input end is the output P0 of the carry adder module, and the 1 input end is the output end of the second shift register.

[0094] The control terminal of the third multiplexer is the output terminal of the 2kth AND gate, the 0 input terminal is connected to the output terminal of the second multiplexer; the 1 input terminal is the output terminal of the third shift register;

[0095] The output end of the shift module is the output end of the third multiplexer.

[0096] In this embodiment, a high-performance calculation method of an approximate multiplier based on operand clipping includes the following steps:

[0097] Step 1: Obtain the interception interval k of operand A according to formula (1), and use the shift register to shift right by 2 bits to achieve:

[0098] (1)

[0099] In formula (1), n ​​is the number of operands, Indicates a round-down operation; the relationship between the number of operands n and the truncation interval k is as follows Figure 4As shown, when n≤5, k=1, that is, the operands are not clipped; when 6≤n≤9, k=2, that is, the low-order a1 and a3 are clipped (the lowest order is a0, increasing in sequence), and the value of a4 is updated to a4'. When 10≤n≤13, k=3, that is, a1, a2, a4, and a5 are clipped, and the value of a6 is updated to a6'. The selection of the truncation interval determines the performance, area, power consumption, accuracy, and other aspects of the approximate multiplier. The calculation method of the operand truncation interval adopted by the present invention ensures that no clipping is performed or the clipping interval is very small when the number of operands is not high, and a large clipping interval is selected when the number of operands is large. While ensuring performance, the accuracy of the result is greatly improved.

[0100] Step 2: Generate approximate flag bits:

[0101] According to formula (2), the approximate flag Ac is obtained, and an OR gate with n-2k-2 inputs is used to output the approximate flag Ac:

[0102] Ac=A n-1 +A n-2 +...+A 2k+3 +A 2k+2 (2)

[0103] In formula (2), An-1 is the highest bit of operand A, and the n-2k-2 bits are taken in sequence as the input of the n-2k-2 input OR gate. The output end of the n-2k-2 input OR gate is connected to the selection control end of the two-to-one multiplexer to decide whether to perform a shift operation on operand A. The output result is A';

[0104] Step 3: Interception of operand A:

[0105] Step 3.1: 2k-2 two-input AND gates intercept the 1st to k-1th and k+1th to 2k-1th bits of operand A' according to formula (3) to obtain the 1st to k-1th and k+1th to 2k-1th bits of the approximate operand.

[0106] A Pi =A i · 0, (i=1, 2...k-1 or i=k+1, k+2...2k-1) (3)

[0107] Formula (3) represents the interception operation of bits 0 to 2k-1 of operand A, retaining bits 0 and k, and removing bits 1 to k-1 and bits k+1 to -2k-1;

[0108] Step 3.2: Update the 2kth bit A of the intercepted operand A using formula (4) 2k , thus obtaining the updated 2k-th bit A 2k ' :

[0109] (4)

[0110] In formula (4), k=1 means no approximate clipping of the operands is performed and A is not changed. 2k ; When k ≥ 2, update A 2k The value of

[0111] like Figure 5 As shown, update the circuit of the 2kth bit. Figure 6 As shown in the figure, when n = 10 and k = 3, the values ​​of a6, a5, and a4 and the updated value of a6'. When a6a5a4 = 011 is input, if the value of a6 is not updated, a6a5a4 becomes 000 after cropping, with a relative error of 100%. After updating a6, a6a5a4 = 100, with a relative error of 33.33%, greatly improving the accuracy of the cropping operation.

[0112] Step 4: Bitwise product:

[0113] The corresponding bits of the n-2k+2-bit multiplier and the n-2k+2-bit multiplicand are ANDed together through an AND gate array to generate (n-2k+2)×(n-2k+2) partial products, which are arranged into a partial product tree with n-2k+2 rows and 2n-2k+1 columns.

[0114] Step 5: Compression and simplification of partial product trees:

[0115] The combination of full adders and half adders is used to simplify the partial product tree to obtain an accurate simplified result; Figure 7 The figure shows the partial product compression process of the exact multiplier. Figure 8 The figure shows the partial product compression process of an approximate multiplier when n=8. When n=8, the partial product tree of the exact multiplier has 8 rows and 15 columns, requiring 7 steps to output a binary result. In contrast, the partial product tree of the approximate multiplier has 6 rows and 13 columns, making it much smaller in size. Furthermore, the exact multiplier can only simplify the first three rows of partial products in the first step, while the first four rows of the partial product tree generated by the approximate multiplier contain only two or three partial products in the same column. Therefore, the approximate multiplier only needs four steps to generate the final binary result. Compared to the exact multiplier, the approximate multiplier proposed in this invention, which uses operand clipping, reduces the number of accumulation steps by approximately 42.8%, significantly improving performance while also significantly reducing power consumption.

[0116] Step 6: Generation of binary product result:

[0117] The carry adder module, which consists of 2n-2k+1 full adders and 2 half adders, adds and sums the exact simplification results and inputs them into the shift register for the corresponding shift operation to obtain the required binary product. Figure 9 As shown in the figure, the corresponding relationship between the approximate flag bits Ac, Bc and the number of shift bits.

Claims

1. A high-performance approximate multiplier based on operand clipping, characterized by: A partial product generation module, a partial product tree compression module, a carry adder module, and a shift module; The partial product generation module includes an operand clipping module and a bit product module; The operand clipping module sets a truncation interval k according to the number of bits n of operand A and generates an approximate flag Ac; selects whether to shift the operand A according to the approximate flag Ac, and then clips the operand A according to the truncation interval k, thereby generating an approximate operand Ap; the operand clipping module also processes the operand B in the same manner to obtain an approximate operand Bp; The operand clipping module includes two registers, a first n-2k-2 input OR gate, two two-input OR gates, a first shift register, a first two-to-one multiplexer, and 2k-1 two-input AND gates; The input of the first register is operand A, and the output is the number of bits n of the operand; The input end of the second register is connected to the output end of the first register, and the output of the second register is the interception interval k; The first shift register input is operand A, and the output is the result A of operand A shifted left by two bits. 2_left ; The first input end of the operand clipping module is the input end of the first shift register; The second input end of the operand clipping module is the output end of the first register; The third input terminal of the operand clipping module is the output terminal of the second register; The output end of the operand clipping module is the output end of the first two-to-one multiplexer; The inputs of the OR gate of the first n-2k-2 inputs are respectively the highest bit to the 2k+2th bit of the operand A, and the output is the approximate flag bit Ac; The selection control terminal of the first two-to-one multiplexer is connected to the output terminal of the first n-2k-2 input OR gate, and the "0" input terminal of the first two-to-one multiplexer is connected to the output A of the first shift register. 2_left , the "1" input of the first two-to-one multiplexer is the input operand A, and the output of the first two-to-one multiplexer is the operand A' that has been selectively shifted but not clipped; The first input ends of the 2k-2 two-input AND gates are sequentially connected to the 1st to k-1th bits and the k+1th to 2k-1th bits of the operand A'; the second input ends of the 2k-2 two-input AND gates are connected to a low level, and the outputs are all "0", which serve as the 1st to k-1th bits and the k+1th to 2k-1th bits output by the operand clipping module; the 0th bit, the kth bit, and the 2k+1th to the nth bits of the operand A' are sequentially used as the 0th bit, the kth bit, and the 2k+1th to the nth bits output by the operand clipping module; The first input terminal of the 2k-1th two-input AND gate inputs the 2k-2th bit of operand A, and the second input terminal inputs the 2k-1th bit of operand A; the output terminal of the 2k-1th two-input AND gate is connected to the first input terminal of the first two-input OR gate, the second input terminal of the first two-input OR gate inputs the 2kth bit of operand A, and the output of the first two-input OR gate is the 2kth bit output of the operand clipping module; The bit product module uses an AND gate array to perform an AND operation on each bit of the approximate operand Ap and each bit of the approximate operand Bp to generate a partial product tree; The partial product tree compression module is composed of a full adder group and a half adder group, and is used to compress the partial product tree into the final two rows of addends; The carry adder module is composed of 2n-2k-1 full adders and 2 half adders, and is used to add the final two addends to obtain an intermediate result; The shift module is composed of two 2n-bit shift registers and is used to shift the intermediate result to obtain the required binary product.

2. The high-performance approximate multiplier according to claim 1, wherein: The shift module is composed of a two-input AND gate, a two-input OR gate, two two-to-one multiplexers, and two shift registers, which are: the 2kth two-input AND gate, the fourth two-input OR gate, the second and third multiplexers, the second shift register, and the third shift register. The first input of the shift module is the output P0 of the carry adder module; The second input of the shift module is the output approximate flag Ac of the first OR gate; The third input of the shift module is the output approximate flag bit Bc of the first OR gate; The input of the second shift register is the output P0 of the carry adder module; the output is the result P of the carry adder module output shifted right by two bits. right ; The input of the third shift register is the output of the second multiplexer, and the output is the result of the output of the second multiplexer shifted right by two bits. right '; The first input of the 2kth AND gate is the output approximate flag bit Ac of the first OR gate, and the second input is the output approximate flag bit Bc of the first OR gate; The input signal of the first input terminal of the fourth OR gate is the output approximate flag bit Ac of the first OR gate, and the input signal of the second input terminal is the output approximate flag bit Bc of the first OR gate; The control terminal of the second multiplexer is the output terminal of the fourth OR gate, the input signal of the "0" input terminal is the output P0 of the carry adder module, and the "1" input terminal is the output terminal of the second shift register; The control terminal of the third multiplexer is the output terminal of the 2kth AND gate, the "0" input terminal is connected to the output terminal of the second multiplexer; the "1" input terminal is the output terminal of the third shift register; The output end of the shift module is the output end of the third multiplexer.

3. A calculation method based on the high performance approximate multiplier according to claim 1, characterized in that Proceed as follows: Step 1: Obtain the interception interval k of operand A according to formula (1), and use the shift register to shift right by 2 bits to achieve: (1) In formula (1), n ​​is the number of operands, Indicates a round-down operation; Step 2: Obtain the approximate flag Ac according to formula (2), and use an OR gate with n-2k-2 inputs to output the approximate flag Ac: And = A n-1 +A n-2 +...+A 2k+3 +A 2k+2 (2) In formula (2), An-1 is the highest bit of operand A, and the n-2k-2 bits are taken in sequence as the input of the n-2k-2 input OR gate. The output end of the n-2k-2 input OR gate is connected to the selection control end of the two-to-one multiplexer to decide whether to perform a shift operation on operand A. The output result is A'; Step 3: Interception of operand A: Step 3.1, 2k-2 two-input AND gates intercept the 1st to k-1th and k+1th to 2k-1th bits of operand A' according to formula (3), and obtain the 1st to k-1th and k+1th to 2k-1th bits of the approximate operand; A Pi =A i · 0, when i = 1, 2... k - 1 or i = k + 1, k + 2... 2k - 1 (3) Formula (3) represents the interception operation of bits 0 to 2k-1 of operand A, retaining bits 0 and k, and removing bits 1 to k-1 and bits k+1 to -2k-1; Step 3.2: Update the 2kth bit A of the intercepted operand A using formula (4) 2k , thus obtaining the updated 2k-th bit A 2k ' : (4) Step 4: Bitwise product: The corresponding bits of the n-2k+2-bit multiplier and the n-2k+2-bit multiplicand are ANDed together through an AND gate array to generate (n-2k+2)×(n-2k+2) partial products, which are then arranged into a partial product tree with n-2k+2 rows and 2n-2k+1 columns. Step 5: Compression and simplification of partial product trees: The partial product tree is simplified using a combination of full adders and half adders to obtain an accurate simplified result. Step 6: Generation of binary product: A carry adder module composed of 2n-2k+1 full adders and 2 half adders adds and sums the precise simplified results, and then inputs the sum into a shift register for a corresponding shift operation, thereby obtaining the desired binary product.

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