Data processing apparatus and its data access circuitry

Abstract

A data processing apparatus includes a memory circuit and a data access circuit. The memory circuit includes a plurality of cache ways for storing data. In response to a first logic state of an enable signal, the data access circuit determines a cache hit occurs if a tag of an address of an access request is the same as a corresponding tag of the plurality of cache ways. In response to a second logic state of the enable signal, the data access circuit determines a cache hit occurs if the address is within one or more default address intervals designated by the data access circuit, and determines a cache miss occurs if the address is outside the one or more default address intervals.

Description

TECHNICAL FIELD

[0001] The present application relates to a data processing device and its data access circuit, and in particular, to a data processing device and its data access circuit capable of setting a cache memory as a tightly coupled memory. BACKGROUND

[0002] A processor can access a cache memory in one to several cycles, so caches are often used to store copies of data required by the processor to improve overall operation performance. However, the storage space of a cache is limited, and in some cases, important data can be evicted back to a main memory, so the processor needs to spend extra time to retrieve the data from the main memory. Moreover, users cannot know the addresses of the cache, and cannot directly access the data in the cache to observe the execution status of a program.

[0003] A tightly coupled memory is also a storage device that can be accessed by a processor in one to several cycles, so it is suitable for storing program codes with strict time requirements or storing data that needs to be frequently accessed. The storage space of a tightly coupled memory is allocated to a fixed address interval, so the data can be easily accessed by users and will not be evicted in general cases. However, because of the fixed addresses, the flexibility of a tightly coupled memory is lower than that of a cache. SUMMARY

[0004] The present application provides a data processing device including a memory circuit and a data access circuit. The memory circuit includes a plurality of cache ways for storing data. In response to a first logic state of an enable signal, the data access circuit determines a cache hit occurs if a tag of an address of an access request is the same as a corresponding tag of the plurality of cache ways. In response to a second logic state of the enable signal, the data access circuit determines a cache hit occurs if the address is located in one or more default address intervals designated by the data access circuit, and determines a cache miss occurs if the address is located outside the one or more default address intervals.

[0005] The present application provides a data access circuit for coupling to a memory circuit to access the memory circuit. The memory circuit includes a plurality of cache ways for storing data. The data access circuit is configured to perform the following operations: in response to a first logic state of an enable signal, determining a cache hit occurs if a tag of an address of an access request is the same as a corresponding tag of the plurality of cache ways; in response to a second logic state of the enable signal, determining a cache hit occurs if the address is located in one or more default address intervals designated by the data access circuit; and in response to the second logic state of the enable signal, determining a cache miss occurs if the address is located outside the one or more default address intervals.

[0006] One of the advantages of the above embodiments is that flexibility of program development and operation efficiency of products can be achieved.

[0007] Another advantage of the above embodiments is that a simple method for reading files in the cache is provided. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A simplified functional block diagram of a data processing system according to an embodiment of the present application.

[0009] Figure 2 A simplified functional block diagram of a cache according to an embodiment of the present application.

[0010] Figure 3 An operation diagram of a data access circuit searching for a target cache column.

[0011] Figure 4 A simplified functional block diagram of a data access circuit according to an embodiment of the present application.

[0012] Figure 5 A functional block diagram of a first logic circuit according to an embodiment of the present application.

[0013] Figure 6 A functional block diagram of a second logic circuit according to an embodiment of the present application.

[0014] Figure 7 A simplified functional block diagram of a data access circuit according to another embodiment of the present application.

[0015] Figure 8 A functional block diagram of a first logic circuit according to another embodiment of the present application.

[0016] Figure 9 A functional block diagram of a second logic circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0017] Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like reference numerals indicate like or similar components or method flows.

[0018] Figure 1Figure 1 is a simplified functional block diagram of a data processing system 100 according to an embodiment of the present application. The data processing system 100 includes an arithmetic circuit 110, a cache 120, and a main memory 130. The arithmetic circuit 110 and the cache 120 are coupled to each other via a data transmission interface, and the cache 120 and the main memory 130 are also coupled to each other via a data transmission interface. During operation of the arithmetic circuit 110, the arithmetic circuit 110 issues a plurality of read access commands to retrieve data. If a cache hit occurs, it means that the data to be retrieved by the arithmetic circuit 110 is stored in the cache 120, and the arithmetic circuit 110 directly obtains the data from the cache 120 to avoid time penalty of accessing the main memory 130.

[0019] When the arithmetic circuit 110 issues a write access command, if the address of the write access command is in a cacheable interval and a cache hit occurs, the arithmetic circuit 110 directly updates the data in the cache 120. If the address of the write access command is in a write-through interval, the corresponding data in the main memory 130 is also updated. If the address of the write access command is in a write-back interval, the main memory 130 is not updated temporarily, and the cache line in the cache 120 that has been updated is given a dirty flag. In subsequent operation, when the cache line with the dirty flag is selected to replace the data stored therein, the data stored in the cache line with the dirty flag is used to update the main memory 130.

[0020] In the embodiment, the cache 120 can be a unified cache for storing data and instructions, or can be implemented by a data cache and an instruction cache. The arithmetic circuit 110 can be implemented by one or more cores of a processor, a digital signal processor (DSP), a field programmable gate array (FPGA), or the like.

[0021] Figure 2 Figure 2 is a simplified functional block diagram of the cache 120 according to an embodiment of the present application. The cache 120 includes a data access circuit 210 and a memory circuit 220 coupled to each other. The data access circuit 210 is configured to receive an address of a read access command issued by the arithmetic circuit 110, retrieve data from the memory circuit 220 according to the received address, and return the data to the arithmetic circuit 110. When the arithmetic circuit 110 issues a write access command, the data access circuit 210 is configured to receive write data from the arithmetic circuit 110, and store the write data in the memory circuit 220 according to the address of the write access command.

[0022] The memory circuit 220 can be implemented in many ways. For ease of explanation, this application assumes that the memory circuit 220 is a multiple-way set association. Specifically, the memory circuit 220 includes a tag RAM 222 and a data RAM 224. The data access circuit 210 compares the tag of the requested address with the tag stored in the tag RAM 222, and then searches the corresponding cache column in the data RAM 224 to access the data based on the comparison result.

[0023] Figure 3 This is a schematic diagram illustrating the operation of the data access circuit 210 in searching the target cache column. Figure 3 As shown, the address 300 for the access request includes fields such as tag 312, index 314, and byte offset 316. Tag memory 222 includes four cache ways, and each way of tag memory 222 stores multiple tags. Data memory 224 also includes four cache ways, and each way of data memory 224 includes multiple cache columns for storing data. Furthermore, since memory circuit 220 is configured as a multiple-way set-associative, memory circuit 220 includes multiple cache sets 320. Each cache set 320 includes one tag from each cache way of tag memory 222 and one cache column from each cache way of data memory 224; that is, cache set 320 includes four tags and four cache columns. Multiple tags in cache set 320 are associated with multiple cache columns in cache set 320, and when any tag in cache set 320 is determined to be the same as the tag 312 for the access request, a cache hit occurs, and the associated cache column is accessed.

[0024] Specifically, the access request index 314 is used to identify a specific cache group 320. Then, multiple tags in the cache group 320 are transmitted to multiple comparators 330 for individual comparison with the access request tag 312. The path selector 340, based on the outputs of the multiple comparators 330, instructs the multiplexer 350 to select a cache column in the cache group 320 and output its stored data 360. At this point, if any tag in the cache group 320 matches the access request tag 312, the path selector 340 notifies the arithmetic circuit 110 of a cache hit via line 370. In some embodiments, the comparator 330, path selector 340, and multiplexer 350 may be located in the data access circuit 210.

[0025] Since the cache lines usually have storage capacity of multiple bytes (e.g., byte 0, byte 1, byte 2, and byte 3), the byte offset 316 of the access request can be used to specify a byte (e.g., byte 3) in the data 360. In the case that the address 300 corresponds to a read access request, the specified byte is outputted to the arithmetic circuit 110 through the line 380. On the other hand, in the case that the address 300 corresponds to a write access request, the cache bank 320 can receive the write data from the arithmetic circuit 110 through the line 390 and store the write data in its cache line.

[0026] Figure 4 A simplified functional block diagram of the data access circuit 210 according to an embodiment of the present application is shown in FIG. 4. The data access circuit 210 includes a first logic circuit 410, a second logic circuit 420, a third logic circuit 430, a plurality of comparators 440, and a multiplexer 450, but the present application is not limited thereto. In some embodiments, the comparators 440 and the multiplexer 450 can also be implemented by circuits other than the data access circuit 210. The first logic circuit 410 and the second logic circuit 420 are used to search the tags stored in the plurality of cache ways 10[0]~10[3] of the tag memory 222 according to the address 300 of the access request, in order to find the associated cache line in the plurality of cache ways 20[0]~20[3] of the data memory 224.

[0027] When the enable signal EN has a first logic state (e.g., logic 0), the first logic circuit 410 and the second logic circuit 420 operate the tag memory 222 and the data memory 224 as cache memories in response to the access request. That is, the tag memory 222 and the data memory 224 can be accessed by the access request with any address. On the other hand, when the enable signal EN has a second logic state (e.g., logic 1), the first logic circuit 410 and the second logic circuit 420 operate the tag memory 222 and the data memory 224 as tightly coupled memories in response to the access request. That is, the tag memory 222 and the data memory 224 can be accessed only by the access request with a specific address. The operation of the data access circuit 210 when the enable signal EN has the first logic state will be described first, and it is assumed that the first logic state of the enable signal EN represents that the enable signal EN is logic 0.

[0028] Figure 5 A functional block diagram of the first logic circuit 410 according to an embodiment of the present application is shown in FIG. 5. Please refer to FIG. 4 as well. Figure 4 Figure 5 ​First, the data access circuit 210 identifies a target bank group in the tag memory 222 and the data memory 224 according to the index 314 of the address 300. The multiplexer 440 is associated with the bank lanes 10[0]~10[3] of the tag memory 222, respectively, and compares the tag 312 of the address 300 with the tags in the bank lanes 10[0]~10[3] belonging to the target bank group. The comparison signals Ma[0]~Ma[3] outputted from the multiplexer 440 to the first logic circuit 410 correspond to the comparison results of the bank lanes 10[0]~10[3], respectively. For example, if the tag in the bank lane 10[0] belonging to the target bank group is different from the tag 312 of the address 300, the comparison signal Ma[0] is set to logic 0, and if the tag in the bank lane 10[0] belonging to the target bank group is the same as the tag 312 of the address 300, the comparison signal Ma[0] is set to logic 1, and so on.

[0029] The first logic circuit 410 includes a plurality of first AND gates 31, a plurality of second AND gates 32 and a plurality of first OR gates 41. The plurality of first AND gates 31 are configured to receive the inverted signal of the enable signal EN and the comparison signals Ma[0]~Ma[3], respectively. In the case that the enable signal EN is logic 0, the outputs of the plurality of first AND gates 31 are the same as the comparison signals Ma[0]~Ma[3], respectively. In addition, the plurality of second AND gates 32 output logic 0 because they also receive the enable signal EN. Each first OR gate 41 is configured to receive the output of a corresponding first AND gate 31 and the output of a corresponding second AND gate 32, so that the outputs of the plurality of first OR gates 41 are the same as the comparison signals Ma[0]~Ma[3], respectively. The outputs of the plurality of first OR gates 41 are outputted to the multiplexer 450 as the multiplexing signals MUX to instruct the multiplexer 450 to select one of the bank columns belonging to the target bank group from the bank lanes 20[0]~20[3] and output the data in the bank column. As mentioned above, the byte offset 316 of the address 300 is used to select a specific byte in the data to be provided to the operation circuit 110, which will not be described again.

[0030] Figure 6 A functional block diagram of the second logic circuit 420 according to an embodiment of the present application. Please refer to Figure 4 and Figure 6The second logic circuit 420 includes a third AND gate 33, a fourth AND gate 34, a second OR gate 42, and a third OR gate 43. The second OR gate 42 is configured to receive the comparison signals Ma[0]-Ma[3] and output an OR operation result of the comparison signals Ma[0]-Ma[3] to the fourth AND gate 34. The third AND gate 33 and the fourth AND gate 34 are both configured to receive the enable signal EN, such that when the enable signal EN is logic 0, the third AND gate 33 outputs logic 0, and the output of the fourth AND gate 34 is identical to the OR operation result of the comparison signals Ma[0]-Ma[3]. The third OR gate 43 is configured to receive the outputs of the third AND gate 33 and the fourth AND gate 34, such that the third OR gate 43 outputs the OR operation result of the comparison signals Ma[0]-Ma[3] as a hit signal HIT. The hit signal HIT is configured to indicate whether a cache hit or a cache miss occurs in the cache 120. For example, when a cache miss occurs, the hit signal HIT is set to logic 0, and when a cache hit occurs, the hit signal HIT is set to logic 1.

[0031] In summary, when the enable signal EN is logic 0, if the tag 312 of the address 300 is identical to a corresponding tag in the cache way 10[0]-10[3], the data access circuit 210 determines that a cache hit occurs. Otherwise, the data access circuit 210 determines that a cache miss occurs. The operation of the data access circuit 210 when the enable signal EN has a second logic state will be described below, and it is assumed that the second logic state of the enable signal EN represents that the enable signal EN is logic 1.

[0032] Referring to Figure 4 AND Figure 5 When the enable signal EN is logic 1, the first AND gate 31 outputs logic 0 due to receiving the inverted enable signal EN, i.e., the first AND gate 31 masks the comparison signals Ma[0]-Ma[3]. The second AND gate 32 is configured to receive a plurality of selection signals W[0]-W[3], respectively. The selection signals W[0]-W[3] are generated by decoding a plurality of corresponding bits in the tag 312. In some embodiments, the number of the corresponding bits can be represented by "Equation 1" below, where M is the number of the corresponding bits, and N is the number of the cache ways or the selection signals.

[0033] M = log2N Equation 1

[0034] In Figure 5In an embodiment, the data access circuit 210 decodes two bits in the tag 312 to obtain four selection signals W[0]-W[3]. For example, if the address 300 includes 32 bits (bit[31:0]) and bits 14-32 (bit[31:13]) are the tag 312, the data access circuit 210 can decode bits 14-15 (bit[14:13]). One of the selection signals W[0]-W[3] has a logic value different from the others. For example, if the decoded bits are 00, the selection signal W[0] is logic 1 and the selection signals W[1]-W[3] are logic 0. For another example, if the decoded bits are 01, the selection signal W[1] is logic 1 and the selection signals W[0], W[2]-W[3] are logic 0. For yet another example, if the decoded bits are 10, the selection signal W[2] is logic 1 and the selection signals W[0]-W[1], W[3] are logic 0, and so on.

[0035] The address determination signal RAN generated by the third logic circuit 430 is transmitted to the second AND gate 32. The third logic circuit 430 includes buffers 431 and 432 storing an upper address limit value Addl and a lower address limit value Add2, respectively, and is configured to determine whether the address 300 is between the upper address limit value Addl and the lower address limit value Add2. If not, the third logic circuit 430 sets the address determination signal RAN to logic 0. If yes, the third logic circuit 430 sets the address determination signal RAN to logic 1. However, the present application is not limited thereto, and the third logic circuit 430 can generate different first and second logic states to indicate whether the address 300 is between the upper address limit value Addl and the lower address limit value Add2, respectively, and the values of the first and second logic states can be determined according to actual circuit design. Thus, if the determination signal RAN is logic 0, the second AND gate 32 masks the selection signals W[0]-W[3]. If the determination signal RAN is logic 1, the outputs of the plurality of second AND gates 32 are respectively identical to the selection signals W[0]-W[3], and the outputs of the plurality of first OR gates 41 are also respectively identical to the selection signals W[0]-W[3].

[0036] In summary, when the enable signal EN is logic 0, the first logic circuit 410 uses the comparison signals Ma[0]-Ma[3] as the multi-task signal MUX. When the enable signal EN and the determination signal RAN are logic 1, the first logic circuit 410 uses the selection signals W[0]-W[3] as the multi-task signal MUX to specify the data of the corresponding one of the cache paths 20[0]-20[3] to be accessed.

[0037] Please refer to Figure 4 and Figure 6When the enable signal EN is logic 1, the determination signal RAN is transmitted to the second OR gate 43 through the third AND gate 33, and the fourth AND gate 34 blocks the OR operation result of the comparison signals M[0]-M[3]. Therefore, when the determination signal RAN is logic 1, the data access circuit 210 determines that a cache hit occurs (the hit signal HIT is logic 1); when the determination signal RAN is logic 0, the data access circuit 210 determines that a cache miss occurs (the hit signal is logic 0).

[0038] In summary, in the development stage of a program, since the storage addresses of instructions and data are not fixed, a user can operate the memory circuit 220 as a cache memory through the data access circuit 210 to obtain the acceleration function suitable for all address intervals. When the user determines the storage addresses of the program code or data to be accelerated, the user can operate the memory circuit 220 as a tightly coupled memory through the data access circuit 210 to focus on accelerating the default address interval (i.e., the interval defined by the upper address limit value Addl and the lower address limit value Add2).

[0039] When a conventional cache control circuit responds to a write access request with an address located in the write-back interval, if a cache miss occurs, the corresponding data in the main memory is first loaded into the cache, and then the cache control circuit updates the cache according to the cache hit rule. In some embodiments, when the data access circuit 210 responds to a write access request with an address located in the write-back interval, even if a cache miss occurs, the data access circuit 210 does not load the data in the main memory 130 into the memory circuit 220, nor store the write data corresponding to the write access request in the memory circuit 220. Instead, the data access circuit 210 directly writes the write data back to the main memory 130. That is, the data in the memory circuit 220 is not replaced at will, thereby further improving the acceleration efficiency.

[0040] In addition, since the user cannot specify a specific storage space of the read conventional cache memory, it is difficult for the user to obtain a temporary file during program execution for debugging. Through the data access circuit 210 in the above embodiments, the user can switch the memory circuit 220 from a cache memory to a tightly coupled memory during the execution of a program. In this way, the user can easily read the files in the cache by specifying the address during the execution of the program.

[0041] Figure 7 A simplified schematic diagram of a data access circuit 210 according to another embodiment of the present application. In this embodiment, the data access circuit 210 includes a first logic circuit 710, a second logic circuit 720, and a third logic circuit 730, and the enable signal EN includes a plurality of sub-enable signals EN[0]-EN[3]. Figure 8Fig. 1 is a functional block diagram of a first logic circuit 710 according to an embodiment of the present application. As shown in Fig. 1, the first logic circuit 710 includes a plurality of inverters 41, a plurality of inverters 42, a plurality of first AND gates 31, and a plurality of second AND gates 32. The plurality of inverters 41 receive a plurality of sub-enable signals EN[0]-EN[3] and output a plurality of inverted sub-enable signals EN[0]-EN[3]. The plurality of inverters 42 receive the plurality of sub-enable signals EN[0]-EN[3] and output the plurality of sub-enable signals EN[0]-EN[3]. The plurality of first AND gates 31 receive the plurality of inverted sub-enable signals EN[0]-EN[3] and output a plurality of first sub-address signals S[0]-S[3]. The plurality of second AND gates 32 receive the plurality of sub-enable signals EN[0]-EN[3] and output a plurality of second sub-address signals S[0]-S[3]. Figure 8 As shown in Fig. 1, the inverted sub-enable signals EN[0]-EN[3] are transmitted to the plurality of first AND gates 31, and the sub-enable signals EN[0]-EN[3] are transmitted to the plurality of second AND gates 32.

[0042] Please refer to Fig. 2 again. Figure 7 The third logic circuit 730 includes a plurality of buffers 431 and a plurality of buffers 432. The plurality of buffers 431 store a plurality of upper address limit values Add1, Add3, Add5, and Add7, and the plurality of buffers 432 store a plurality of lower address limit values Add2, Add4, Add6, and Add8. The upper address limit values Add1, Add3, Add5, and Add7 and the lower address limit values Add2, Add4, Add6, and Add8 define four address intervals. The third logic circuit 730 provides a plurality of sub-address judgment signals RAN[0]-RAN[3] to indicate whether the address 300 is located in the four address intervals. In some embodiments, the four address intervals do not overlap.

[0043] For example, if the address 300 is located in the address interval defined by the upper address limit value Add1 and the lower address limit value Add2, the sub-address judgment signal RAN[0] is set to logic 1; otherwise, the sub-address judgment signal RAN[0] is set to logic 0. For another example, if the address 300 is located in the address interval defined by the upper address limit value Add3 and the lower address limit value Add4, the sub-address judgment signal RAN[1] is set to logic 1; otherwise, the sub-address judgment signal RAN[0] is set to logic 0. The same applies to the other two sub-address judgment signals RAN[2] and RAN[3].

[0044] Figure 9 Fig. 3 is a functional block diagram of a second logic circuit 720 according to an embodiment of the present application. The second logic circuit 720 is similar to the second logic circuit 420 of Fig. 2, except that the second logic circuit 720 further includes a fourth OR gate 44 and a fifth OR gate 45. The fourth OR gate 44 receives the sub-address judgment signals RAN[0]-RAN[3], and the third AND gate 33 receives the output of the fourth OR gate 44. The fifth OR gate 45 receives the sub-enable signals EN[0]-EN[3], and the third AND gate 33 receives the output of the fifth OR gate 45. The fourth AND gate 34 receives the inverted output of the fifth OR gate 45. Figure 6

[0045] ​In this embodiment, if the enable signal EN has a first logic state (e.g., all of the sub-enable signals EN[0]-EN[3] are logic 0), the data read circuit 210 operates the memory circuit 220 as a cache memory. If the enable signal EN has a second logic state (e.g., one of the sub-enable signals EN[0]-EN[3] is logic 1), the data read circuit 210 operates the memory circuit 220 as a tightly coupled memory. In addition, when the access-requested address 300 is not located in the above-mentioned four address intervals, the judge signal RAN has a first logic state (e.g., all of the sub-judge signals RAN[0]-RAN[3] are logic 0); when the access-requested address 300 is located in one of the above-mentioned four address intervals, the judge signal RAN has a second logic state (e.g., one of the sub-judge signals RAN[0]-RAN[3] is logic 1), and the data access circuit 210 generates the multi-task signal MUX according to the selection signals W[0]-W[3].

[0046] From the above, Figure 7 The data access circuit 210 of the above-mentioned memory circuit 220 can operate the memory circuit 220 as a tightly coupled memory having a plurality of mutually non-overlapping address intervals, so as to increase the application flexibility thereof. The above-mentioned Figure 4 The remaining connection modes, components, embodiments, and advantages of the data access circuit 210 of the above-mentioned memory circuit 220 are applicable to the data access circuit 210 of the above-mentioned memory circuit 220, and thus are not repeated here for the sake of brevity. Figure 7

[0047] In the description and in the claims, certain terms have been used for brevity, clarity and understanding. No unnecessary limitations are to be implied therefrom beyond the require limitations set forth in the claims. The terms "comprises" and variations thereof do not have to be interpreted literally, but encompass the multiple instances of illustrated range or the several aspects of one or more embodiments. In addition, the terms "a" and "an" are defined as one or more unless explicitly stated otherwise, and the term "plurality" is defined as two or more unless explicitly stated otherwise.

[0048] In addition, unless explicitly stated otherwise, any singular article ("a", "an", "the") is to be read in the context of the article's normal usage and not to exclude the plural from coverage or vice versa.

[0049] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and practice described. Accordingly, all such variations are intended to be included within the scope of the application as defined in the following claims.

[0050] BRIEF DESCRIPTION OF DRAWINGS ​

[0051] 100: data processing system

[0052] 110: arithmetic circuit

[0053] 120: cache

[0054] 130: main memory

[0055] 210: data access circuit

[0056] 220 memory circuit

[0057] 222: tag memory

[0058] 224: data memory

[0059] 300: address

[0060] 312: tag

[0061] 314: index

[0062] 316: byte offset

[0063] 320: cache set

[0064] 330, 440: comparator

[0065] 340: path selector

[0066] 350, 450: multitasker

[0067] 360: data

[0068] 370, 380, 390: line

[0069] 410, 710: first logic circuit

[0070] 420, 720: second logic circuit

[0071] 430, 730: third logic circuit

[0072] 431, 432: buffer

[0073] Addl, Add3, Add5, Add7: upper address limit value

[0074] Add2, Add4, Add6, Add8: lower address limit value

[0075] Ma[0] ~ Ma[3]: comparison signal

[0076] EN: enable signal

[0077] EN[0] ~ EN[3]: sub-enable signal

[0078] RAN: address determination signal

[0079] RAN[0] - RAN[3]: sub-address determination signal

[0080] W[0] - W[3]: selection signal

[0081] 10[0] - 10[3], 20[0] - 20[3]: cache way

[0082] HIT: hit signal

[0083] 31: first AND gate

[0084] 32: second AND gate

[0085] 33: third AND gate

[0086] 34: fourth AND gate

[0087] 41: first OR gate

[0088] 42: second OR gate

[0089] 43: third OR gate

[0090] 44: fourth OR gate

[0091] 45: fifth OR gate

Claims

1. A data processing apparatus, comprising: A memory circuit, including multiple cache paths for storing data; as well as A data access circuit; In response to a first logic state of a consensus signal, if a tag of an address for an access request is the same as a corresponding tag of the plurality of cache paths, the data access circuit determines that a cache hit has occurred. In response to a second logic state of the enable signal, if the address is located within one or more default address ranges specified by the data access circuit, the data access circuit determines that a cache hit has occurred; otherwise, if the address is located outside the one or more default address ranges, the data access circuit determines that a cache miss has occurred. Each of the plurality of cache paths includes a cache column, and the data processing device further includes: Multiple comparators are associated with the multiple cache paths, and each comparator is used to compare the tag of the address with a tag of a corresponding cache path of the multiple cache paths; In response to the first logic state of the enable signal, the data access circuit uses the output of the plurality of comparators as a multitasking signal, the multitasking signal being used to specify the cache column of one of the plurality of cache paths, so that the data of the cache column is output to an arithmetic circuit. In response to the second logic state of the enable signal, if the address is located in one or more default address ranges, the data access circuit generates the multitasking signal based on multiple corresponding bits in the address.

2. The data processing apparatus according to claim 1, characterized in that, The data access circuit includes: A first logic circuit, coupled to the plurality of comparators, is configured to, in response to a first logic state of the enable signal, use the outputs of the plurality of comparators as the multiplexing signal, and to, in response to a second logic state of the enable signal, generate the multiplexing signal based on the plurality of corresponding bits in the address when the address is located within the one or more default address ranges; and A second logic circuit is configured to, in response to the first logic state of the enable signal, determine whether a cache hit or a cache miss occurs based on the OR operation result of the outputs of the plurality of comparators, and to, in response to the second logic state of the enable signal, determine whether a cache hit or a cache miss occurs based on the address.

3. The data processing apparatus according to claim 2, characterized in that, The first logic circuit includes: Multiple first AND gates are used to receive the inverted signal of the enable signal and to receive the outputs of the multiple comparators respectively; Multiple second AND gates are configured to receive the enable signal and an address determination signal, and to receive multiple selection signals corresponding to the multiple corresponding bits in the address, wherein a first logic state and a second logic state of the address determination signal respectively represent that the address is outside the one or more default address ranges and that the address is within the one or more default address ranges; and Multiple first OR gates are used to receive the outputs of the multiple first AND gates, and are also used to receive the outputs of the multiple second AND gates. The data access circuit uses the outputs of the multiple first OR gates as the multitasking signal.

4. The data processing apparatus according to claim 3, characterized in that, The second logic circuit includes: A second OR gate is used to receive the outputs of the plurality of comparators to generate the OR operation result of the outputs of the plurality of comparators; A third AND gate is used to receive the enable signal and the address determination signal; A fourth AND gate, used to receive an inverted signal of the enable signal and the output of the second OR gate; and A third OR gate is used to receive the outputs of the third AND gate and the fourth AND gate, and to output a hit signal. When the hit signal has a first logic value, the data access circuit determines that the cache miss has occurred. When the hit signal has a second logic value, the data access circuit determines that the cache hit has occurred.

5. The data processing apparatus according to claim 3, characterized in that, The address determination signal includes multiple sub-address determination signals, and the multiple second AND gates are respectively used to receive the multiple sub-address determination signals. The first logical state of the address judgment signal is that all of the plurality of sub-address judgment signals are a first logical value, and the second logical state of the address judgment signal is that one of the plurality of sub-address judgment signals is a second logical value. The enabling signal includes multiple sub-enabling signals. The multiple first AND gates are respectively used to receive multiple inverted signals of the multiple sub-enabling signals, and the multiple second AND gates are respectively used to receive the multiple sub-enabling signals. The first logic state of the enable signal is that all of the plurality of sub-enable signals are the first logic value, and the second logic state of the enable signal is that one of the plurality of sub-enable signals is the second logic value.

6. The data processing apparatus according to claim 5, characterized in that, The second logic circuit includes: A fourth OR gate is used to receive the address determination signal; A fifth OR gate is used to receive the enable signal; A second OR gate is used to receive the outputs of the plurality of comparators to generate the OR operation result of the outputs of the plurality of comparators; A third AND gate is used to receive the outputs of the fourth OR gate and the fifth OR gate; A fourth AND gate, used to receive the output of the second OR gate and the output of the fifth OR gate; and A third OR gate is used to receive the outputs of the third AND gate and the fourth AND gate, and to output a hit signal. When the hit signal has the first logic value, the data access circuit determines that the cache failure has occurred. When the hit signal has the second logic value, the data access circuit determines that the cache hit has occurred.

7. A data access circuit for coupling to a memory circuit to access the memory circuit, the memory circuit including a plurality of cache paths for storing data, and the data access circuit for performing the following operations: In response to a first logic state of a consensus signal, if a tag of an address requiring access is the same as a corresponding tag of the plurality of cache paths, a cache hit is determined to have occurred. In response to a second logic state of the enable signal, if the address is located in one or more default address ranges specified by the data access circuit, it is determined that a cache hit has occurred. as well as In response to the second logic state of the enable signal, if the address is outside the one or more default address ranges, a cache failure is determined to have occurred. Each of the plurality of cache paths includes a cache column, and the data access circuitry is coupled to a plurality of comparators respectively associated with the plurality of cache paths. Each comparator is used to compare the tag of the address with a tag of a corresponding cache path of the plurality of cache paths. The data access circuitry is also used to perform the following operations: In response to the first logic state of the enable signal, the outputs of the plurality of comparators are used as a multitasking signal, which is used to specify the cache column of one of the plurality of cache paths, so that the data of the cache column is output to an arithmetic circuit. as well as In response to the second logic state of the enable signal, if the address is located in one or more default address ranges, the multitasking signal is generated based on multiple corresponding bits in the address.

8. The data access circuit according to claim 7, characterized in that, include: A first logic circuit, coupled to the plurality of comparators, is configured to, in response to the first logic state of the enable signal, use the outputs of the plurality of comparators as the multitasking signal, and to, in response to the second logic state of the enable signal, generate the multitasking signal based on the plurality of corresponding bits in the address when the address is located in the one or more default address ranges. as well as A second logic circuit is configured to, in response to the first logic state of the enable signal, determine whether a cache hit or a cache miss occurs based on the OR operation result of the outputs of the plurality of comparators, and to, in response to the second logic state of the enable signal, determine whether a cache hit or a cache miss occurs based on the address.

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