FPGA Circuit TILE-Level Connection Inspection Method, Device, Electronic Device and Storage Medium

Abstract

The present invention provides a method, apparatus, electronic device and computer-readable storage medium for checking the connections at the TILE level of an FPGA circuit. The method for checking the connections at the TILE level of an FPGA circuit provided by the present invention includes: obtaining the connection relationships between the functional modules and CRAM units in the TILE BMA model at the TILE level, and generating a first connection check assertion file according to the connection relationships; obtaining the connection relationships between the functional modules and CRAM units in the TILE NETLIST netlist at the TILE level, and generating a second connection check assertion file according to the connection relationships; using the first connection check assertion file to check successively whether the connections between the TILE BMA model and the TILE NETLIST netlist are correct, and using the second connection check assertion file to check successively whether the connections between the TILE NETLIST netlist and the TILE BMA model are correct. The method for checking the connections at the TILE level of an FPGA circuit of the present invention improves the verification efficiency at the TILE level.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA circuit inspection, and in particular, to a method, device, electronic device and computer-readable storage medium for checking the connection at the TILE level of an FPGA circuit. Background Art

[0002] FPGA (Field-Programmable Gate Array) chips play a crucial role in fields such as communication, security, and industry. With the gradual improvement of the process level, the scale of FPGA chips has been continuously expanding, the performance has been continuously improved, and at the same time, the verification workload has also increased accordingly. How to effectively improve the verification efficiency of large-scale FPGA circuits has become an important issue.

[0003] The expansion of the scale of the FPGA circuit means an increase in the number of modules, the scale of the circuit netlist, and the complexity of the connections. As one of the verification levels of the FPGA circuit, the TILE level, writing assertion check files for connection checking tends to consume more time. At the same time, the connection check between the TILE BMA (Behavior Micro-Architecture) model and the TILE NETLIST netlist is carried out independently, resulting in certain repetitions and redundancies, making the verification efficiency at the TILE level relatively low. Summary of the Invention

[0004] The purpose of the present invention is to provide a method, device, electronic device and computer-readable storage medium for checking the connection at the TILE level of an FPGA circuit, so as to solve the technical problem of relatively low verification efficiency at the TILE level in the prior art.

[0005] The technical solution of the present invention is as follows. A method for checking the connection at the TILE level of an FPGA circuit is provided, including:

[0006] Obtain the connection relationship between each functional module and the CRAM unit in the TILE BMA model at the TILE level, and generate a first connection check assertion file according to this connection relationship;

[0007] Obtain the connection relationship between each functional module and the CRAM unit in the TILE NETLIST netlist at the TILE level, and generate a second connection check assertion file according to this connection relationship;

[0008] Use the first connection check assertion file to check whether the connection between the TILE BMA model and the TILE NETLIST netlist is correct, and use the second connection check assertion file to check whether the connection between the TILE NETLIST netlist and the TILE BMA model is correct.

[0009] Further, for the method for checking the connection at the TILE level of the FPGA circuit, the obtaining of the connection relationships between the functional modules and the CRAM units in the TILE-level TILE BMA model includes:

[0010] Obtain the wire names of the port connections of the functional modules and the CRAM units in the TILE-level TILE BMA model, and obtain the connection relationships between the functional modules and the CRAM units according to the port connection wire names.

[0011] Further, obtaining the connection relationships between the functional modules and the CRAM units according to the port connection wire names includes:

[0012] If the port connection wire names of two functional modules are the same, then the two functional modules are connected, and thus the connection relationships between the functional modules and the CRAM units are obtained.

[0013] Further, obtaining the connection relationships between the functional modules and the CRAM units according to the port connection wire names further includes:

[0014] If the port connection wire name of a functional module is the same as that of a CRAM unit, then the functional module is connected to the CRAM unit, and thus the connection relationships between the functional modules and the CRAM units are obtained.

[0015] Further, before using the first connection check assertion file to check whether the connections between the TILE BMA model and the TILE NETLIST netlist are correct, it further includes that if the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist are inconsistent, then make the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist consistent.

[0016] Further, making the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist consistent includes:

[0017] Extract the module names and their instance names from the TILE BMA model and the TILE NETLIST netlist respectively, and modify the instance name corresponding to the module name in the TILE NETLIST netlist that is the same as the module name in the TILE BMA model to be consistent with the instance name of this module name in the TILE BMA model.

[0018] Further, making the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist consistent includes:

[0019] Extract the module names and their instance names from the TILE BMA model and the TILE NETLIST respectively, and modify the instance names corresponding to the same module names in the TILE BMA model to be the same as the instance names of the module names in the TILE NETLIST.

[0020] Another technical solution of the present invention is as follows. There is provided a device for checking the TILE-level connection of an FPGA circuit, including a first assertion file generation module, a second assertion file generation module, and a connection check module;

[0021] The first assertion file generation module is used to obtain the connection relationships between the functional modules and the CRAM units in the TILE-level TILE BMA model, and generate a first connection check assertion file according to the connection relationships;

[0022] The second assertion file generation module is used to obtain the connection relationships between the functional modules and the CRAM units in the TILE-level TILE NETLIST, and generate a second connection check assertion file according to the connection relationships;

[0023] The connection check module is used to use the first connection check assertion file to check whether the connections between the TILE BMA model and the TILE NETLIST are correct, and use the second connection check assertion file to check whether the connections between the TILE NETLIST and the TILE BMA model are correct.

[0024] Another technical solution of the present invention is as follows. There is provided an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the method for checking the TILE-level connection of the FPGA circuit as described in any one of the above technical solutions.

[0025] Another technical solution of the present invention is as follows. There is provided a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, it implements the method for checking the TILE-level connection of the FPGA circuit as described in any one of the above technical solutions.

[0026] The beneficial effects of the present invention are as follows: Obtain the connection relationships between the functional modules and CRAM units in the TILE BMA model at the TILE level, and generate a first connection check assertion file according to these connection relationships; obtain the connection relationships between the functional modules and CRAM units in the TILE NETLIST at the TILE level, and generate a second connection check assertion file according to these connection relationships; use the first connection check assertion file to check whether the connections between the TILE BMA model and the TILE NETLIST are correct successively, and use the second connection check assertion file to check whether the connections between the TILE NETLIST and the TILE BMA model are correct successively; through the above method, the verification efficiency at the TILE level is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic flowchart of the method for checking the TILE-level connection of the FPGA circuit according to the first embodiment of the present invention;

[0028] Figure 2 It is a schematic diagram of the TILE-level structure according to the first embodiment of the present invention;

[0029] Figure 3 It is a schematic diagram of the structure of the device for checking the TILE-level connection of the FPGA circuit according to the second embodiment of the present invention;

[0030] Figure 4 It is a schematic diagram of the structure of the electronic device according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

[0032] Referring to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0033] Figure 1It is a flowchart showing the method for checking the connection at the TILE level of the FPGA circuit in the first embodiment of the present invention. It should be noted that, if there are substantially the same results, the method for checking the connection at the TILE level of the FPGA circuit of the present invention is not limited to Figure 1 the process sequence shown. As Figure 1 shown, the method for checking the connection at the TILE level of the FPGA circuit mainly includes the following steps:

[0034] S101, obtain the connection relationship between each functional module and the CRAM unit in the TILE-level TILE BMA model, and generate a first connection check assertion file according to this connection relationship;

[0035] S102, obtain the connection relationship between each functional module and the CRAM unit in the TILE-level TILE NETLIST netlist, and generate a second connection check assertion file according to this connection relationship;

[0036] S103, use the first connection check assertion file to check whether the connection between the TILE BMA model and the TILE NETLIST netlist is correct, and use the second connection check assertion file to check whether the connection between the TILE NETLIST netlist and the TILE BMA model is correct.

[0037] Among them, the FPGA circuit TILE level includes multiple basic modules such as functional modules and CRAM units. These functional modules are modules that can implement some basic FPGA functions. For example, each functional module in the IOB TILE level includes IOBD, IOBS, BSCR, BKCL, CCS, etc.; the CRAM unit is used to store configuration points that can control the basic functions of the above functional modules, and the CRAM unit is a circuit module that controls the flow direction of the configuration data stream through word lines and bit lines.

[0038] Specifically, when generating the connection check assertion file, a script is used. First, the first connection check assertion file of each internal module is extracted based on the TILE BMA model, and then the second assertion check file is extracted based on the TILE NETLIST netlist.

[0039] In an optional implementation manner, the obtaining of the connection relationship between each functional module and the CRAM unit in the TILE-level TILE BMA model includes:

[0040] Obtain the wire names of the port connections of each functional module and the CRAM unit in the TILE-level TILE BMA model, and obtain the connection relationship between each functional module and the CRAM unit according to the port connection wire names.

[0041] In a specific embodiment, there are several connection relationships in the TILE hierarchical structure. These connection relationships include the connection relationships between functional modules, the connection relationships from functional modules to the top layer, the connection relationships from CRAM units to functional modules, and the connection relationships from CRAM units to the top layer (address and data ports). The schematic diagram of the TILE hierarchical structure is shown as Figure 2 shown. For the TILE hierarchical connection check, it is necessary to ensure the correctness of the above-mentioned several connection relationships, so as to ensure the normal signal transmission between functional modules and from functional modules to the top layer, and ensure that at the whole-chip level, the bitstream can be correctly configured to each specific configuration point of the functional module through the CRAM.

[0042] In an alternative embodiment, the connection relationships between each functional module and the CRAM unit are obtained according to the port connection line names, including:

[0043] If the port connection line names of two functional modules are the same, then these two functional modules are connected, and in this way, the connection relationships between each functional module and the CRAM unit are obtained.

[0044] In a specific embodiment, the instance names of each module are extracted from the TILE BMA model or the TILE NETLIST netlist through a script, then the ports of the module are extracted, and then the port connection line names are extracted. The information extracted is compared through the script to query which two modules have the same port connection line names. Part of the script code of the basic format of the TILE hierarchical BMA model is

[0045] ‘timescale 1ns / 1ps

[0046] module AND_OR_TILE(

[0047] inout DATA,

[0048] input ADDR_1.

[0049] input ADDR_2,

[0050] input[1:0]A,

[0051] output[1:0]B);

[0052] wire Q_1;

[0053] wire Q_2;

[0054] RAM ram_1(.DATA(DATA),.Q(Q_1),.ADDR(ADDR_1));

[0055] RAM ram_2(.DATA(DATA),.Q(Q_2),.ADDR(ADDR__2));

[0056] and_orinst_1(.A(A[0]),.B(B[0]),.PA(Q_1));

[0057] and_orinst_2(.A(A[1]),.B(B[1]),.PA(Q_2));

[0058] endmodule

[0059] RAM ram_1(.DATA(DATA),.Q(Q_1),.ADDR(ADDR_1)) is the instantiation of the CRAM cell RAM with the instance name ram_1, and and_or inst_1(.A(A[0]),.B(B[0]),.PA(Q_1)) is the instantiation of the functional module and_or with the instance name inst_1. In the above code, A, B, and PA are the ports of the functional module. In the above code, A[0], B[1], and Q_1 are the net names of the port connection lines. If the net names of the inst_1.PA port connection line and the ram_1.Q port connection line extracted are the same, then an assertion check file for checking the connection between inst_1.PA and ram_1.Q will be generated. The partial script code for generating the connection assertion check file is as follows,

[0060] assertproperty(

[0061] @(posedge clk) ram_1.Q == inst_1.PA)

[0062] else begin

[0063] $display("assertion_check:", "Q assertion fail"); $fatal;

[0064] end

[0065] The above code means to judge whether the inst_1.PA port and the ram_1.Q port are the same. When they are the same, the next judgment will be made; otherwise, a failure warning will be displayed. Through the above method, the first connection check assertion file and the second connection check assertion file can be generated respectively based on the TILE BMA model and the TILE NETLIST netlist.

[0066] In an alternative embodiment, obtaining the connection relationship between each functional module and the CRAM cell according to the net names of the ports further includes:

[0067] If the connection line names between a functional module and a port of a CRAM cell are the same, then the functional module is connected to the CRAM cell, so as to obtain the connection relationships between the functional modules and the CRAM cells.

[0068] In an optional embodiment, before using the first connection check assertion file to check whether the connections between the TILE BMA model and the TILE NETLIST are correct, it further includes that if the instance names of the same functional modules or the same CRAM cells in the TILE BMA model and the TILE NETLIST are inconsistent, then making the instance names of the same functional modules or the same CRAM cells in the TILE BMA model and the TILE NETLIST consistent.

[0069] It should be noted that since the TILE BMA model and the TILE NETLIST may have inconsistent hierarchical structures, it is necessary to check whether the instance names of the same functional modules or the same CRAM cells in the TILE BMA model and the TILE NETLIST are consistent. If they are inconsistent, then use a script to make the instance names of the same functional modules or the same CRAM cells in the TILE BMA model and the TILE NETLIST consistent.

[0070] In an optional embodiment, making the instance names of the same functional modules or the same CRAM cells in the TILE BMA model and the TILE NETLIST consistent includes:

[0071] Respectively extract the module names and their instance names from the TILE BMA model and the TILE NETLIST, and modify the instance name corresponding to the module name in the TILE NETLIST that is the same as the module name in the TILE BMA model to be the same as the instance name of this module name in the TILE BMA model.

[0072] In an optional embodiment, making the instance names of the same functional modules or the same CRAM cells in the TILE BMA model and the TILE NETLIST consistent includes:

[0073] Respectively extract the module names and their instance names from the TILE BMA model and the TILE NETLIST, and modify the instance name corresponding to the module name in the TILE BMA model that is the same as the module name in the TILE NETLIST to be the same as the instance name of this module name in the TILE NETLIST.

[0074] Among them, a script can be used to generate the first connection check assertion file based on the connection relationship of the TILE BMA model, thus saving a large amount of time compared to writing the connection check assertion file. This first connection check assertion file can be directly used for the connection verification of TILE BMA. For the problem of inconsistent hierarchical structures between the TILE BMA model and the TILE NETLIST netlist, a script is used to process the TILE NELTIST netlist. The script indexes the instantiation names corresponding to each module in the TILE BMA model and replaces the instantiation names of the common modules in the TILE NETLIST netlist to make them consistent with those in the TILE BMA model. At this time, the previously generated assertion file can be reused for the connection check of the TILE NETLIST; the above process is repeated for the TILE NETLIST netlist, generating an assertion check file based on the TILE NETLIST netlist, and the script processes the TILE BMA model to make the second connection check assertion file generated based on the TILENETLIST netlist reusable for the connection check of TILE BMA. This way of reusing the assertion check file achieves the effect of cross-verification and ensures the completeness of the TILE-level connection check.

[0075] In a specific embodiment, the instantiation names of the module names in the TILE BMA model and the TILE NETLIST netlist may be inconsistent. For example, the script extracts the module names and their instantiation names from the TILE BMA model and the TILE NETLIST netlist. In the TILE BMA model, the instantiation name of a certain module module1 is inst1, and in the TILE NETLIST netlist, the instantiation name of the same module module1 is inst2. Then, when the connection check file extracted from the TILE BMA is used to check the NETLIST, the instantiation names of the relevant modules in the NETLIST need to be changed to be the same as those in the BMA before the check; similarly, when the connection check file extracted from the TILE NETLIST is used to check the BMA model, the instantiation names of the relevant modules in the BMA also need to be changed to be the same as those in the NETLIST model.

[0076] In another specific embodiment, the TILE NETLIST netlist can be processed based on the TILE BMA model to obtain the file NETLIST_MODIFY. At the same time, the TILE BMA model can be processed based on the TILE NETLIST netlist to obtain the file BMA_MODIFY, so that the instance names of the modules in the NETLIST_MODIFY and the TILE BMA model are the same, and the instance names of the modules in the BMA_MODIFY and the TILE NETLIST netlist are the same. When checking whether the connection between the TILE BMA model and the TILE NETLIST netlist is correct, the first connection check assertion file is used to check the connection between the TILE BMA model and the NETLIST_MODIFY, and the second connection check assertion file is used to check the connection between the TILE NETLIST netlist and the BMA_MODIFY, so as to determine whether the connection relationship between the various modules in the TILE BMA model and the TILE NETLIST netlist is correct and whether their connection relationships are consistent at the same time.

[0077] The FPGA circuit TILE-level connection check method provided by the embodiments of the present invention obtains the connection relationship between the functional modules and the CRAM units in the TILE-level TILE BMA model, and generates a first connection check assertion file according to this connection relationship; obtains the connection relationship between the functional modules and the CRAM units in the TILE-level TILE NETLIST netlist, and generates a second connection check assertion file according to this connection relationship; uses the first connection check assertion file to check whether the connection between the TILE BMA model and the TILE NETLIST netlist is correct, and uses the second connection check assertion file to check whether the connection between the TILE NETLIST netlist and the TILE BMA model is correct; through the above method, the TILE-level verification efficiency is improved.

[0078] In the prior art, when performing FPGA full-chip TILE-level connection inspection, due to the large number of ports and complex connections, it takes a long time to write assertion checks, resulting in low verification efficiency at the TILE level. In the embodiments of the present invention, in the TILE-level connection inspection, scripts are used to generate assertion check files based on the TILE BMA model and the TILE NETLIST netlist respectively, and a method of mutual reuse during the connection inspection of the model and the netlist is used to solve the problem that the TILE BMA (behavioral level) model and the TILE NETLIST (gate level) netlist have different hierarchical structures due to being written by designers and directly extracted from the circuit respectively, resulting in incompatibility in assertion file verification. The embodiments of the present invention also ensure the connection consistency between the TILE-level BMA model and the NETLIST netlist through cross-verification of the reuse of connection inspection assertion files, thereby achieving the purpose of reducing verification time, improving verification efficiency, and ensuring verification completeness.

[0079] Figure 3 It is a schematic structural diagram of an FPGA circuit TILE-level connection inspection device according to the second embodiment of the present invention. As Figure 3 shown, the FPGA circuit TILE-level connection inspection device includes a first assertion file generation module 31, a second assertion file generation module 32, and a connection inspection module 33;

[0080] The first assertion file generation module 31 is configured to obtain the connection relationships between the functional modules and CRAM units in the TILE-level TILE BMA model, and generate a first connection inspection assertion file according to the connection relationships;

[0081] The second assertion file generation module 32 is configured to obtain the connection relationships between the functional modules and CRAM units in the TILE-level TILE NETLIST netlist, and generate a second connection inspection assertion file according to the connection relationships;

[0082] The connection inspection module 33 is configured to use the first connection inspection assertion file to sequentially check whether the connections of the TILE BMA model and the TILE NETLIST netlist are correct, and use the second connection inspection assertion file to sequentially check whether the connections of the TILE NETLIST netlist and the TILE BMA model are correct.

[0083] Figure 4 It is a schematic structural diagram of an electronic device according to the third embodiment of the present invention. As Figure 4 shown, the electronic device 40 includes a processor 41 and a memory 42 communicatively connected to the processor 41.

[0084] The memory 42 stores program instructions for implementing the FPGA circuit TILE-level connection inspection method according to any one of the above embodiments.

[0085] The processor 41 is configured to execute the program instructions stored in the memory 42 for code testing.

[0086] Among them, the processor 41 can also be referred to as a CPU (Central Processing Unit). The processor 41 may be an integrated circuit chip with signal processing capabilities. The processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0087] The memory 42 can be used to store the computer programs and / or modules. The processor 41 realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory 42 and by invoking the data stored in the memory 42. The memory 42 mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function, etc.

[0088] The memory 42 can be integrated in the processor 41 or can be separately provided from the processor 41.

[0089] The fourth embodiment of the present invention provides a storage medium. The storage medium of the embodiments of the present invention stores program instructions capable of implementing all the above methods. The storage medium can be non-volatile or volatile. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc. Among them, the program instructions can be stored in the above storage medium in the form of a software product, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks, optical disks, and other media that can store program codes, or terminal devices such as computers, servers, mobile phones, and tablets.

[0090] In several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of devices or modules can be in electrical, mechanical, or other forms.

[0091] In addition, each functional module in various embodiments of the present invention may be integrated into a processing unit, may exist physically alone for each module, or two or more modules may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software functional unit. The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A method for checking the connection at the TILE level of an FPGA circuit, characterized in that, The steps are as follows: Obtain the connection relationships among the functional modules and CRAM units in the TILE BMA model at the TILE level, and generate a first connection check assertion file according to the connection relationships; Obtain the connection relationships among the functional modules and CRAM units in the TILE NETLIST netlist at the TILE level, and generate a second connection check assertion file according to the connection relationships; Use the first connection check assertion file to check whether the connections between the TILE BMA model and the TILE NETLIST netlist are correct successively, and use the second connection check assertion file to check whether the connections between the TILE NETLIST netlist and the TILE BMA model are correct successively.

2. The method for checking the connection at the TILE level of the FPGA circuit according to claim 1, wherein The obtaining of the connection relationships among the functional modules and CRAM units in the TILE BMA model at the TILE level includes: Obtain the wire names of the port connections of the functional modules and CRAM units in the TILE BMA model at the TILE level, and obtain the connection relationships among the functional modules and CRAM units according to the port connection wire names.

3. The method for checking the connection at the TILE level of the FPGA circuit according to claim 1, wherein The obtaining of the connection relationships among the functional modules and CRAM units according to the port connection wire names includes: If the port connection wire names of two functional modules are the same, then these two functional modules are connected, and thus the connection relationships among the functional modules and CRAM units are obtained.

4. The method for checking the connection at the TILE level of the FPGA circuit according to claim 3, wherein The obtaining of the connection relationships among the functional modules and CRAM units according to the port connection wire names further includes: If the port connection wire name of a functional module is the same as that of a CRAM unit, then this functional module is connected to this CRAM unit, and thus the connection relationships among the functional modules and CRAM units are obtained.

5. The FPGA circuit TILE-level connection inspection method according to claim 1, wherein Before using the first connection check assertion file to check whether the connections between the TILE BMA model and the TILE NETLIST netlist are correct successively, it further includes that if the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist are inconsistent, then make the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist consistent.

6. The method for checking the connection at the TILE level of the FPGA circuit according to claim 5, wherein Making the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist consistent includes: Extract the module names and their instance names from the TILE BMA model and the TILE NETLIST netlist respectively, and modify the instance name corresponding to the module name that is the same as that in the TILE BMA model in the TILE NETLIST netlist to be the same as the instance name of this module name in the TILE BMA model.

7. The method for checking the connection at the TILE level of the FPGA circuit according to claim 5, wherein Making the instance names of the same functional modules or the same CRAM units in the TILE BMA model and the TILE NETLIST netlist consistent includes: Extract the module names and their instance aliases from the TILE BMA model and the TILE NETLIST respectively, and modify the instance alias corresponding to the module name in the TILE BMA model that is the same as the module name in the TILE NETLIST to be consistent with the instance alias of this module name in the TILENETLIST.

8. An FPGA circuit TILE-level connection inspection device, characterized in that It includes a first assertion file generation module, a second assertion file generation module, and a connection check module; The first assertion file generation module is used to obtain the connection relationship between each functional module and the CRAM unit in the TILE-level TILE BMA model, and generate a first connection check assertion file according to this connection relationship; The second assertion file generation module is used to obtain the connection relationship between each functional module and the CRAM unit in the TILE-level TILE NETLIST, and generate a second connection check assertion file according to this connection relationship; The connection check module is used to use the first connection check assertion file to check whether the connection between the TILE BMA model and the TILE NETLIST is correct, and use the second connection check assertion file to check whether the connection between the TILENETLIST and the TILE BMA model is correct.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the FPGA circuit TILE-level connection check method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the FPGA circuit TILE-level connection check method according to any one of claims 1 to 7.

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