Detection circuit, driving method thereof, and display device

Abstract

Embodiments of the present invention provide a detection circuit, a driving method thereof, and a display device. The detection circuit includes multiple drive circuits and multiple read signal lines, with one read signal line coupled to the multiple drive circuits. The detection circuit also includes a preconfiguration module coupled to the read signal line and configured to output a preset signal to the read signal line to preconfigure the potential on the read signal line. This invention can reduce noise in the detection signal during detection and improve detection accuracy.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a detection circuit, a driving method thereof, and a display device. Background Art

[0002] With the advancement of technology, a variety of display devices with fingerprint recognition capabilities have emerged on the market, including mobile phones, tablets, and smart wearable devices. Existing fingerprint recognition technologies are divided into capacitive, optical, and ultrasonic. Ultrasonic fingerprint recognition uses the reflection of ultrasound waves to capture fingerprint images. It doesn't require the screen to be illuminated, is unaffected by strong sunlight, and is relatively secure. While ultrasonic fingerprint recognition offers certain advantages over optical fingerprint recognition, it currently suffers from high detection noise, which can affect accuracy. Summary of the Invention

[0003] The embodiments of the present invention provide a detection circuit, a driving method thereof, and a display device to solve the problem in the prior art that detection accuracy is affected by large detection noise.

[0004] In a first aspect, an embodiment of the present invention provides a detection circuit, the detection circuit comprising a plurality of driving circuits and a plurality of read signal lines, wherein one read signal line is coupled to the plurality of driving circuits;

[0005] The detection circuit further includes a pre-configuration module coupled to the read signal line, and configured to output a preset signal to the read signal line to pre-configure the potential on the read signal line.

[0006] In a second aspect, an embodiment of the present invention provides a driving method for a detection circuit, wherein the detection circuit includes multiple driving circuits and multiple read signal lines, wherein one read signal line is coupled to the multiple driving circuits; the detection circuit also includes a pre-configuration module, and the read signal line is coupled to the pre-configuration module; the driving method includes: controlling a duty cycle of the detection circuit to include a preset phase and a detection phase;

[0007] In the preset stage, the preconfiguration module is controlled to be turned on to output a preset signal to the read signal line;

[0008] In the detection phase, at least part of the driving circuit is controlled to be turned on to output a detection signal to the read signal line.

[0009] In a third aspect, an embodiment of the present invention provides a display device, comprising the detection circuit provided by any embodiment of the present invention.

[0010] The detection circuit, driving method, and display device provided by embodiments of the present invention have the following advantageous effects: Embodiments of the present invention provide a read signal line coupled to a preconfiguration module. The preconfiguration module is capable of outputting a preset signal to the read signal line before the read signal line reads a valid detection signal, thereby preconfiguring the potential on the read signal line using the preset signal. This preconfiguration of the potential on the read signal line can reduce the effect of the opening action of a detection switch coupled to the read signal line on the potential on the read signal line, thereby reducing the noise introduced into the detection signal and improving detection accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0012] Figure 1 This is a schematic diagram of a detection circuit in the prior art;

[0013] Figure 2 A partial schematic diagram of a detection circuit provided by an embodiment of the present invention;

[0014] Figure 3 A flow chart of a driving method for a detection circuit provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of a driving circuit in another detection circuit provided by an embodiment of the present invention;

[0016] Figure 5 for Figure 4 A timing diagram of a detection circuit provided in an embodiment;

[0017] Figure 6 A partial schematic diagram of another detection circuit provided by an embodiment of the present invention;

[0018] Figure 7 A partial schematic diagram of another detection circuit provided by an embodiment of the present invention;

[0019] Figure 8 A schematic diagram of another detection circuit provided by an embodiment of the present invention;

[0020] Figure 9 A schematic diagram of another detection circuit provided by an embodiment of the present invention;

[0021] Figure 10 A working timing diagram of the detection circuit provided by an embodiment of the present invention;

[0022] Figure 11 A schematic diagram of another detection circuit provided by an embodiment of the present invention;

[0023] Figure 12 A schematic diagram of another detection circuit provided by an embodiment of the present invention;

[0024] Figure 13 A timing diagram of another detection circuit provided by an embodiment of the present invention;

[0025] Figure 14 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0027] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0028] Figure 1 A detection circuit diagram in the prior art is shown in FIG. Figure 1 As shown, the detection circuit includes multiple driver circuits 01 and multiple read signal lines 02. Optionally, multiple driver circuits 01 are arranged in an array. One read signal line 02 is coupled to multiple driver circuits 01 in a column of driver circuits. Three read signal lines 02 are coupled to the same demultiplexing circuit 03, and then coupled to a data processing circuit 04 through the demultiplexing circuit 03. Each demultiplexing circuit 03 includes three distribution switches 031, one for each read signal line 02. The detection circuit also includes branch control lines CHK1, CKH2, and CKH3. Read signal lines 02 are used to read detection signals output by each driver circuit 01 in a column of driver circuits. Each distribution switch 031 in the same demultiplexing circuit 03 is sequentially activated, outputting the detection signals read by read signal lines 02 to the data processing circuit 04 for processing. In the prior art, the activation of each distribution switch 031 causes the voltage on the read signal line 02 to change, introducing noise into the signal detected by the driver circuit 01, which can affect detection accuracy. And the greater the voltage change on the read signal line 02, the more serious the noise.

[0029] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a detection circuit, in which a pre-configuration module is set up. The pre-configuration module is used to pre-configure the voltage on the read signal line to reduce noise in the detection circuit and improve detection accuracy.

[0030] Figure 2 A partial schematic diagram of a detection circuit provided by an embodiment of the present invention, such as Figure 2 As shown, the detection circuit includes multiple driving circuits 10 and multiple reading signal lines 20, and one reading signal line 20 is coupled to multiple driving circuits 10; the detection circuit also includes a pre-configuration module 30, which is coupled to the reading signal line 20, and the pre-configuration module 30 is used to output a preset signal to the reading signal line 20 to pre-configure the potential on the reading signal line 20.

[0031] like Figure 2 As shown, the detection circuit also includes a multiplexing circuit 40, and the three read signal lines 20 are connected to the same multiplexing circuit 40; the multiplexing circuit 40 includes three detection switches 41, the first end of the detection switch 41 is coupled to the read signal line 20, the second end of the detection switch 41 is coupled to the output end OUT of the multiplexing circuit 40, and the control ends of the three detection switches 41 are respectively coupled to a branch control line. Figure 2 The shunt control lines shown in FIG. 4 include a first shunt control line CKH1 , a second shunt control line CKH2 , and a third shunt control line CKH3 . In some embodiments, the detection switch 41 includes a thin film transistor, which is either an n-type transistor or a p-type transistor.

[0032] The output terminal OUT of the multiplexing circuit 40 is coupled to the data processing circuit ( Figure 2 For a multiplexing circuit 40, the first branch control line CKH1, the second branch control line CKH2, and the third branch control line CKH3 are used to control the three detection switches 41 to be opened in sequence, and the signals read by the three read signal lines 20 are output to the data processing circuit in sequence and processed respectively.

[0033] Figure 2The multiplexing circuit 40 is shown schematically only. In an embodiment of the present invention, the multiplexing circuit 40 is coupled to at least two read signal lines 20. The number of detection switches 41 in the multiplexing circuit 40 is the same as the number of read signal lines 20 coupled thereto, i.e., one detection switch 41 corresponds to one read signal line 20. By configuring the multiplexing circuit 40, at least two read signal lines 20 can share a data processing circuit, thereby reducing the number of data processing circuits. In some applications, the display module includes the detection circuit provided by an embodiment of the present invention. The data processing circuit can be integrated into a detection chip, and the read signal line 20 is coupled to the detection chip via a pad. The configuration of the multiplexing circuit 40 can also reduce the number of pins provided on the detection chip.

[0034] In the embodiment of the present invention, the read signal line 20 is coupled to a preconfiguration module 30. The preconfiguration module 30 is capable of outputting a preset signal to the read signal line 20 before the read signal line 20 reads a valid detection signal, thereby preconfiguring the potential on the read signal line 20 using the preset signal. After the potential on the read signal line 20 is preconfigured, the effect of the opening action of the detection switch 41 coupled to the read signal line 20 on the potential on the read signal line 20 can be reduced, thereby reducing the noise introduced into the detection signal and improving detection accuracy.

[0035] Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a detection circuit, which is used to drive the detection circuit provided by the embodiment of the present invention. Figure 3 A flow chart of a driving method of a detection circuit provided by an embodiment of the present invention is shown as follows: Figure 3 As shown, the driving method includes: controlling the working cycle of the detection circuit to include a preset phase and a detection phase, and executing the detection phase after the preset phase; wherein,

[0036] In the preset stage, the pre-configuration module 30 is controlled to be turned on to output a preset signal to the read signal line 20 ; that is, in this stage, the potential on the read signal line 20 is pre-configured using the preset signal.

[0037] In the detection phase, at least part of the driving circuit 10 is controlled to be turned on to output a detection signal to the read signal line 20. In this phase, the detection circuit performs its detection function.

[0038] By adopting the driving method provided in an embodiment of the present invention, a preset stage is performed before the detection stage, and the potential on the read signal line 20 is pre-configured in the preset stage. This can reduce the influence of the opening action of the detection switch 41 coupled to the read signal line 20 on the potential on the read signal line 20, thereby reducing the noise introduced into the detection signal and improving the detection accuracy.

[0039] In some embodiments, Figure 4 Schematic diagram of a driving circuit in another detection circuit provided by an embodiment of the present invention. Figure 4 As shown, the driving circuit 10 includes a reset sampling module 11, a driving module 12, a control module 13 and a detection unit 14. The reset sampling module 11 is coupled to the detection unit 14, and the reset sampling module 11 is used to reset the detection unit 14. The reset sampling module 11 is also used to receive and store the electrical signal fed back by the detection unit 14; the driving module 12 is coupled to the reset sampling module 11, and the driving module 12 is used to read the electrical signal stored in the reset sampling module 11 and amplify the electrical signal; the control module 13 is coupled to the driving module 12 and the read signal line 20 respectively, and the control module 13 is used to provide the electrical signal amplified by the driving module 12 to the read signal line 20. Figure 3 As can be seen, the reset sampling module 11, the detection unit 14, and the driving module 12 are all coupled to the first node N1. In this embodiment of the present invention, after resetting the detection unit 14, the electrical signal fed back by the detection unit 14 is received and stored, thereby ensuring the accuracy of the acquired electrical signal. Simultaneously, the stored electrical signal is amplified by the driving module 12, facilitating the subsequent identification and computational processing of electrical signals of different magnitudes.

[0040] like Figure 4 As shown, the reset sampling module 11 includes a first transistor T1 and a storage capacitor C, the driving module 12 includes a second transistor T2, and the control module 13 includes a third transistor T3.

[0041] The control terminal of the first transistor T1 is coupled to the first control signal line 51, the first electrode of the first transistor T1 is coupled to the first voltage signal line 52, and the second electrode of the first transistor T1 is coupled to the detection unit 14. The first plate of the storage capacitor C is coupled to the detection unit 14, and the second plate of the storage capacitor C is coupled to the second voltage signal line 53, where the second voltage signal line 53 provides a constant voltage signal. The control terminal of the second transistor T2 is coupled to the first plate of the storage capacitor C, the first electrode of the second transistor T2 is coupled to the second plate of the storage capacitor C, and the second electrode of the second transistor T2 is coupled to the first electrode of the third transistor T3. The control terminal of the third transistor T3 is coupled to the read scan line 54, and the second electrode of the third transistor T3 is coupled to the read signal line 20.

[0042] The detection circuit provided by the embodiment of the present invention can be applied to ultrasonic fingerprint recognition detection. Figure 5 for Figure 4 A timing diagram of the detection circuit provided in the embodiment. Figure 5 As shown, the working process of the detection circuit includes a reset phase t1, a sampling phase t2, and a reading phase t3; wherein,

[0043] In the reset phase t1 , the first control signal line 51 provides an enable signal to control the first transistor T1 , and writes the signal provided by the first voltage signal line 52 into the first node N1 , thereby resetting the detection unit 14 .

[0044] In the sampling stage t2: a driving voltage Tx is applied to the driving electrode of the detection unit 14 to control the detection unit 14, so that the detection unit 14 generates an ultrasonic signal. At this time, the detection unit 14 acts as an ultrasonic transmitting sensor; in this stage, the first control signal line 51 continuously provides an enable signal to control the first transistor T1 to be turned on. After the detection unit 14 starts to emit ultrasonic waves, it delays for t0 time. The detection unit 14 acts as an ultrasonic receiving sensor and converts the received ultrasonic waves into electrical signals and stores them in the storage capacitor C; in the process of the detection unit 14 storing the electrical signal in the storage capacitor C, the first voltage signal line 52 provides a bias voltage to raise the electrical signal fed back by the detection unit 14, and stores the raised electrical signal in the storage capacitor C, so that a detection signal with a larger contrast can be obtained, and the sampling is completed.

[0045] During the read phase t3, the electrical signal stored in the storage capacitor C turns on the second transistor T2. Different electrical signals stored in the storage capacitor C result in different currents when the second transistor T2 turns on. The second transistor T2 amplifies the electrical signal stored in the storage capacitor C. When the read scan line 54 provides an enable signal, the third transistor T3 is turned on, and the read signal line 20 reads the amplified electrical signal. The signal read by the read signal line 20 is subsequently used to perform fingerprint recognition.

[0046] Combine Figure 2 Schematic diagram of the detection circuit structure and Figure 4 The structure of the driving circuit 10 is schematically shown. Figure 2 The figure also illustrates a read scan line 54, one of which is coupled to multiple drive circuits 10. When a read scan line 54 provides an enable signal to control the third transistor T3 in the drive circuit 10 connected thereto to turn on, the three detection switches 41 in the multiplexing circuit 40 are sequentially opened to control the signals read by the three read signal lines 10 to be output sequentially to the output terminal OUT of the multiplexing circuit 40. When the detection switch 41 is turned on, the voltage on the read signal line 10 changes, causing the storage capacitor C in the drive circuit 10 to charge and discharge. This process introduces noise into the signal detected by the drive circuit 10. In an embodiment of the present invention, the pre-configuration module 30 is configured to charge the read signal line 10 to a certain potential before the detection switch 41 in the multiplexing circuit 40 is turned on. This can reduce the impact of the opening action of the detection switch 41 on the potential on the read signal line 20, thereby reducing the charge and discharge effect, reducing the noise introduced into the detection signal, and improving detection accuracy.

[0047] In some embodiments, the detection unit 14 includes a stacked driving electrode 141, a piezoelectric material layer 142 and a receiving electrode 143, wherein the piezoelectric material layer 142 is located between the driving electrode 141 and the receiving electrode 143; the receiving electrode 143 is coupled to the reset sampling module 11. In fingerprint recognition applications, when a driving voltage Tx is applied to the driving electrode 141, the piezoelectric material layer 142 senses the voltage excitation and produces an inverse piezoelectric effect, emitting an ultrasonic signal outward. When the ultrasonic signal contacts the finger, it will be reflected by the finger, and the intensity of the ultrasonic wave reflected back to the piezoelectric material layer 142 by the valleys and ridges of the fingerprint is different. Then, a fixed voltage is applied to the driving electrode 141, and the piezoelectric material layer 142 can convert the ultrasonic signal into a voltage signal, which is stored in the storage capacitor C through the receiving electrode 143 to achieve sampling and storage of the detection signal. The position of the valleys and ridges in the fingerprint can be determined later by the voltage signal.

[0048] In some embodiments, Figure 6 FIG1 is a partial schematic diagram of another detection circuit provided by an embodiment of the present invention. Figure 6 As shown, the pre-configuration module 30 reuses at least one driver circuit 10, utilizing the driver circuit 10 to pre-configure the potential on the read signal line 20 coupled thereto. In other words, some of the multiple driver circuits 10 coupled to the same read signal line 20 are used to pre-configure that read signal line 20. With this arrangement, the circuit structure of the pre-configuration module 30 is identical to that of the driver circuit 10 used for detection in the detection circuit. Therefore, the configuration of the pre-configuration module 30 does not add any new process steps. Furthermore, the drive control of the pre-configuration module 30 can directly refer to the control method of the driver circuit 10. Pre-configuration of the read signal line 20 can be achieved by simply adjusting the timing of the control signal of the pre-configuration module 30.

[0049] In some embodiments, in the driving method provided by an embodiment of the present invention, in the preset stage: controlling the preconfiguration module 30 to turn on to output a preset signal to the read signal line 20 includes: controlling at least one drive circuit 10 to turn on to output a preset signal to the read signal line 20. Using the driving method provided by this embodiment, the read signal line 20 can be preconfigured using at least a portion of the drive circuit 10 during the preset stage. The circuit structure of the preconfiguration module 30 is identical to the circuit structure of the drive circuit 10 used for detection in the detection circuit, and the provision of the preconfiguration module 30 does not add any new process steps. Furthermore, the drive control of the preconfiguration module 30 can directly refer to the control method of the drive circuit 10. Preconfiguration of the read signal line 20 can be achieved by simply adjusting the timing of the control signal of the preconfiguration module 30.

[0050] In some embodiments, the working cycle of the detection circuit includes a preset phase and a detection phase. In the preset phase, at least one driving circuit 10 starts to output a preset signal to the read signal line 20. In the detection phase, at least some driving circuits 10 start to output a detection signal to the read signal line 20. In the detection phase, the working process of the driving circuit 10 outputting the detection signal can be referred to above. Figure 4 Related description in the embodiment. That is to say, in the preset stage, one driving circuit 10 can be controlled to be turned on, or two or more driving circuits 10 can be controlled to be turned on, or all driving circuits 10 can be controlled to be turned on, and the voltage signal output by the driving circuit 10 turned on in this stage is the preset signal. In the detection stage, some driving circuits 10 can be controlled to be turned on, or all driving circuits 10 can be controlled to be turned on, and the voltage signal output by the driving circuit 10 turned on in this stage is used as a detection signal for realizing detection; for example, in a fingerprint recognition application, the voltage signal output by the driving circuit 10 turned on in this stage is the detection signal for realizing fingerprint recognition detection.

[0051] The detection circuit provided in an embodiment of the present invention performs a preset phase before the detection phase. First, a preset signal is output to the read signal line 20 to pre-configure the potential on the read signal line 20. This can reduce the impact of the opening action of the detection switch coupled to the read signal line 20 on the potential on the read signal line 20 during the detection phase, thereby reducing the noise introduced into the detection signal and improving detection accuracy. In this embodiment, the pre-configuration module 30 reuses at least one drive circuit 10, and no new process steps are added when the detection circuit is manufactured. In addition, the drive control of the pre-configuration module 30 can directly refer to the control method of the drive circuit 10. Only the timing of the control signal of the pre-configuration module 30 needs to be adjusted to achieve the function of pre-configuring the read signal line 20.

[0052] In some embodiments, multiple driving circuits 10 are arranged into a driving circuit array, wherein the pre-configuration module 30 reuses part of the driving circuits 10. The driving circuits 10 reused as the pre-configuration module 30 are only used to perform the pre-configuration function in the preset stage and are no longer used for detection.

[0053] In other embodiments, multiple driving circuits 10 are arranged into a driving circuit array, wherein the pre-configuration module 30 reuses at least part of the driving circuits 10, and the driving circuits 10 that are reused as the pre-configuration module 30 are used to perform the pre-configuration function in the preset stage and are also used to perform the detection function in the detection stage.

[0054] In some embodiments, as Figure 6As shown, multiple driver circuits 10 are arranged into a driver circuit array. The driver circuit array includes multiple driver circuit rows 10H and multiple driver circuit columns 10L. The driver circuit rows 10H extend along a first direction x and are arranged along a second direction y. The driver circuit columns 10L extend along the second direction y and are arranged along the first direction x, with the first direction x and the second direction y intersecting. That is, multiple driver circuits 10 are arranged in each driver circuit row 10H, and multiple driver circuits 10 are arranged in each driver circuit column 10L. A read signal line 20 extends along the second direction y and is coupled to the multiple driver circuits 10 in a driver circuit column 10L. The driver circuit 10 includes a first driver circuit 10a. The driver circuit row 10H containing the first driver circuit 10a is multiplexed into a pre-configuration module 30. In this embodiment, it can also be understood that the pre-configuration module 30 includes multiple sub-configuration modules, each of which is used to pre-configure the potential on a read signal line 20. Each sub-configuration module includes at least one first driver circuit 10a.

[0055] Figure 6 FIG. 3 illustrates that the pre-configuration module 30 multiplexes one driving circuit row 10H. In other embodiments, the pre-configuration module 30 may multiplex two or more driving circuit rows 10H.

[0056] In one embodiment, Figure 7 A partial schematic diagram of another detection circuit provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the pre-configuration module 30 multiplexes two driver circuit rows 10H. For a single read signal line 20, during the pre-setting phase, two first driver circuits 10a belonging to the two driver circuit rows 10H can output a preset signal to the read signal line 20. In another embodiment, the pre-configuration module 30 multiplexes three driver circuit rows 10H. For a single read signal line 20, during the pre-setting phase, three first driver circuits 10a can output a preset signal to the read signal line 20. By multiplexing two or more driver circuit rows 10H, the pre-configuration module 30 can increase the number of first driver circuits 10a providing preset signals to the read signal line 20 during the pre-setting phase. This can increase the speed of pre-configuration of the read signal line 20 and reduce the time it takes for the read signal line 20 to reach a stable potential, thereby shortening the duty cycle of the detection circuit and improving detection efficiency.

[0057] In one embodiment, during the preset phase, the first driver circuit 10a starts outputting a preset signal to the coupled read signal line 20. During the detection phase, the first driver circuit 10a starts outputting a detection signal to the coupled read signal line 20. During the detection phase, at least some of the remaining driver circuits 10 in the driver circuit array, excluding the first driver circuit 10a, also correspondingly start outputting detection signals to the read signal line 20. In this embodiment, the first driver circuit 10a performs a preconfiguration function during the preset phase and also performs a detection function during the detection phase.

[0058] In another embodiment, during the preset phase, the first driver circuit 10a starts outputting a preset signal to the read signal line 20 coupled thereto. During the detection phase, the remaining driver circuits 10 in the driver circuit array, except for the first driver circuit 10a, each start outputting a detection signal to the read signal line 20. In this embodiment, the first driver circuit 10a performs the pre-configuration function only during the preset phase, while at least some of the remaining driver circuits 10 in the driver circuit array perform the detection function during the detection phase.

[0059] In some embodiments, a dummy driving circuit is further provided around the array of the driving circuit 10 for detection, wherein the driving circuit 10 for detection is a circuit that can perform a detection function in the detection stage. The dummy driving circuit has the same structure as the driving circuit 10 for detection, but the dummy driving circuit is not used for signal detection in the detection stage. When the detection circuit is manufactured, the problem of uneven etching caused by a sudden change in the density of the pattern in the same film layer will occur in the transistors of the dummy driving circuit. The setting of the dummy driving circuit can ensure that the characteristics of each transistor in the driving circuit 10 for detection are uniform. In some embodiments of the present invention, the pre-configuration module 30 reuses the original dummy driving circuit in the detection circuit, and uses the dummy driving circuit to pre-configure the read signal line 20. There is no need to add an additional driving circuit for use as the pre-configuration module 30, which can reduce the area occupied by the detection circuit as a whole.

[0060] In some embodiments, Figure 8 Another detection circuit diagram provided by an embodiment of the present invention is as follows: Figure 8As shown, the detection circuit also includes a detection shift circuit 60, which includes n cascaded shift registers 61, where n is a positive integer and n ≥ 2. The n cascaded shift registers 61 are sequentially a first-stage shift register 61_1, a second-stage shift register 61_2, a third-stage shift register 61_3, and so on to an n-th-stage shift register 61_n. The n shift registers 61 are respectively coupled to n drive circuit rows 10H. The detection shift circuit 60 is configured to drive the plurality of drive circuit rows 10 row by row in the second direction y. The drive circuit row 10H coupled to the first-stage shift register 61_1 is the first-stage drive circuit row 10H_1, and the drive circuit row 10H coupled to the n-th-stage shift register 61_n is the n-th-stage drive circuit row 10H_n. The pre-configuration module 30 reuses at least one driver circuit row 10H located on the side of the first-stage driver circuit row 10H_1 that is away from the n-stage driver circuit row 10H_n. The driver circuit rows 10H reused as the pre-configuration module 30 include multiple first driver circuits 10a. In this embodiment, the driver circuit rows 10H reused by the pre-configuration module 30 are not coupled to the detection shift circuit 60. Therefore, the driver circuit rows 10H reused by the pre-configuration module 30 only perform the function of presetting the potential of the read signal line 20 during the preset phase and do not participate in detection during the detection phase. This configuration allows the control of the pre-configuration module 30 and the control of the driver circuits 10 used for detection to be performed independently without interfering with each other, which helps simplify the control of the detection circuit.

[0061] In other embodiments, the detection circuit includes multiple driver circuit rows 10H arranged in the second direction y. At least one driver circuit row 10H is disposed on a side of the first-stage driver circuit row 10H_1 that is away from the n-stage driver circuit row 10H_n, and at least one driver circuit row 10H is disposed on a side of the n-stage driver circuit row 10H_n that is away from the first-stage driver circuit row 10H_1. The preconfiguration module 30 reuses at least one driver circuit row 10H located on a side of the first-stage driver circuit row 10H_1 that is away from the n-stage driver circuit row 10H_n. Furthermore, the preconfiguration module 30 reuses at least one driver circuit row 10H located on a side of the n-stage driver circuit row 10H_n that is away from the first-stage driver circuit row 10H_1. This embodiment utilizes two or more driver circuits 10 to simultaneously preconfigure a single read signal line 20. During the preconfiguration phase, the potential on the read signal line 20 is quickly charged to a desired state and the potential on the read signal line 20 is ensured to be stable.

[0062] In one embodiment of the present invention, the detection circuit includes multiple driver circuit rows 10H arranged in a second direction y. During the detection phase, the detection circuit is sequentially driven by the first-stage driver circuit row 10H_1 through the n-stage driver circuit row 10H_n. In other embodiments, the pre-configuration module 30 further reuses at least one driver circuit row 10H located on a side of the n-stage driver circuit row 10H_n that is away from the first-stage driver circuit row 10H_1.

[0063] like Figure 8 As shown, the detection circuit includes a read scan line 54 and a pre-scan control line 31. The drive circuit 10 is coupled to the read scan line 54, see Figure 4 As shown in the diagram and description, the read scan line 54 is used to control the working state of the third transistor T3. In the detection phase, the read scan line 54 provides an enable signal to control the conduction of the third transistor T3 to enable the read signal line 20 to read the electrical signal. The pre-configuration module 30 is coupled to the pre-scan control line 31, and the pre-scan control line 31 is used to control the working state of the pre-configuration module 30. In the preset phase, the pre-scan control line 31 provides an enable signal to control the pre-configuration module 30 to pre-configure the potential on the read signal line 20. In this embodiment, the pre-configuration module 30 multiplexes at least one drive circuit 10, and at least one read scan line 54 is multiplexed as the pre-scan control line 31. In other words, the coupling method of the pre-scan control line 31 and the drive circuit in the pre-configuration module 30 is the same as the coupling method of the read scan line 54 and the drive circuit 10, except that Figure 8 In the embodiment, the read scan line 54 coupled to the pre-configuration module 30 is not coupled to the shift register 61 in the detection shift circuit 60 .

[0064] Figure 8 In this embodiment, the pre-configuration module 30 can also be understood as comprising multiple sub-configuration modules, each of which comprises at least one first drive circuit 10a and is coupled to at least one read signal line 20. The multiple sub-configuration modules are coupled to the same pre-scan control line 31. Using a single pre-scan control line 31 to control the multiple sub-configuration modules simplifies the control of the pre-configuration module 30, reduces wiring in the detection circuit, and saves space.

[0065] In other embodiments, the preconfiguration module 30 reuses all the detection driver circuits 10. During the preconfiguration phase, all the detection driver circuits 10 operate to preconfigure the coupled read signal lines 20, meaning that during this phase, all the detection driver circuits 10 perform the preconfiguration function. During the detection phase, all the detection driver circuits 10 operate to output detection signals to the read signal lines 20, meaning that during this phase, all the detection driver circuits 10 perform the detection function. In this embodiment, by utilizing the detection driver circuits 10 to perform the preconfiguration function, the read signal lines 20 can be preconfigured without adding additional circuit structures, simplifying the detection circuit structure and saving space.

[0066] In some embodiments, Figure 9 Another detection circuit diagram provided by an embodiment of the present invention is as follows: Figure 9 As shown, the pre-configuration module 30 includes at least one fourth transistor T4. A first electrode of the fourth transistor T4 is coupled to the preset signal terminal YD, which is used to provide a preset signal. A second electrode of the fourth transistor T4 is coupled to the read signal line 20, and a control terminal of the fourth transistor T4 is coupled to the pre-scan control line 31. Figure 9 As shown in FIG. , a fourth transistor T4 is provided for each read signal line 20. During the preset phase, the pre-scan control line 31 provides an enable signal to turn on the fourth transistor T4. The preset signal provided by the preset signal terminal YD is then written to the read signal line 20 to pre-configure the potential on the read signal line 20. This reduces the effect of the opening of the detection switch 41 coupled to the read signal line 20 on the potential on the read signal line 20, thereby reducing noise introduced into the detection signal and improving detection accuracy.

[0067] In some embodiments, the preset signal terminal YD is configured to provide a preset signal with a magnitude close to the voltage of the signal read by the read signal line 20 during the detection phase.

[0068] In some embodiments, the magnitude of the preset signal is Y0, where 0V ≤ Y0 ≤ 5V. During the operation of the driver circuit 10, the bias voltage provided by the first voltage signal line 52 is V1, and Y0 ≤ V1-Vth, where Vth is the threshold voltage of the transistors in the driver circuit 10. In the embodiments of the present invention, the magnitude of the preset signal is set taking into account the operation of the driver circuit 10, ensuring that the preset signal can pre-charge the read signal line 20, thereby reducing the impact of the opening action of the detection switch 41 coupled to the read signal line 20 on the potential on the read signal line 20. Furthermore, the magnitude of the preset signal does not need to be set too large, which can reduce power consumption.

[0069] exist Figure 9In this embodiment, each fourth transistor T4 corresponds to a sub-configuration module. The pre-configuration module 30 includes multiple sub-configuration modules. Each sub-configuration module is coupled to at least one read signal line 20, and multiple sub-configuration modules are coupled to the same pre-scanning control line 31. In other words, a single pre-scanning control line 31 controls multiple fourth transistors T4. This configuration simplifies the control of the pre-configuration module 30, reduces wiring in the detection circuit, and saves space.

[0070] In some embodiments, another driving method provided by an embodiment of the present invention includes: controlling the working cycle of the detection circuit to include a preset phase and a detection phase; wherein,

[0071] In the preset stage, the pre-scan control line 31 is controlled to provide an enable signal to the pre-configuration module 30 to control the pre-configuration module 30 to start. After the pre-configuration module 30 is turned on, the preset signal is output to the read signal line 20.

[0072] During the detection phase, the read scan line 54 is controlled to provide an enable signal to the driving circuit 10 to control the driving circuit 10 to be turned on. After the driving circuit 10 is turned on, the driving circuit 10 outputs a detection signal to the read signal line 20 .

[0073] In the embodiment of the present invention, the pulse width of the enable signal provided by the pre-scan control line 31 is greater than the pulse width of the enable signal provided by the read scan line 54. This arrangement ensures that the read signal line 20 is fully charged during the pre-set phase, so that the potential on the read signal line 20 is relatively stable after the pre-set phase.

[0074] Figure 10 A working timing diagram of the detection circuit provided by the embodiment of the present invention, such as Figure 10 As shown, the working cycle of the detection circuit includes a preset phase S1 and a detection phase S2.

[0075] In the preset stage S1 , the pre-scan control line 31 provides an enable signal to control the pre-configuration module 30 to start. After starting, the pre-configuration module 30 outputs a preset signal to the read signal line 20 to pre-configure the potential on the read signal line 20 .

[0076] After the preset phase S1 , the detection phase S2 is executed. In the detection phase S2 , the read scan line 54 provides an enable signal to control the drive circuit 10 to operate, and the drive circuit 10 outputs a detection signal to the read signal line 20 . Figure 10 FIG. 5 shows the timing of three sequentially arranged readout scan lines 54 , which respectively control three drive circuit rows 10H. Figure 10FIG2 illustrates the timing of the first branch control line CKH1, which controls the detection switches 41 in the multiplexing circuits 40. During the period when each read scan line 54 provides an enable signal, the first branch control line CKH1 also provides an enable signal to control the output of the detection signal read by the read signal line 20 to the subsequent data processing circuit.

[0077] Depend on Figure 10 It can be seen that the pulse width of the enable signal provided by the pre-scan control line 31 is greater than the pulse width of the enable signal provided by the read scan line 54. This arrangement ensures that the read signal line 20 is fully charged in the preset stage S1, so that the potential on the read signal line 20 is relatively stable after the preset stage S1.

[0078] Combine Figure 8 In the embodiment, Figure 8 In this embodiment, the pre-configuration module 30 reuses a drive circuit row 10H, and the drive circuit row 10H reused by the pre-configuration module 30 is not coupled to the detection shift circuit 60. This allows for independent control of the pre-configuration module 30 and the drive circuit 10 corresponding to the detection. The pulse width of the enable signal provided by the pre-scan control line 31 during the preset phase is controlled to be greater than the pulse width of the enable signal provided by the read scan line 54 during the detection phase. The enable signal provided by the pre-scan control line 31 controls the conduction of the third transistor T3 in the first drive circuit 10a, while the enable signal provided by the read scan line 54 controls the conduction of the third transistor T3 in the drive circuit 10 used for detection. By increasing the pulse width of the enable signal provided by the pre-scan control line 31, the conduction time of the third transistor T3 in the first drive circuit 10a can be increased, ensuring that the read signal line 20 is fully charged, so that the read signal line 20 reaches a stable potential after the preset phase S1.

[0079] In some embodiments, Figure 11 Another detection circuit diagram provided by an embodiment of the present invention is as follows: Figure 11 As shown, the detection circuit further includes at least one initialization module 70, which is coupled to the read signal line 20. The initialization module 70 is configured to initialize the read signal line 20 before the pre-configuration module 30 is enabled. The operation cycle of the detection circuit provided in this embodiment also includes an initialization phase, followed by a pre-configuration phase.

[0080] In some embodiments, the driving method provided by an embodiment of the present invention further includes: controlling the working cycle of the detection circuit to include an initialization phase; in the initialization phase, controlling the initialization module 70 to turn on to reset the read signal line 20; wherein, the initialization phase is executed before the detection circuit is controlled to execute the preset phase.

[0081] In conventional designs, after a read signal line 20 completes a signal read or a detection cycle, it maintains a certain potential, and the potentials on different read signal lines 20 may differ. In the embodiments of the present invention, the initialization module 70, after being activated, can reset the read signal line 20. Specifically, the read signal line 20 is discharged during the initialization phase, ensuring that the potentials on each read signal line 20 are substantially consistent before the pre-setting phase. Therefore, when each read signal line 20 is pre-configured in the same time period, the charging speeds on each read signal line 20 are substantially the same, and each read signal line 20 can be charged to substantially the same potential. This ensures that the potentials on the read signal lines 20 during the detection phase are substantially affected by the opening of the detection switch 41, reducing noise differences in the detection signals on different read signal lines 20 and improving detection accuracy.

[0082] In some embodiments, Figure 12 Another detection circuit diagram provided by an embodiment of the present invention is shown. Figure 13 This is another working timing diagram of the detection circuit provided by the embodiment of the present invention. Figure 12 As shown, the initialization module 70 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is coupled to the initialization voltage terminal SD, which is used to provide an initialization signal. A second electrode of the fifth transistor T5 is coupled to the read signal line 20. A control terminal of the fifth transistor T5 is coupled to the initialization control line 71.

[0083] like Figure 13 As shown, the working cycle of the detection circuit also includes an initialization phase S0. After the initialization phase S0 is completed, the pre-set phase S1 is executed. During the initialization phase S0, the initialization control line 71 provides an enable signal to control the conduction of the fifth transistor T5. The initialization voltage terminal SD then writes the initialization signal to the read signal line 20 to reset the potential on the read signal line 20. This ensures that the potentials on each read signal line 20 are substantially consistent before the pre-set phase. Therefore, when each read signal line 20 is pre-configured in the same time period, the charging speeds on each read signal line 20 are substantially the same, and each read signal line 20 can be charged to substantially the same potential. This ensures that the potentials on the read signal lines 20 during the detection phase are substantially affected by the opening action of the detection switch 41. This reduces the noise differences in the detection signals on different read signal lines 20 and improves detection accuracy.

[0084] like Figure 12As shown, the initialization module 70 includes a first capacitor C1. A first plate of the first capacitor C1 is coupled to the read signal line 20, and a second plate of the first capacitor C1 is coupled to the initialization voltage terminal SD. In this embodiment, the first capacitor C1 is configured to stabilize the potential on the read signal line 20 to which it is coupled, so that the potential on the read signal line 20 remains stable after the initialization phase.

[0085] like Figure 12 As shown, the control terminals of the multiple initialization modules 70 are coupled to the same initialization control line 71. During the initialization phase, the multiple initialization modules 70 are controlled by one initialization control line 71, which can reduce the wiring in the detection circuit and save space.

[0086] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the detection circuit provided by any embodiment of the present invention. Figure 14 A schematic diagram of a display device provided by an embodiment of the present invention, such as Figure 14 As shown, the display device includes a display area AA, and the display area AA includes a detection area JA. The position of the detection area JA in the display area AA is only schematically shown. The embodiment of the present invention does not impose any limitation on the shape, size, etc. of the detection area JA. Figure 14 The detection circuit is not shown in the figure. In the embodiment of the present invention, the detection circuit is located in the module structure of the display device and overlaps with the detection area JA. In some embodiments, the detection area JA is a fingerprint recognition area, and the detection circuit is used to implement the fingerprint recognition function of the display device.

[0087] The display device provided by the embodiment of the present invention can be any device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader, a television, a smart watch, or the like.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A detection circuit, characterized in that: The detection circuit includes a plurality of driving circuits and a plurality of read signal lines, and one read signal line is coupled to the plurality of driving circuits; The detection circuit further includes a pre-configuration module, the pre-configuration module is coupled to the read signal line, and the pre-configuration module is used to output a preset signal to the read signal line to pre-configure the potential on the read signal line; The detection circuit includes a pre-scan control line, the pre-configuration module is coupled to the pre-scan control line, the pre-configuration module includes multiple sub-configuration modules, one sub-configuration module is coupled to at least one read signal line, and multiple sub-configuration modules are coupled to the same pre-scan control line.

2. The detection circuit according to claim 1, characterized in that The driving circuit includes a reset sampling module, a driving module, a control module and a detection unit; The reset sampling module is coupled to the detection unit, and is used to reset the detection unit. The reset sampling module is also used to receive and store the electrical signal fed back by the detection unit. The driving module is coupled to the reset sampling module, and the driving module is used to read the electrical signal stored in the reset sampling module and amplify the electrical signal; The control module is coupled to the driving module and the read signal line respectively, and the control module is used to provide the electrical signal amplified by the driving module to the read signal line.

3. The detection circuit according to claim 2, characterized in that: The reset sampling module includes a first transistor and a storage capacitor, the driving module includes a second transistor, and the control module includes a third transistor; The control end of the first transistor is coupled to the first control signal line, the first electrode of the first transistor is coupled to the first voltage signal line, and the second electrode of the first transistor is coupled to the detection unit; The first plate of the storage capacitor is coupled to the detection unit, and the second plate of the storage capacitor is coupled to the second voltage signal line; The control terminal of the second transistor is coupled to the first plate of the storage capacitor, the first electrode of the second transistor is coupled to the second plate of the storage capacitor, and the second electrode of the second transistor is coupled to the first electrode of the third transistor; A control electrode of the third transistor is coupled to a read scan line, and a second electrode of the third transistor is coupled to the read signal line.

4. The detection circuit according to claim 2, characterized in that: The detection unit includes a stacked driving electrode, a piezoelectric material layer and a receiving electrode, wherein the piezoelectric material layer is located between the driving electrode and the receiving electrode; and the receiving electrode is coupled to the reset sampling module.

5. The detection circuit according to claim 1, characterized in that: The pre-configuration module reuses at least one of the driving circuits.

6. The detection circuit according to claim 5, characterized in that: The working cycle of the detection circuit includes a preset phase and a detection phase; wherein, In the preset stage, at least one of the driving circuits is turned on to output the preset signal to the read signal line; During the detection phase, at least part of the driving circuits are turned on to output detection signals to the read signal lines.

7. The detection circuit according to claim 5, characterized in that: A plurality of drive circuits are arranged in a drive circuit array, the drive circuit array comprising a plurality of drive circuit rows and a plurality of drive circuit columns, the drive circuit rows extending along a first direction and arranged along a second direction, the drive circuit columns extending along the second direction and arranged along the first direction, the first direction and the second direction intersecting each other; the read signal line extending along the second direction and coupled to one of the drive circuit columns; The pre-configuration module multiplexes at least one of the drive circuit rows.

8. The detection circuit according to claim 6, characterized in that: The detection circuit further includes a detection shift circuit, which includes n cascaded shift registers, where n is a positive integer and n≥2; the n shift registers are respectively coupled to n rows of the driving circuits; wherein, The driving circuit row coupled to the first-stage shift register is a first-stage driving circuit row, and the driving circuit row coupled to the n-th-stage shift register is an n-stage driving circuit row; The pre-configuration module multiplexes at least one of the drive circuit rows located on a side of the first-stage drive circuit rows away from the n-stage drive circuit rows, and / or the pre-configuration module multiplexes at least one of the drive circuit rows located on a side of the n-stage drive circuit rows away from the first-stage drive circuit rows.

9. The detection circuit according to claim 5, characterized in that: The detection circuit includes a read scan line, and the driving circuit is coupled to the read scan line; wherein, At least one of the read scan lines is multiplexed as the pre-scan control line.

10. The detection circuit according to claim 1, characterized in that: The pre-configuration module includes at least one fourth transistor, a first electrode of the fourth transistor is coupled to a preset signal terminal, and a second electrode of the fourth transistor is coupled to the read signal line; the preset signal terminal is used to provide the preset signal.

11. The detection circuit according to claim 1, characterized in that: The detection circuit includes a read scan line; one read scan line is coupled to a plurality of the driving circuits; The pulse width of the enable signal provided by the pre-scan control line is greater than the pulse width of the enable signal provided by the read scan line.

12. The detection circuit according to claim 1, characterized in that: The detection circuit further includes at least one initialization module, which is coupled to the read signal line; the initialization module is configured to initialize the read signal line before the pre-configuration module is turned on.

13. The detection circuit according to claim 12, characterized in that: The initialization module includes a fifth transistor, a first electrode of the fifth transistor is coupled to the initialization voltage terminal, and a second electrode of the fifth transistor is coupled to the read signal line.

14. The detection circuit according to claim 13, characterized in that: The initialization module includes a first capacitor, a first plate of the first capacitor is coupled to the read signal line, and a second plate of the first capacitor is coupled to the initialization voltage terminal.

15. The detection circuit according to claim 12, characterized in that: The detection circuit further includes an initialization control line, and control terminals of a plurality of the initialization modules are coupled to the same initialization control line.

16. The detection circuit according to claim 1, characterized in that: The detection circuit further includes a multiplexing circuit, and at least two of the read signal lines are connected to the same multiplexing circuit.

17. The detection circuit according to claim 1, characterized in that: The magnitude of the preset signal is Y0, where 0V≤Y0≤5V.

18. A method for driving a detection circuit, characterized in that: The detection circuit includes a plurality of driving circuits and a plurality of read signal lines, wherein one read signal line is coupled to the plurality of driving circuits; the detection circuit also includes a pre-configuration module, wherein the read signal line is coupled to the pre-configuration module; the detection circuit includes a pre-scan control line, wherein the pre-configuration module is coupled to the pre-scan control line, and wherein the pre-configuration module includes a plurality of sub-configuration modules, wherein one sub-configuration module is coupled to at least one read signal line, and a plurality of sub-configuration modules are coupled to the same pre-scan control line; the driving method includes: controlling a working cycle of the detection circuit to include a preset phase and a detection phase; In the preset stage, controlling the pre-configuration module to start up so as to output a preset signal to the read signal line includes: controlling the pre-scan control line to provide an enable signal to the pre-configuration module so as to control the pre-configuration module to start up; In the detection phase, at least a portion of the driving circuit is controlled to be turned on to output a detection signal to the read signal line.

19. The driving method according to claim 18, wherein: The pre-configuration module multiplexes at least one of the driving circuits; Controlling the pre-configuration module to be turned on to output a preset signal to the read signal line includes: controlling at least one of the driving circuits to be turned on to output the preset signal to the read signal line.

20. The driving method according to claim 18, wherein: The detection circuit includes a read scan line; one read scan line is coupled to a plurality of the driving circuits; Controlling at least part of the driving circuit to turn on to output a detection signal to the read signal line includes controlling the read scan line to provide an enable signal to the driving circuit to control the driving circuit to turn on, The pulse width of the enable signal provided by the pre-scan control line is greater than the pulse width of the enable signal provided by the read scan line.

21. The driving method according to claim 18, wherein: The detection circuit further includes an initialization module, and the read signal line is coupled to the initialization module; The driving method further includes: controlling the working cycle of the detection circuit to include an initialization phase; in the initialization phase, controlling the initialization module to be turned on to reset the read signal line; wherein the initialization phase is performed before controlling the detection circuit to perform the preset phase.

22. A display device, characterized in that: The detection circuit comprises the detection circuit according to any one of claims 1 to 17.

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