Control device and display device

Abstract

A control device and a display device. The control device includes a control module. A first pin of the control module provides a control signal. A second pin of the control module provides a clock signal. A third pin of the control module provides a data signal, and the data signal includes display data and configuration setting data. A fourth pin of the control module provides a vertical synchronization signal. During an enable period of the vertical synchronization signal, the control module provides a first-level control signal, a clock signal, and a data signal including configuration setting data to the display device, so that the display module performs configuration settings based on the control signal, clock signal, and configuration setting data. During a disable period of the vertical synchronization signal, the control module provides a second-level control signal, a clock signal, and a data signal including display data to the display device, so that the display module performs normal display based on the control signal, clock signal, and display data.

Description

Technical Field

[0001] The present invention relates to a control device, and more particularly to a control device and a display device for reducing the number of pins used by devices. Background Art

[0002] Generally speaking, some display devices require a serial peripheral interface (SPI) to set the display device's internal registers to adjust the display device's display characteristics (such as resolution). However, the display device controller uses three pins to provide the SPI control signal, SPI clock signal, and SPI data signal, respectively, so that the display device can set and adjust the display characteristics accordingly. Since setting the display device's display characteristics occupies three pins of the display device controller, the controller's functionality is limited, reducing its usability.

[0003] Therefore, how to effectively reduce the number of used pins of the controller is an important issue at present. Summary of the Invention

[0004] The present invention provides a control device and a display device, which effectively reduce the number of used pins of the device so that the free pins can be used for function expansion and maintain normal display function, thereby increasing convenience in use.

[0005] The present invention provides a control device suitable for a display device. The control device includes a control module. The control module has a first pin, a second pin, a third pin, and a fourth pin. The first pin of the control module provides a control signal. The second pin of the control module provides a clock signal. The third pin of the control module provides a data signal, and the data signal includes display data and configuration setting data. The fourth pin of the control module provides a vertical synchronization signal. During the enabling period of the vertical synchronization signal, the control module provides a first-level control signal, a clock signal, and a data signal including configuration setting data to the display device, so that the display module performs configuration settings according to the control signal, the clock signal, and the configuration setting data. During the disabling period of the vertical synchronization signal, the control module provides a second-level control signal, a clock signal, and a data signal including display data to the display device, so that the display module performs normal display according to the control signal, the clock signal, and the display data.

[0006] The present invention provides a display device, comprising a control module and a display module. The control module has a first pin, a second pin, a third pin, and a fourth pin. The first pin of the control module provides a control signal, the second pin of the control module provides a clock signal, and the third pin of the control module provides a data signal, wherein the data signal includes display data and configuration setting data. The display module has a first pin, a second pin, a third pin, a fourth pin, a fifth pin, and a sixth pin. The first pin of the display module is coupled to the first pin of the control module. The second and third pins of the display module are coupled to the second pin of the control module. The fourth and fifth pins of the display module are coupled to the third pin of the control module. The sixth pin of the display module is coupled to the fourth pin of the control module. During the enable period of the vertical synchronization signal, the control module provides a control signal of a first level, a clock signal, and a data signal including configuration setting data to the display module, so that the display module performs configuration settings according to the control signal, the clock signal, and the configuration setting data. During the disable period of the vertical synchronization signal, the control module provides a second level control signal, a clock signal and a data signal including display data to the display module, so that the display module performs normal display according to the control signal, the clock signal and the display data.

[0007] The control device and display device of the present invention provide a control signal via a first pin of the control module, a clock signal via a second pin of the control module, and a data signal via a third pin of the control module. The data signal includes display data and configuration data. During an enabled period of a vertical synchronization signal, the control module provides a first-level control signal, a clock signal, and a data signal including the configuration data to the display module (display device), causing the display module to perform configuration settings based on the control signal, clock signal, and configuration data. During a disabled period of the vertical synchronization signal, the control module provides a second-level control signal, clock signal, and a data signal including the display data to the display module (display device), causing the display module (display device) to perform normal display based on the control signal, clock signal, and display data. Furthermore, the second and third pins of the display module can share the second pin of the control module, and the fourth and fifth pins of the display module can share the third pin of the control module. This effectively reduces the number of used pins of the control module, allowing the free pins of the control module to expand its functionality while maintaining the normal display function of the display module, thereby increasing ease of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a waveform diagram of a vertical synchronization signal and a horizontal synchronization signal according to an embodiment of the present invention.

[0010] Figure 3 for Figure 2 Waveform diagram of a portion of the horizontal synchronization signal, control signal, clock signal, data signal, and data display indication signal.

[0011] Figure 4 for Figure 2 Another part of the horizontal synchronization signal, the control signal, the clock signal, the data signal, and the waveform diagram of the data display indication signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] 100: Display device

[0014] 110: Control module

[0015] 111,131: first pin

[0016] 112,132: Second pin

[0017] 113,133: Third pin

[0018] 114,134: fourth pin

[0019] 115,135: Fifth pin

[0020] 116,136: Pin 6

[0021] 130: Display module

[0022] 137: Pin 7

[0023] 138: Pin 8

[0024] CS: control signal

[0025] CLK: clock signal

[0026] DAT: data signal

[0027] VSYNC: vertical synchronization signal

[0028] HSYNC: horizontal synchronization signal

[0029] DE: Data display indication signal

[0030] TF: Picture duration

[0031] TE: Enable period

[0032] TD: Disabled period

[0033] TH1, TH2: horizontal synchronization period

[0034] D: Display data

[0035] INV: Invalid data

[0036] CSD: Configuration Setting Data DETAILED DESCRIPTION

[0037] In the various embodiments listed below, the same reference numerals will be used to represent the same or similar devices or components.

[0038] Figure 1 is a schematic diagram of a display device according to an embodiment of the present invention. Figure 1 The display device 100 may include a control module 110 and a display module 130. In this embodiment, the control module 110 is, for example, a microcontroller (MCU), a microprocessor (microprocessor), or a central processing unit (CPU), and the display module 130 is, for example, a liquid crystal display (LCD).

[0039] The control module 110 may have at least a first pin 111 , a second pin 112 , a third pin 113 , a fourth pin 114 , a fifth pin 115 and a sixth pin 116 .

[0040] A first pin 111 of the control module 110 (e.g., a control signal pin of a serial peripheral interface (SPI)) provides a control signal CS. A second pin 112 of the control module 110 (e.g., a clock signal pin of a display interface) provides a clock signal CLK. A third pin 113 of the control module 110 (e.g., a data signal pin of a display interface) provides a data signal DAT. The data signal DAT includes display data and configuration data. A fourth pin 114 of the control module 110 (e.g., a vertical synchronization signal pin of a display interface) provides a vertical synchronization signal VSYNC. A fifth pin 115 of the control module 110 (e.g., a horizontal synchronization signal pin of a display interface) provides a horizontal synchronization signal HSYNC. A sixth pin 116 of the control module 110 (e.g., a data display indication signal pin of a display interface) provides a data display indication signal DE.

[0041] The display module 130 may have at least a first pin 131 , a second pin 132 , a third pin 133 , a fourth pin 134 , a fifth pin 135 , a sixth pin 136 , a seventh pin 137 and an eighth pin 138 .

[0042] A first pin 131 of the display module 130 (e.g., an SPI control signal pin) is coupled to the first pin 111 of the control module 110 to receive a control signal CS. A second pin 132 of the display module 130 (e.g., an SPI clock signal pin) and a third pin 133 of the display module 130 (e.g., a display interface clock signal pin) are coupled to the second pin 112 of the control module 110 to receive a clock signal CLK. A fourth pin 134 of the display module 130 (e.g., an SPI data signal pin) and a fifth pin 135 of the display module 130 (e.g., a display interface clock signal pin) are coupled to the third pin 113 of the control module 110 to receive a data signal DAT.

[0043] The sixth pin 136 of the display module 130 (e.g., a vertical synchronization signal pin of the display interface) is coupled to the fourth pin 114 of the control module 110 to receive the vertical synchronization signal VSYNC. The seventh pin 137 of the display module 130 (e.g., a horizontal synchronization signal pin of the display interface) is coupled to the fifth pin 115 of the control module 110 to receive the horizontal synchronization signal HSYNC. The eighth pin 138 of the display module 130 (e.g., a data display indication signal pin of the display interface) is coupled to the sixth pin 116 of the control module 110 to receive the data display indication signal DE.

[0044] During the enable period of the vertical synchronization signal VSYNC, the control module 110 provides a control signal CS at a first level, a clock signal CLK, and a data signal DAT including configuration data to the display module 130, so that the display module 130 can be configured according to the control signal CS, the clock signal CLK, and the configuration data. In this embodiment, during the enable period of the vertical synchronization signal VSYNC, the control signal CS can serve as an SPI control signal, the clock signal CLK can serve as an SPI clock signal, and the data signal DAT can serve as an SPI data signal. Furthermore, the vertical synchronization signal VSYNC in this embodiment is, for example, negative-edge triggered, meaning that during the enable period of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a low logic level, but the embodiments of the present invention are not limited thereto. In other embodiments, the vertical synchronization signal VSYNC can also be positive-edge triggered, meaning that during the enable period of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a high logic level.

[0045] For example, the first pin 111 of the control module 110 can provide a control signal CS of a first level (e.g., a low logic level), the second pin 112 of the control module 110 can provide a clock signal CLK, and the third pin 113 of the control module 110 can provide a data signal DAT including configuration setting data to the display module 130.

[0046] At this time, the first pin 131 of the display module 130 receives a control signal CS at a first level (e.g., a low logic level), the second pin 132 of the display module 130 receives a clock signal CLK, and the fourth pin 134 of the display module 130 receives a data signal DAT including configuration data. The display module 130 can then be configured based on the control signal CS at the first level (e.g., a low logic level), the clock signal CLK, and the configuration data of the data signal DAT.

[0047] In this embodiment, the configuration data includes initial settings such as the resolution and image format of the display module 130, but the present invention is not limited thereto. For example, the display module 130 can use the configuration data of the data signal DAT to configure internal registers of the display module 130 so that the display module 130 can display a corresponding display image according to the set resolution and image format.

[0048] On the other hand, during the enabled period of the vertical synchronization signal VSYNC, the sixth pin 116 of the control module 110 may provide, for example, a data display indication signal DE at a low logic level (e.g., during the disabled period of the data display indication signal DE). At this time, the third pin 133 of the display module 130 receives the clock signal CLK, the fifth pin 135 of the display module 130 receives the data signal DAT including the configuration data, and the eighth pin 138 of the display module 130 receives the data display indication signal DE at a low logic level. Because the data display indication signal DE is at a low logic level, indicating the disabled period of the data display indication signal DE, the display module 130 ignores the clock signal CLK received by the third pin 133 of the display module 130 and the data signal DAT including the configuration data received by the fifth pin 135 of the display module 130. In other words, the display module 130 does not display the data signal DAT including the configuration data.

[0049] During the period when the vertical synchronization signal VSYNC is disabled, the control module 110 provides the control signal CS at the second level, the clock signal CLK, and the data signal DAT including display data to the display module 130, so that the display module 130 displays the display data normally according to the control signal CS, the clock signal CLK, and the display data. In this embodiment, during the period when the vertical synchronization signal VSYNC is disabled, the clock signal CLK can serve as the clock signal of the display interface, and the data signal DAT can serve as the data signal of the display interface. Furthermore, during the period when the vertical synchronization signal VSYNC is disabled, the vertical synchronization signal VSYNC is, for example, at a high logic level.

[0050] For example, the first pin 111 of the control module 110 may provide a control signal CS of a second level (e.g., a high logic level), the second pin 112 of the control module 110 may provide a clock signal CLK, and the third pin 113 of the control module 110 may provide a data signal DAT including display data.

[0051] At this time, the first pin 131 of the display module 130 receives the control signal CS at the second level, the second pin 132 of the display module 130 receives the clock signal CLK, and the fourth pin 134 of the display module 130 receives the data signal DAT including display data. Because the control signal CS is at a high logic level, the display module 130 ignores the clock signal CLK received by the second pin 132 of the display module 130 and the data signal DAT including display data received by the fourth pin 134 of the display module 130. In other words, the display module 130 does not configure or set the internal registers.

[0052] On the other hand, during the period when the vertical synchronization signal VSYNC of the display module 130 is disabled, the sixth pin 116 of the control module 110 can provide, for example, a data display indication signal DE at a high logic level (e.g., during the period when the data display indication signal DE is enabled). At this time, the third pin 133 of the display module 130 receives the clock signal CLK, the fifth pin 135 of the display module 130 receives the data signal DAT including display data, and the eighth pin 138 of the display module 130 receives the data display indication signal DE at a high logic level. The display module 130 can then perform normal display based on the data display indication signal DE at a high logic level, the clock signal CLK, and the data signal DAT including display data. That is, the display module 130 can display the data signal DAT including display data via the clock signal CLK during the period when the data display indication signal DE is enabled.

[0053] In this embodiment, each enabled period of the vertical synchronization signal VSYNC includes several scanning lines, and each of these scanning lines may correspond to a horizontal synchronization period of the horizontal synchronization signal HSYNC. That is, the enabled period of the vertical synchronization signal VSYNC may include multiple horizontal synchronization periods of the horizontal synchronization signal HSYNC. In addition, each scanning line may have a corresponding number of clock pulses of the clock signal CLK based on the resolution of the display module 130. That is, each horizontal synchronization period includes multiple clock pulses of the clock signal CLK. Furthermore, the number of clock pulses of the clock signal CLK for each scanning line may vary depending on the resolution of the display module 130.

[0054] For example, assuming the display module 130 has a resolution of 640x480, each scan line has at least 640 clock pulses. That is, each horizontal synchronization period includes 640 clock pulses of the clock signal CLK. If the vertical synchronization signal VSYNC is enabled for 10 scan lines, then there will be 6,400 (640*10) clock pulses of the clock signal CLK during the vertical synchronization signal VSYNC enable period. These 6,400 clock pulses can be used as the SPI clock signal. In this way, the display module 130 can use the configuration setting data of the data signal DAT to configure the internal register configuration of the display module 130 during these 6,400 clock pulses.

[0055] Furthermore, if the vertical synchronization signal VSYNC is enabled for two scan lines, then 1,280 (640*2) clock pulses of the clock signal CLK will be generated during the VSYNC enable period. These 1,280 clock pulses can be used as the SPI clock signal. The same applies to the rest of the clock signal. The 640x480 resolution of the display module 130 described above is merely an example embodiment of the present invention, and the present invention is not limited thereto. Users can adjust the number of scan lines included in the VSYNC enable period, i.e., the number of HSYNC horizontal synchronization periods included in the VSYNC enable period, as needed.

[0056] Furthermore, the first level of the control signal CS and the second level of the control signal CS can be complementary. For example, when the first level of the control signal CS is a low logic level, the second level of the control signal CS is a high logic level, as in the aforementioned embodiment. However, the present invention is not limited thereto. In some embodiments, when the first level of the control signal CS is a high logic level, the second level of the control signal CS is a low logic level.

[0057] From the above description of the embodiment, it can be seen that the second pin 132 (e.g., the SPI clock signal pin) and the third pin 133 (e.g., the display interface clock signal pin) of the display module 130 of this embodiment can share the second pin 112 (e.g., the display interface clock pin) of the control module 110, and the fourth pin 134 (e.g., the SPI data signal pin) and the fifth pin 135 (e.g., the display interface data signal pin) of the display module 130 can share the third pin 113 (e.g., the display interface data signal pin) of the control module 110. Furthermore, the control module 110 provides corresponding control signals, clock signals, and data signals to the display module 130 during the enable and disable periods of the vertical synchronization signal VSYNC, respectively, so that the display module 130 can perform configuration settings or perform normal display. In this way, the number of pins used by the control module 110 can be effectively reduced, that is, the number of pins used by the control module 110 to generate the SPI clock signal and the SPI data signal can be reduced, thereby achieving a simplified serial peripheral interface (SSPI) for use in the display device 100. In addition, since the number of pins used by the control module 110 is reduced, the control module 110 can have free pins to expand the function of the control module 110 and maintain the normal display function of the display module 130, thereby increasing the convenience of use.

[0058] exist Figure 1 In the figure, the third pin 113 of the control module 110 and the fifth pin 115 of the display module 130 are shown as one. However, in practice, the display device 100 may have multiple data signal lines, that is, the control module 110 and the display module 130 may have multiple data signal pins, of which the third pin 113 of the control module 110 and the fifth pin 135 of the display module 130 are one of the aforementioned data signal pins. In addition, different display devices 100 may have different numbers of data signal lines.

[0059] For example, when the display device 100 has 8 data signal lines, the control module 110 and the display module 130 may have 8 data signal pins, wherein the third pin 113 of the control module 110 and the fifth pin 135 of the display module 130 may be one of the 8 data signal pins. When the display device 100 has 16 data signal lines, the control module 110 and the display module 130 may have 16 data signal pins, wherein the third pin 113 of the control module 110 and the fifth pin 135 of the display module 130 may be one of the 16 data signal pins. When the display device 100 has 24 data signal lines, the control module 110 and the display module 130 may have 24 data signal pins, wherein the third pin 113 of the control module 110 and the fifth pin 135 of the display module 130 may be one of the 24 data signal pins. The same applies to the rest.

[0060] Figure 2 FIG. 4 is a waveform diagram of a vertical synchronization signal and a horizontal synchronization signal according to an embodiment of the present invention. Figure 3 for Figure 2 Waveform diagram of a portion of the horizontal synchronization signal, control signal, clock signal, data signal, and data display indication signal. Figure 4 for Figure 2 Another part of the horizontal synchronization signal, the control signal, the clock signal, the data signal, and the waveform diagram of the data display indication signal.

[0061] exist Figures 2 to 4 , label “VSYNC” denotes a vertical synchronization signal, label “HSYNC” denotes a horizontal synchronization signal, label “TF” denotes a frame period of the display module 130, label “TE” denotes an enable period of the vertical synchronization signal VSYNC, label “TD” denotes a disable period of the vertical synchronization signal VSYNC, labels “TH1” and “TH2” denote horizontal synchronization periods of the horizontal synchronization signal HSYNC, respectively (e.g., including an enable period (e.g., a low logic level) and a disable period (e.g., a high logic level) of the horizontal synchronization signal HSYNC), label “CLK” denotes a clock signal, label “DE” denotes a data display indication signal, label “DAT” denotes a data signal, label “D” denotes display data, label “INV” denotes invalid data, label “CSD” denotes configuration setting data, and label “CS” denotes a control signal.

[0062] Please also refer to Figures 1 to 4 .like Figure 2As shown, during one frame period TF of the display module 130, during the enable period TE of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a low logic level, and the enable period TE of the vertical synchronization signal VSYNC includes two scan lines, that is, the enable period TE of the vertical synchronization signal VSYNC includes two horizontal synchronization periods TH1 of the horizontal synchronization signal HSYNC, and each of the two horizontal synchronization periods TH1 of the horizontal synchronization signal HSYNC may include multiple clock pulses of the clock signal CLK. At this time, as Figure 3 As shown, the control module 110 provides a control signal CS of a low logic level, a clock signal CLK, a data signal DAT including configuration setting data CSD, and a data display signal DE of a low logic level to the display module 130 .

[0063] Then, the display module 130 can perform configuration settings based on the control signal CS, the clock signal CLK, and the configuration setting data CSD at a low logic level. Furthermore, the display module 130 can ignore the clock signal CLK received by the third pin 133 of the display module 130 and the data signal DAT including the configuration setting data CSD received by the fifth pin 135 of the display module 130 based on the data display indication signal DE at a low logic level (e.g., during the disable period of the data display indication signal DE). In other words, the display module 130 will not display the data signal DAT including the configuration setting data CSD.

[0064] Then, if Figure 2 As shown, during the disable period TD of the vertical synchronization signal VSYNC, the vertical synchronization signal VSYNC is at a high logic level, and the disable period TD of the vertical synchronization signal VSYNC may include a plurality of horizontal synchronization periods TH2 of the horizontal synchronization signal HSYNC, and each of these horizontal synchronization periods TH2 may include a plurality of clock pulses of the clock signal CLK. At this time, Figure 4 As shown, the control module 110 may provide a control signal CS of a high logic level, a clock signal CLK, a data signal DAT including display data D, and a data display indication signal DE of a high logic level to the display module 130 .

[0065] Then, the display module 130 may ignore the clock signal CLK received by the second pin 132 of the display module 130 and the data signal DAT including the display data D received by the fourth pin 134 of the display module 130 according to the control signal CS at a high logic level. That is, the display module 130 does not configure the internal register.

[0066] On the other hand, the display module 130 can perform normal display according to the data display indication signal DE at a high logic level (e.g., during the enable period of the data display indication signal DE), the clock signal CLK, and the data signal DAT including the display data D. That is, the display module 130 can display the data signal DAT including the display data D via the clock signal CLK during the enable period of the data display indication signal DE.

[0067] exist Figure 2 In the figure, the enable period TE of the vertical synchronization signal VSYNC is shown to include two scan lines, that is, the enable period TE includes two horizontal synchronization periods TH1 of the horizontal synchronization signal HSYNC, but the embodiment of the present invention is not limited thereto. The user can adjust the enable period TE of the vertical synchronization signal VSYNC to include three or more scan lines, that is, the enable period TE can include three or more horizontal synchronization periods TH1 of the horizontal synchronization signal HSYNC, as needed, to achieve the same effect.

[0068] In summary, the control device and display device of the present invention provide a control signal via a first pin of the control module, a clock signal via a second pin of the control module, and a data signal via a third pin of the control module. The data signal includes display data and configuration data. During an enabled period of a vertical synchronization signal, the control module provides a first-level control signal, a clock signal, and a data signal including the configuration data to the display module (display device), causing the display module to perform configuration settings based on the control signal, clock signal, and configuration data. During a disabled period of the vertical synchronization signal, the control module provides a second-level control signal, a clock signal, and a data signal including the display data to the display module (display device), causing the display module (display device) to perform normal display based on the control signal, clock signal, and display data. Furthermore, the second and third pins of the display module can share the second pin of the control module, and the fourth and fifth pins of the display module can share the third pin of the control module. In this way, the number of used pins of the control module can be effectively reduced, so that the free pins of the control module can be used to expand the functions of the control module and maintain the normal display function of the display module, thereby increasing the convenience of use.

[0069] Although the present invention is described above with reference to the embodiments, they are not intended to limit the scope of the invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A control device, applicable to a display device, characterized in that: include: a control module having a first pin, a second pin, a third pin, and a fourth pin, wherein the first pin of the control module provides a control signal, the second pin of the control module provides a clock signal, the third pin of the control module provides a data signal, and the data signal includes display data and configuration setting data, and the fourth pin of the control module provides a vertical synchronization signal; During an enabling period of the vertical synchronization signal, the control module provides the control signal of a first level, the clock signal, and the data signal including the configuration setting data to the display device, so that the display device performs a configuration setting according to the control signal, the clock signal, and the configuration setting data; During a disable period of the vertical synchronization signal, the control module provides the control signal of a second level, the clock signal, and the data signal including the display data to the display device, so that the display device performs a normal display according to the control signal, the clock signal, and the display data.

2. The control device according to claim 1, wherein: The configuration setting data includes the resolution and image format of the display device.

3. The control device according to claim 1, wherein: The control module further includes a fifth pin. The fifth pin of the control module provides a horizontal synchronization signal.

4. The control device according to claim 3, wherein: The enable period of the vertical synchronization signal includes a plurality of horizontal synchronization periods of the horizontal synchronization signal, and each of the horizontal synchronization periods includes a plurality of clock pulses of the clock signal.

5. The control device according to claim 1, wherein: The first level and the second level are complementary.

6. A display device, characterized in that: include: a control module having a first pin, a second pin, a third pin, and a fourth pin, wherein the first pin of the control module provides a control signal, the second pin of the control module provides a clock signal, the third pin of the control module provides a data signal, and the data signal includes display data and configuration setting data, and the fourth pin of the control module provides a vertical synchronization signal; and a display module having a first pin, a second pin, a third pin, a fourth pin, a fifth pin, and a sixth pin, wherein the first pin of the display module is coupled to the first pin of the control module, the second pin and the third pin of the display module are coupled to the second pin of the control module, the fourth pin and the fifth pin of the display module are coupled to the third pin of the control module, and the sixth pin of the display module is coupled to the fourth pin of the control module; During an enabling period of the vertical synchronization signal, the control module provides the control signal of a first level, the clock signal, and the data signal including the configuration setting data to the display module, so that the display module performs a configuration setting according to the control signal, the clock signal, and the configuration setting data; During a disable period of the vertical synchronization signal, the control module provides the control signal of a second level, the clock signal, and the data signal including the display data to the display module, so that the display module performs a normal display according to the control signal, the clock signal, and the display data.

7. The display device according to claim 6, wherein The configuration setting data includes the resolution and image format of the display module.

8. The display device according to claim 6, wherein The control module further includes a fifth pin, and the fifth pin of the control module provides a horizontal synchronization signal. The display module further includes a sixth pin, and the sixth pin of the display module is coupled to the fourth pin of the control module.

9. The display device according to claim 8, wherein The enable period of the vertical synchronization signal includes a plurality of horizontal synchronization periods of the horizontal synchronization signal, and each of the horizontal synchronization periods includes a plurality of clock pulses of the clock signal.

10. The display device according to claim 6, wherein The first level and the second level are complementary.

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