Infinitely scalable display device and driving method thereof

Abstract

An infinitely scalable display device includes a setting board that outputs image data with a first resolution and a plurality of display units that are connected to each other through an interface circuit based on a cascade scheme to display the image data, each of the plurality of display units includes an application-specific integrated circuit (ASIC) embedded therein, wherein each of the plurality of display units includes: a plurality of slave display units that generate unit layout coordinate information based on connection of the interface circuit; and a master display unit that scales the image data with the first resolution based on the unit layout coordinate information and transmits the scaled image data to the plurality of slave display units.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0184358, filed on Dec. 28, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to an infinitely expandable display device that can be expanded. Background Art

[0004] Recently, large-size displays are being used in various fields, such as indoor and outdoor digital advertising. In order to meet the demand for large-size displays, an infinitely scalable display device has been proposed. In the infinitely scalable display device, a single screen is configured by connecting a plurality of display units, and the screen size can be increased according to the situation.

[0005] The screen size of each infinitely scalable display device is determined based on the number of connected display units, and image data reproduced by the display units is supplied from a set board. In the case of changing the number of connected display units, a resolution matching process between the set board and the display units is necessarily required. For example, when the output resolution of the set board is not changed based on the number of connected display units, a screen fading phenomenon or the like occurs, and it is impossible to reproduce an image normally. Summary of the invention

[0006] In order to overcome the above-mentioned problems of the related art, the present disclosure may provide an infinitely scalable display device and a driving method thereof, in which a display unit may reproduce a normal image even without changing an output resolution of a setting panel.

[0007] To achieve these goals and other advantages, and in accordance with the purposes of the present disclosure, as specifically implemented and broadly described herein, an infinitely scalable display device includes: a setting board that outputs image data having a first resolution; and a plurality of display units that are connected to each other via an interface circuit based on a cascade scheme to display the image data, each of the plurality of display units including an application-specific integrated circuit (ASIC) embedded therein, wherein each of the plurality of display units includes: a plurality of slave display units that generate unit arrangement coordinate information based on the connection of the interface circuit; and a master display unit that scales the image data having the first resolution based on the unit arrangement coordinate information and transmits the scaled image data to the plurality of slave display units.

[0008] In another aspect of the present disclosure, a driving method of an infinitely scalable display device, the infinitely scalable display device includes a plurality of display units connected to each other through an interface circuit based on a cascade scheme, and each display unit includes an application-specific integrated circuit (ASIC) embedded therein, the method including outputting image data having a first resolution to the plurality of display units by using a setting board, generating unit arrangement coordinate information based on connection of the interface circuit by using a plurality of slave display units of the plurality of display units, and scaling the image data having the first resolution based on the unit arrangement coordinate information, and transmitting the scaled image data to the plurality of slave display units by using a master display unit of the plurality of display units. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments (single or multiple) of the present disclosure and together with the description serve to explain the principles of the present application. In the drawings:

[0010] Figure 1 is a diagram schematically illustrating an infinitely scalable display device according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown based on Figure 1 Graph showing the resolution of a drive unit of an infinitely scalable display device.

[0012] Figure 3 is a diagram showing a configuration of a display unit in an infinitely scalable display device.

[0013] Figure 4 is a diagram showing a configuration of a panel driving circuit of a display unit in an infinitely scalable display device.

[0014] Figure 5 and Figure 6 is a diagram showing a configuration of a back cover of a display unit in an infinitely scalable display device.

[0015] Figure 7 is a diagram showing a screen fading phenomenon occurring due to a resolution mismatch between a setting board and a display unit in a comparative example of the present disclosure.

[0016] Figure 8 is a diagram showing a case where a normal screen is reproduced despite a mismatch in resolution between a set panel and a display unit in an embodiment of the present disclosure.

[0017] Fig. 9 and Fig.10 is a diagram showing a connection configuration of a display unit for compensating for resolution mismatch.

[0018] Fig.11is a diagram showing an operation sequence of a display unit for compensating for resolution mismatch.

[0019] Figure 12 to Figure 14 : is a diagram showing the principle of generating cell arrangement coordinate information about a display cell having a size of two cells (width)×two cells (height).

[0020] Fig.15 is a diagram showing the principle of generating cell arrangement coordinate information about a display cell having a size of three cells (width)×two cells (height).

[0021] Fig.16 shows a screen display state before applying an embodiment of the present disclosure; and

[0022] Fig.17 The screen display state after applying the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concepts of the present disclosure to those skilled in the art.

[0024] The following embodiments described with reference to the accompanying drawings will illustrate the advantages and features of the present disclosure and their implementation methods. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0025] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing various embodiments of the present disclosure are exemplary only, and the present disclosure is not limited thereto. Similar reference numerals refer to similar elements throughout. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "including", "having", "comprising", etc. imply that other parts may be added, unless the term "only" is used. As used herein, the singular forms "one", "an", and "the" are also intended to include plural forms, unless the context clearly indicates otherwise.

[0026] Even if not explicitly stated, the elements in the various embodiments of the present disclosure should be construed as including error tolerances.

[0027] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "over", "under", and "immediately adjacent to", one or more other parts may be disposed between the two parts unless "just" or "directly" is used.

[0028] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the key points of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a diagram schematically illustrating an infinitely scalable display device according to an embodiment of the present disclosure. Figure 2 It is shown based on Figure 1 Illustration showing the resolution of a drive unit of an infinitely scalable display device. Figure 3 is a diagram showing a configuration of a display unit in an infinitely scalable display device. Figure 4 is a diagram showing the configuration of a panel driving circuit of a display unit in an infinitely scalable display device. Also, Figure 5 and Figure 6 is a diagram showing a configuration of a back cover of a display unit in an infinitely scalable display device.

[0031] Figure 1 The infinitely expandable display device according to an embodiment of the present disclosure shown in FIG. 1 may include a setting plate and a cabinet.

[0032] The housing may include a plurality of display units connected to each other via an interface circuit, and thus a large screen may be configured. The total resolution of the large screen may be determined as the sum of the unit resolutions of the display units. Figure 2 As shown, when the housing is configured with sixteen display units with a unit resolution of 480*270, the total resolution of the housing can be 1920*1080.

[0033] The display unit can be based on an electroluminescent display type or a liquid crystal display type, but the technical spirit of the present disclosure is not limited to the implementation type of the display unit. Hereinafter, for ease of description, in the embodiments of the present disclosure, an example of implementing the display unit as an electroluminescent display type will be mainly described.

[0034] In order to achieve zero border, the interval between display units in the housing (ie, the seam size) can be designed to be smaller than the interval between pixels (ie, the pixel pitch). Zero border can improve the visibility and readability of the screen.

[0035] The display units can be connected to each other through an interface circuit based on a cascade scheme, and image data generated by the setting board can be sequentially transmitted. In order to reduce the complexity and manufacturing cost of the communication interface, the interface circuit connecting the display units can be implemented based on a wireless scheme. Here, the interface circuit can be a unidirectional interface circuit, or it can be a bidirectional interface circuit.

[0036] Each display unit may be an electroluminescent display device including a display panel provided with a plurality of pixels and a panel driving circuit for driving the display panel. The panel driving circuit may include an application specific integrated circuit (ASIC), a data driver, and a gate driver.

[0037] The display unit may include a master display unit and a plurality of slave display units. The ASIC of the master display unit may include an image scaler embedded therein, and therefore, an operation of calculating the physical resolution of each display unit and an image scaling operation of the display unit may be performed. Therefore, when a resolution mismatch occurs between the setting board and the display unit, the display unit may reproduce a normal image even without changing the output resolution of the setting board.

[0038] The ASIC of each slave display unit may generate unit arrangement coordinate information for calculating the physical resolution. The unit arrangement coordinate information may be transmitted from the first slave display unit to the last slave display unit based on the cascade scheme, and thus may be updated. The unit arrangement coordinate information finally updated in the last slave display unit may be fed back to the master display unit through a feedback loop.

[0039] Figure 3The pixel array shown in the figure can be formed in the front surface of the substrate of the display panel. A plurality of sub-pixels can be arranged in the pixel array, and in addition, a plurality of signal lines for supplying a driving voltage to the plurality of sub-pixels can be arranged in the pixel array. The signal line can include a plurality of data lines DL for transmitting a data voltage Vdata, a plurality of gate lines GL1 and GL2 for transmitting gate signals SCAN and SEN, and a plurality of read lines RL for supplying a reference voltage VREF and sensing pixel driving characteristics Vsen. In addition, the signal line arranged in the pixel array can also include a driving voltage line for transmitting a high-level pixel voltage EVDD. In the pixel array, the data line DL and the read line RL can be arranged to extend in a first direction, and the gate lines GL1 and GL2 can be arranged to extend in a second direction intersecting the first direction. The signal line can be connected to the pixel circuit of each sub-pixel and can be connected to the panel driving circuit. In addition, a low-level pixel voltage EVSS can be supplied to the pixel array. Here, the low-level pixel voltage EVSS can be a common voltage applied to all sub-pixels. Compared with the display mode for displaying an image, in the sensing mode for detecting the driving characteristics, the low-level pixel voltage EVSS can be applied as a higher voltage.

[0040] A plurality of sub-pixels may constitute one pixel. For example, red (R), white (W), green (G), and blue (B) sub-pixels adjacent to each other in a first direction may constitute one pixel. In addition, R, G, and B sub-pixels may constitute one pixel, and in this case, the W sub-pixel may be omitted in the pixel array. The R, W, G, and B sub-pixels may only include different luminescent materials contained in their light-emitting devices and may have a configuration substantially the same as that of their pixel circuits.

[0041] Each sub-pixel, such as Figure 3 As shown in FIG. 1 , a light emitting device OLED, a driving thin film transistor (TFT) DT, a plurality of switching TFTs ST1 and ST2, and a storage capacitor Cst may be included. The driving TFT DT and the switching TFTs ST1 and ST2 may be implemented as NMOS transistors, but are not limited thereto.

[0042] The light emitting device OLED may be a light emitting device that emits light having an intensity corresponding to a pixel current input from the driving TFT DT. The light emitting device OLED may be implemented as an organic light emitting diode including an organic light emitting layer, or may be implemented as an inorganic light emitting diode including an inorganic light emitting layer. An anode electrode of the light emitting device OLED may be connected to the second node N2, and a cathode electrode thereof may be connected to an input terminal for a low-level pixel voltage EVSS.

[0043] The driving TFT DT may be a driving element that generates a pixel current based on its gate-source voltage. A gate electrode of the driving TFT DT may be connected to a first node N1, a first electrode (drain electrode) may be connected to an input terminal of a high-level pixel voltage EVDD, and a second electrode (source electrode) may be connected to a second node N2.

[0044] The switching TFTs (eg, first and second switching TFTs) ST1 and ST2 may be switching elements that set a gate-source voltage and connect the second electrode of the driving TFT DT to the read line RL.

[0045] The first switch TFT ST1 may be connected between the data line DL and the first node N1, and may be turned on based on the first gate signal SCAN applied through the first gate line GL1. The first switch TFT ST1 may be turned on in a setting operation in each of the display mode and the sensing mode. When the first switch TFT ST1 is turned on, a display or sensing data voltage Vdata may be applied to the first node N1. A gate electrode of the first switch TFT ST1 may be connected to the first gate line GL1, a first electrode thereof may be connected to the data line DL, and a second electrode thereof may be connected to the first node N1.

[0046] The second switch TFT ST2 may be connected between the read line RL and the second node N2, and may be turned on based on the second gate signal SEN applied through the second gate line GL2. The second switch TFT ST2 may be turned on in the setting operation in each of the display mode and the sensing mode and may apply the reference voltage VREF to the second node N2. In addition, the second switch TFT ST2 may be turned on when performing the sensing operation after the setting operation in the sensing mode, and may transmit the source node voltage (or source voltage) of the driving TFT DT to the read line RL. Then, the sensing voltage Vsen corresponding to the source voltage may be stored in the parasitic capacitor Cp of the read line RL. The gate electrode of the second switch TFT ST2 may be connected to the second gate line GL2, the first electrode thereof may be connected to the read line RL, and the second electrode thereof may be connected to the second node N2.

[0047] The storage capacitor Cst may be connected between the first node N1 and the second node N2 and may maintain the gate-source voltage of the driving TFT DT during a certain period of time. In the display mode, the gate-source voltage of the driving TFT DT may be set to a difference voltage between the display data voltage Vdata and the reference voltage VREF, and in the sensing mode, the gate-source voltage of the driving TFT DT may be set to a difference voltage between the sensing data voltage Vdata and the reference voltage VREF.

[0048] In the display mode, a pixel current corresponding to the gate-source voltage of the driving TFT DT may flow in the driving TFT DT, and the light emitting device OLED may emit light based on the pixel current. In the sensing mode, a pixel current corresponding to the gate-source voltage of the driving TFT DT may flow in the driving TFT DT, and the source node voltage of the driving TFT DT may vary. The source node voltage may vary based on the driving characteristics of the driving TFT DT, and therefore, the driving characteristic change of the driving TFT DT may be detected based on the sensing voltage Vsen corresponding to the source node voltage. In the sensing mode, the low-level pixel voltage EVSS may be applied to be higher than the operating point voltage of the light emitting device OLED, and therefore, the pixel current of the driving TFT DT may not flow to the light emitting device OLED, but may flow only to the reading line RL. Therefore, the source node voltage may be reflected as the sensing voltage Vsen at an early stage, and therefore, the sensing reliability may be improved.

[0049] The configuration and operation of the sub-pixel are only embodiments, and the technical spirit of the present disclosure is not limited thereto. For example, the first and second gate signals SCAN and SEN can be provided as one signal, and the first and second gate lines GL1 and GL2 can be provided as one line. In addition, the configuration of the sub-pixel can be designed based on a double-rate driving scheme.

[0050] In each display unit, Figure 4 In the embodiment, the ASIC may be mounted on a control printed circuit board C-PCB and may be disposed on the rear surface of the substrate of the display panel. The control printed circuit board C-PCB may be connected to the source printed circuit board S-PCB through a connection cable CBL. The conductive film COF on which the data driver DIC is mounted may be bonded to the source printed circuit board S-PCB. Therefore, the ASIC may be electrically connected to the data driver DIC, and a signal supply path may be formed therebetween. The control printed circuit board C-PCB may include a first connection terminal LCNT and a second connection terminal RCNT for connecting the ASIC to the interface circuit. The first connection terminal LCNT and the second connection terminal RCNT may be connected to a source printed circuit board S-PCB disposed on the control printed circuit board C-PCB. Figure 5 and Figure 6The back cover terminals BC-LCNT and BC-RCNT in the back cover of the ASIC can be connected to the interface circuit (i.e., the signal transmission / reception terminals TX and RX). A plurality of connection check pins CCP representing specific logic combination information when connecting the interface circuit can be connected to the control printed circuit board C-PCB. The connection check pins CCP can be connected between the ASIC and the first and second connection terminals LCNT and RCNT. Each ASIC of the slave display unit can calculate the coordinate increase value based on the logic combination information about the connection check pins CCP, and can add the calculated coordinate increase value to the coordinate information about the previous unit, thereby generating the coordinate information about the current unit.

[0051] A signal receiving terminal RX and a signal transmitting terminal TX can be installed Figure 5 The back cover of the display unit is provided to realize a unidirectional interface circuit based on a wireless scheme. The signal receiving terminal RX can be wirelessly connected to the signal transmission terminal TX included in the adjacent display unit. In addition, the signal transmission terminal TX can be wirelessly connected to the signal receiving terminal RX included in another adjacent display unit. The back cover terminals BC-LCNT and BC-RCNT can be electrically connected to the power socket and can be further connected to the signal receiving terminal RX and the signal transmission terminal TX through an internal cable. The input power can be supplied to the power socket from the outside. The input power supplied to the power socket can be supplied to the signal receiving terminal RX and the signal transmission terminal TX through the back cover terminals BC-LCNT and BC-RCNT and the internal cable. In addition, the input power supplied to the power socket can be supplied to the ASIC through the back cover terminals BC-LCNT and BC-RCNT and the first and second connection terminals LCNT and RCNT, and can be further supplied to the power circuit. The power circuit can be mounted on the control printed circuit board C-PCB and can process the input power to generate the operating voltage of the data driver DIC, the operating voltage of the gate driver, and the operating voltage EVDD and VREF of the pixel. The various operating voltages generated by the power circuit can be supplied to the data driver DIC through the connecting cable CBL and the source printed circuit board S-PCB.

[0052] Two signal receiving terminals RX and RX1 and two signal transmitting terminals TX and TX1 can be installed in Figure 6In the back cover of the power socket, to realize a bidirectional interface circuit based on a wireless scheme. The signal receiving terminal RX can be wirelessly connected to the signal transmission terminal TX included in the adjacent display unit, and the signal transmission terminal TX can be wirelessly connected to the signal receiving terminal RX included in another adjacent display unit. In addition, the signal receiving terminal RX1 can be wirelessly connected to the signal transmission terminal TX1 included in the adjacent display unit, and the signal transmission terminal TX1 can be wirelessly connected to the signal receiving terminal RX1 included in another adjacent display unit. The back cover terminals BC-LCNT and BC-RCNT can be electrically connected to the power socket and can be further connected to one of the signal receiving terminals RX and the signal transmission terminals TX through an internal cable. The input power supplied to the power socket can be supplied to the signal receiving terminals RX and RX1 and the signal transmission terminals TX and TX1 through the back cover terminals BC-LCNT and BC-RCNT and the internal cable. In addition, the input power supplied to the power socket can be supplied to the ASIC through the back cover terminals BC-LCNT and BC-RCNT and the first and second connection terminals LCNT and RCNT, and can be further supplied to the power circuit. The power circuit may be mounted on the control printed circuit board C-PCB and may process input power to generate an operating voltage of the data driver DIC, an operating voltage of the gate driver, and operating voltages EVDD and VREF of the pixel. The various operating voltages generated by the power circuit may be supplied to the data driver DIC through the connection cable CBL and the source printed circuit board S-PCB.

[0053] The bidirectional interface circuit can be activated in a first transmission direction and then can be activated in a second transmission direction opposite to the first transmission direction. When the bidirectional interface circuit is activated in the first transmission direction, Figure 6 The back cover terminals BC-LCNT and BC-RCNT in the back cover can be connected to the signal receiving terminal RX and the signal transmitting terminal TX through an internal cable. On the other hand, when the bidirectional interface circuit is activated in the second transmission direction, Figure 6 The back cover terminals BC-LCNT and BC-RCNT in the back cover can be connected to the signal receiving terminal RX1 and the signal transmitting terminal TX1 through an internal cable.

[0054] The image data output from the setting board can be transmitted from the adjacent display unit to the signal receiving terminal RX. The image data transmitted to the signal receiving terminal RX can be supplied to the ASIC through the internal cable, the back cover terminals BC-LCNT and BC-RCNT, and the first and second connection terminals LCNT and RCNT. The ASIC can process the image data into unit image data based on the unit resolution of the display panel, and then, the unit image data can be stored in the memory. In addition, the ASIC can supply the image data remaining after processing to the signal transmission terminal TX through the first and second connection terminals LCNT and RCNT, the back cover terminals BC-LCNT and BC-RCNT, and the internal cable. Then, the signal transmission terminal TX can transmit the image data remaining after processing to another adjacent display unit.

[0055] The ASIC may supply the data driver DIC with unit image data and a timing control signal synchronized with the unit image data.

[0056] The data driver DIC may include a digital-to-analog converter DAC that generates a data voltage Vdata, a sensing circuit SENU, and an analog-to-digital converter ADC. In a display mode, the digital-to-analog converter DAC may convert image data supplied from the ASIC based on a timing control signal to generate a display data voltage Vdata, and may supply the display data voltage Vdata to the data line DL. In a sensing mode, the digital-to-analog converter DAC may generate a predetermined sensing data voltage Vdata and may supply the sensing data voltage Vdata to the data line DL.

[0057] In the display mode, the sensing circuit SENU can supply the reference voltage VREF to the read line RL. In the sensing mode, the sensing circuit SENU can supply the reference voltage VREF to the read line RL and can sample the sensing voltage Vsen charged into the read line RL. The sensing circuit SENU may include a reference voltage switch SPRE connected between the read line RL and the reference voltage VREF input terminal, and a sampling switch SAM connected between the read line RL and the analog-to-digital converter ADC. The reference voltage switch SPRE may be turned on only in the setting period of the display mode / sensing mode, and the sampling switch SAM may be turned on only in the sampling period of the sensing mode.

[0058] The analog-to-digital converter ADC may digitally process the sampling voltage generated when the sampling switch SAM is turned on in the sensing mode to output the sensing result data SDATA. The sensing result data SDATA may be an execution result signal based on the driving command signal.

[0059] The gate driver may receive an operating voltage and a timing control signal through a data driver DIC. The gate driver may be embedded in a non-display area outside the pixel array of the display panel. The data driver may generate first and second gate signals SCAN and SEN based on the timing control signal, and may supply the first and second gate signals SCAN and SEN to the first and second gate lines GL1 and GL2. In display mode, the first and second gate signals SCAN and SEN may be used to select a pixel line to which the display data voltage Vdata is to be applied, and in sensing mode, the first and second gate signals SCAN and SEN may be used to select a sensing target pixel line. Here, a pixel line may represent a group of signal lines and pixels adjacent to each other in a second direction.

[0060] Figure 7 is a diagram illustrating a screen fading phenomenon occurring due to a resolution mismatch between a setting board and a display unit in a comparative example of the present disclosure. Figure 8 is a diagram showing a case where a normal screen is reproduced despite a mismatch in resolution between a set panel and a display unit in an embodiment of the present disclosure.

[0061] according to Figure 7 In a comparative example, when the connection between the four display units constituting the fourth row is released in a chassis having a screen size of four units (width) × four units (height), a portion of the output image of the setting board may not be displayed in the chassis and screen fading may occur.

[0062] On the other hand, according to Figure 8 In an embodiment of the present disclosure, even when the connection between the four display units constituting the fourth row is released in a housing having a screen size of four units (width) × four units (height), the output image of the setting board can be reduced in the housing based on the reduced screen size, and therefore, the screen fading phenomenon may not occur. According to an embodiment of the present disclosure, regardless of how the screen size changes (increases or decreases), the resolution of the image displayed by the setting board can be fixed to the original state, and a specific display unit (i.e., the main display unit) of the housing can perform an operation to compensate for the resolution mismatch (i.e., an image scaling operation to match the changed screen size).

[0063] Considering the bandwidth of the interface circuit connecting the setting board to the chassis, the image zooming operation may not be performed by the setting board but should be performed by the main display unit. When the image zooming operation is performed by the main display unit, the bandwidth of the interface circuit can be significantly reduced.

[0064] Fig. 9 and Fig.10 is a diagram showing a connection configuration of a display unit for compensating for resolution mismatch.

[0065] refer to Fig. 9 In the infinitely scalable display device according to an embodiment of the present disclosure, the display units can be connected to each other based on a one-way communication scheme based on a cascade scheme. The image data and the sensing command signal transmitted from the setting board can be sequentially transmitted and processed in a signal transmission direction based on the cascade order from the display unit [1,1] to the display unit [3,3].

[0066] According to the unidirectional communication scheme, each display unit may include a signal receiving terminal RX and a signal transmitting terminal TX, and therefore, the communication interface between the display units can be simplified and the manufacturing cost can be reduced. In addition, when the communication interface between the display units is implemented as a short-range wireless communication scheme, the simplified effect and convenience of screen expansion can be increased. The short-range wireless communication scheme can be implemented as an infrared scheme, but the present embodiment is not limited thereto.

[0067] refer to Fig.10 In the infinitely scalable display device according to an embodiment of the present disclosure, the display units may be connected to each other based on a bidirectional communication scheme based on a cascade scheme. The image data and the sensing command signal transmitted from the setting board may be sequentially transmitted and processed in a signal transmission direction based on a cascade sequence from the display unit [1,1] to the display unit [3,3]. According to the bidirectional communication scheme, each display unit may include two signal receiving terminals RX and two signal transmitting terminals TX.

[0068] exist Fig. 9 and Fig.10 In the embodiment, the setting board can be connected to the display unit through the setting interface circuit [1,1]. The setting interface circuit can be implemented as a wired or wireless interface circuit. The setting interface circuit and the unidirectional interface circuit can be implemented based on a V-by-One (Vx1) scheme that can achieve high-speed and large-capacity connection, but is not limited to this. The setting interface circuit can be replaced by another serial communication scheme (for example, a serial peripheral interface (SPI), I2C, a controller area network (CAN), and a universal asynchronous receiver / transmitter (UART)).

[0069] exist Fig. 9 and Fig.10 In the embodiment, the display unit [1, 1] may be a master display unit including a scaler, and the display units [1, 2] to [3, 3] may be slave display units that arrange coordinate information based on a connection generation unit of an interface circuit.

[0070] The slave display units may include a first slave display unit and a last slave display unit based on a signal transmission direction of the interface circuit, the display unit [1, 2] may be the first slave display unit, and the display unit [3, 3] may be the last slave display unit. The unit arrangement coordinate information may be obtained as a result of coordinate information about each slave display unit, and the coordinate information about each slave display unit is updated by sequentially transmitting the coordinate information about each slave display unit to the display units [1, 2] to the display unit [3, 3] based on a cascade scheme.

[0071] Each slave display unit may include a coordinate calculator for generating coordinate information about the current unit (which is transmitted based on the cascade scheme), a plurality of interface connection terminals LCNT and RCNT for connection of an interface circuit, and a plurality of connection check pins (see Figure 4 The coordinate calculator can be included in the corresponding ASIC. Connection check pin (see Figure 4 The CCP in the interface circuit may represent specific logic combination information when the interface circuit is connected. The coordinate calculator may receive coordinate information about the previous unit through the interface circuit, and may calculate a coordinate increase value based on the logic combination information about the connection check pin. The coordinate calculator may add the coordinate increase value to the coordinate information about the previous unit to generate coordinate information about the current unit, and may transmit the coordinate information about the current unit to the next unit through the interface circuit. Based on such a method, the coordinate information about each slave display unit may be transmitted from display unit [1,2] to display unit [3,3] based on a cascade scheme, so that it may be updated sequentially.

[0072] The display unit [3,3] may be connected to the display unit [1,1] via a feedback loop and may feed back the unit arrangement coordinate information (e.g., [3,3]) (which is the final update result) to the display unit [1,1]. The ASIC of the display unit [1,1] may calculate the physical resolution of each display unit based on the unit arrangement coordinate information (e.g., [3,3]). For example, the unit arrangement coordinate information [3,3] may indicate that the screen size of the connected display unit (i.e., the matrix number of the housing) is "three units (width) × three units (height)", and therefore, the ASIC of the display unit [1,1] may calculate the physical resolution corresponding to the screen size based on the unit resolution information about a single unit previously stored in the memory. The ASIC of the display unit [1,1] may scale the image data received from the setting board based on the physical resolution of each display unit, and may transmit the scaled image data to the slave display unit.

[0073] The operation of generating and transmitting the coordinate information by using the display unit can be performed in a power-on sequence and / or a power-off sequence. Therefore, even when the physical position of the display unit is switched therebetween for a specific purpose, the coordinate information and the unit image data can be reallocated based on the switched position, and thus, the same screen can be displayed. In addition, during the power-on sequence period and the power-off sequence period, the alternating current (AC) power supply can be turned on and the direct current (DC) power supply can be turned off, and the operation associated with the generation of the coordinate information can be performed in a state where the screen is not reproduced.

[0074] Fig.11 is a diagram showing an operation sequence of a display unit for compensating for resolution mismatch.

[0075] refer to Fig.11 , the main display unit can check the number of matrices of the case based on the unit arrangement coordinate information fed back from the slave display unit and can calculate the total resolution of the case. In addition, the main display unit can check the resolution of the input image received from the setting board, and then, when the resolution of the input image does not match the total resolution of the case, the main display unit can scale the resolution of the input image based on the total resolution of the case, and can transmit the scaled image data to the slave display unit (S31 to S34).

[0076] refer to Fig.11 , each slave display unit may divide the scaled image data into unit image data based on the corresponding coordinate information, and may output the divided image data as a corresponding coordinate image (S35 and S36).

[0077] Figure 12 to Figure 14 : is a diagram showing the principle of generating cell arrangement coordinate information about a display cell having a size of two cells (width)×two cells (height).

[0078] exist Fig.12 , display unit [1,1] may be a master display unit, and display units [1,2], [2,2], and [2,1] may be slave display units. Unlike the master display unit, each slave display unit may update the coordinate information received from the previous unit to the coordinate information about the current unit, and may transmit the updated coordinate information to the next unit. The master display unit may receive the final updated coordinate information (i.e., unit arrangement coordinate information) fed back from the last slave display unit. Here, the previous unit, the current unit, and the last slave display unit may be specified based on the signal transmission direction of the interface circuit.

[0079] Each display unit may include a plurality of connection check pins Vx1L#1, Vx1L#2, and TCNT and a plurality of auxiliary pins Vx1R#1, Vx1R#2, and BCNT. All of the connection check pins Vx1L#1, Vx1L#2, and TCNT may be connected to a logic low voltage L of 0V. Among the auxiliary pins Vx1R#1, Vx1R#2, and BCNT, the auxiliary pin Vx1R#2 may be connected to a logic low voltage L, and the auxiliary pins Vx1R#1 and BCNT may be connected to a logic high voltage H of 3.3V.

[0080] When display units having a size of two units (width)×two units (height) are connected to each other, the connection check pins Vx1L#1 and Vx1L#2 of the current unit can be connected to the auxiliary pins Vx1R#1 and Vx1R#2 of the previous unit. In this case, Vx1L#1 can be connected to Vx1R#1, and Vx1L#2 can be connected to Vx1R#2.

[0081] When the current cell is connected to the previous cell in the same row, the connection check pin TCNT may not be connected to the auxiliary check pin BCNT. On the other hand, when the current cell is connected to the previous cell in a different row, the connection check pin TCNT may be connected to the auxiliary check pin BCNT.

[0082] The following will refer to Figures 12 to 14 The principle of transmitting and updating unit coordinate information in a display unit based on a cascade scheme is described.

[0083] Since the display unit [1, 1] is the main display unit, the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "LLL", and the coordinate information may be [1, 1].

[0084] Display unit [1,2] can be connected to display unit [1,1] and can receive coordinate information [1,1]. In display unit [1,2], the logical combination information about the connection check pins Vx1L#1, Vx1L#2 and TCNT can be "HHH". The connection check pins Vx1L#1 and Vx1L#2 can be a logic high voltage H and a logic low voltage L, respectively, and therefore, it can be checked that display unit [1,2] is connected to display unit [1,1]. In addition, the connection check pin TCNT can be a logic low voltage L, and therefore, it can be checked that display unit [1,2] is connected to display unit [1,1] in the same row (ie, non-inverting connection). Display unit [1,2] can calculate the coordinate increase value [0,1] based on the logical combination information "HLL", and the coordinate increase value [0,1] can be added to the coordinate information [1,1] about the previous unit to generate coordinate information [1,2] about the current unit.

[0085] Display unit [2, 2] can be connected to display unit [1, 2] and can receive coordinate information [1, 2]. In display unit [2, 2], the logical combination information about the connection check pins Vx1L#1, Vx1L#2 and TCNT can be "HHH". All connection check pins Vx1L#1 and Vx1L#2 can be a logic high voltage H, and therefore, it can be checked that display unit [2, 2] is connected to display unit [1, 2]. In addition, the connection check pin TCNT can be a logic high voltage H, and therefore, it can be checked that display unit [2, 2] is connected to display unit [1, 2] in a different row (i.e., inversely connected). Display unit [2, 2] can calculate the coordinate increase value [1, 0] based on the logical combination information "HHH", and the coordinate increase value [1, 0] can be added to the coordinate information [1, 2] about the previous unit to generate coordinate information [2, 2] about the current unit.

[0086] Display unit [2, 1] can be connected to display unit [2, 2] and can receive coordinate information [2, 2]. In display unit [2, 1], the logical combination information about the connection check pins Vx1L#1, Vx1L#2 and TCNT can be "HLL". The connection check pins Vx1L#1 and Vx1L#2 can be a logic high voltage H and a logic low voltage L, respectively, and therefore, it can be checked that display unit [2, 1] is connected to display unit [2, 2]. In addition, the connection check pin TCNT can be a logic low voltage L, and therefore, it can be checked that display unit [2, 1] is connected to display unit [2, 2] in the same row (ie, non-inverting connection). Display unit [2, 1] can calculate a coordinate increase value [0, -1] based on the logical combination information "HLL", and can add the coordinate increase value [0, -1] to the coordinate information [2, 2] about the previous unit to generate coordinate information [2, 1] about the current unit.

[0087] Fig.15 is a diagram showing the principle of generating cell arrangement coordinate information about a display cell having a size of three cells (width)×two cells (height).

[0088] refer to Fig.15 , in the display unit [1, 1], the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "LLL", and the coordinate information may be [1, 1].

[0089] The display unit [1, 2] may be connected to the display unit [1, 1] and may receive the coordinate information [1, 1]. When the display unit [1, 2] is connected to the display unit [1, 1], the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "HLL". The display unit [1, 2] may calculate the coordinate increase value [0, 1] based on the logical combination information "HLL", and may add the coordinate increase value [0, 1] to the coordinate information [1, 1] about the previous unit to generate the coordinate information [1, 2] about the current unit.

[0090] The display unit [1,3] may be connected to the display unit [1,2] and may receive the coordinate information [1,2]. When the display unit [1,3] is connected to the display unit [1,2], the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "HLL". The display unit [1,3] may calculate the coordinate increase value [0,1] based on the logical combination information "HLL", and may add the coordinate increase value [0,1] to the coordinate information [1,2] about the previous unit to generate the coordinate information [1,3] about the current unit.

[0091] The display unit [2,3] may be connected to the display unit [1,3] and may receive the coordinate information [1,3]. When the display unit [2,3] is connected to the display unit [1,3], the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "HHH". The display unit [2,3] may calculate the coordinate increase value [1,0] based on the logical combination information "HHH", and may add the coordinate increase value [1,0] to the coordinate information [1,3] about the previous unit to generate the coordinate information [2,3] about the current unit.

[0092] The display unit [2, 2] may be connected to the display unit [2, 3] and may receive the coordinate information [2, 3]. When the display unit [2, 2] is connected to the display unit [2, 3], the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "HLL". The display unit [2, 2] may calculate the coordinate increase value [0, -1] based on the logical combination information "HLL", and may add the coordinate increase value [0, -1] to the coordinate information [2, 3] about the previous unit to generate the coordinate information [2, 2] about the current unit.

[0093] The display unit [2, 1] may be connected to the display unit [2, 2] and may receive the coordinate information [2, 2]. When the display unit [2, 1] is connected to the display unit [2, 2], the logical combination information about the connection check pins Vx1L#1, Vx1L#2, and TCNT may be "HLL". The display unit [2, 1] may calculate the coordinate increase value [0, -1] based on the logical combination information "HLL", and may add the coordinate increase value [0, -1] to the coordinate information [2, 2] about the previous unit to generate the coordinate information [2, 1] about the current unit.

[0094] Fig.16 A screen display state before the embodiment of the present disclosure is applied is shown. Fig.17 A screen display state after applying an embodiment of the present disclosure is shown.

[0095] When Fig.16 When the embodiments of the present disclosure are not applied, the input image from the setting board may maintain the original resolution regardless of the physical resolution of the housing. For example, when the resolution of the input image is 960*540 and the physical resolution of the housing is 1920*1080, the area outside the resolution of the input image may be displayed in black. Therefore, the visibility of the user may be reduced.

[0096] On the other hand, when Fig.17 When the embodiments of the present disclosure are applied in the main display unit of the housing, the resolution of the input image can be scaled based on the physical resolution of the housing. For example, when the resolution of the input image is 960*540 and the physical resolution of the housing is 1920*1080, the resolution of the input image can be enlarged to 1920*1080. As a result, the input image can be displayed to match the screen size of the housing.

[0097] This embodiment can achieve the following effects.

[0098] In the infinitely scalable display device according to the embodiment of the present disclosure, when a resolution mismatch occurs between the setting board and the display unit, one of the display units instead of the setting board can perform scaling of the input image. Therefore, in the embodiment of the present disclosure, even if the output resolution of the setting board is not changed, the display unit can reproduce a normal image, or the bandwidth of the interface circuit connecting the setting board to the display unit can be minimized.

[0099] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0100] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. An infinitely scalable display device, comprising: Setting a board to output image data having a first resolution; as well as a plurality of display units connected to each other through an interface circuit based on a cascade scheme to display the image data, each of the plurality of display units including an application specific integrated circuit (ASIC) embedded therein, Wherein, the plurality of display units include: a plurality of slave display units, each of the plurality of slave display units generating unit arrangement coordinate information indicating a position of a slave display unit among the plurality of slave display units based on connection of the interface circuit; and a master display unit that scales the image data having the first resolution based on the unit arrangement coordinate information and transmits the scaled image data to the plurality of slave display units, and wherein the master display unit that scales the image data and the plurality of slave display units display the scaled image data, Wherein, each of the plurality of slave display units comprises: Second ASIC; An interface connection terminal, used to connect the interface circuit; and a plurality of connection check pins connected between the interface connection terminal and the second ASIC, Each of the plurality of connection check pins represents specific logic combination information when the interface circuit is connected. The specific logic combination information represents whether a previous slave display unit and a current slave display unit among the plurality of slave display units are invertingly connected or non-invertingly connected.

2. The infinitely scalable display device according to claim 1, wherein: The first ASIC of the main display unit calculates a physical second resolution of each of the plurality of display units based on the unit arrangement coordinate information and scales the first resolution of the image data to the physical second resolution.

3. The infinitely scalable display device according to claim 1, wherein: The plurality of slave display units include a first slave display unit and a last slave display unit based on a signal transmission direction of the interface circuit; and The unit arrangement coordinate information is an update result when coordinate information of each slave display unit is transmitted from the first slave display unit to the last slave display unit based on the cascade scheme.

4. The infinitely scalable display device according to claim 3, wherein: The unit arrangement coordinate information updated in the last slave display unit is fed back to the master display unit through a feedback loop.

5. The infinitely scalable display device according to claim 1, wherein: The second ASIC of the current slave display unit receives the coordinate information about the previous slave display unit through the interface circuit, calculates a coordinate increase value based on the logical combination information about the multiple connection check pins, adds the coordinate increase value to the coordinate information about the previous slave display unit to generate coordinate information about the current slave display unit, and transmits the coordinate information about the current slave display unit to the next slave display unit through the interface circuit.

6. The infinitely expandable display device according to claim 1, wherein: The interface circuit is a unidirectional interface circuit.

7. The infinitely expandable display device according to claim 1, wherein: The interface circuit is a bidirectional interface circuit.

8. The infinitely expandable display device according to claim 6 or 7, wherein: The interface circuit is a short-range wireless communication scheme.

9. The infinitely expandable display device according to claim 8, wherein: The interface circuit is implemented based on a V-to-one (Vx1) scheme.

10. A method for driving an infinitely scalable display device, the infinitely scalable display device comprising a plurality of display units, the plurality of display units being connected to each other via an interface circuit based on a cascade scheme, and each display unit comprising an application specific integrated circuit (ASIC) embedded therein, the method comprising: outputting image data having a first resolution to the plurality of display units by using a setting panel; generating, by each of a plurality of slave display units among the plurality of display units, unit arrangement coordinate information based on the connection of the interface circuit, the unit arrangement coordinate information indicating a position of a slave display unit among the plurality of slave display units; as well as scaling the image data having the first resolution based on the unit arrangement coordinate information through a master display unit among the plurality of display units, and transmitting the scaled image data to the plurality of slave display units through the master display unit, wherein the master display unit that scales the image data and the plurality of slave display units display the scaled image data, Wherein, each of the plurality of slave display units comprises: Second ASIC; An interface connection terminal, used to connect the interface circuit; and a plurality of connection check pins connected between the interface connection terminal and the second ASIC, Each of the plurality of connection check pins represents specific logic combination information when the interface circuit is connected. The specific logic combination information represents whether a previous slave display unit and a current slave display unit among the plurality of slave display units are invertingly connected or non-invertingly connected.

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