Non-volatile three-dimensional memory, storage system and reading method thereof

Abstract

The application provides a nonvolatile three-dimensional memory, a storage system and a reading method thereof. The nonvolatile three-dimensional memory comprises a plurality of memory cell strings, each of which comprises a plurality of memory cells and a drain select gate transistor. The reading method comprises: after an idle stage of the nonvolatile three-dimensional memory, performing n reading operations on selected memory cells included in a selected memory cell string according to received n reading commands, n≥2 and n is a positive integer. During the n reading operations, the drain select gate transistor of an unselected memory cell string is controlled to be turned off for a longer time from being turned on to being turned off in a pre-pulse recovery stage of the first reading operation than in a pre-pulse recovery stage of any of the remaining n-1 reading operations, so as to improve the offset of the threshold voltage of the memory cell and reduce the number of failed bits in the first reading.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology. In particular, the present application relates to a non-volatile three-dimensional memory, a storage system and a reading method thereof. BACKGROUND

[0002] Non-volatile three-dimensional memories employ a vertical memory array to increase the number of cells. As the market demands for higher storage density, the industry develops non-volatile three-dimensional memories with more data states so that each cell can store more bits of data.

[0003] Non-volatile three-dimensional memories experience a period of idle time after programming or reading is completed. When the first read is performed, the data state of the cell changes due to the loss of charge stored in the cell, resulting in incorrect data being read out.

[0004] It should be appreciated that the background section is intended to provide useful background information for understanding the technology described herein and does not necessarily constitute an acknowledgement or admission that any of the information provided herein necessarily constitutes prior art. SUMMARY

[0005] One aspect of the present application provides a reading method for a non-volatile three-dimensional memory, the non-volatile three-dimensional memory comprising a plurality of strings of memory cells, each of the strings of memory cells comprising a plurality of memory cells and a drain select gate transistor, the method comprising: after an idle phase of the non-volatile three-dimensional memory, performing n read operations on selected memory cells comprised in a selected string of memory cells according to received n read commands, n≥2 and is a positive integer, wherein during the n read operations, a time from turning on to turning off of the drain select gate transistor of unselected strings of memory cells in a pre-pulse recovery phase of a first read operation is longer than a time from turning on to turning off of the drain select gate transistor of the unselected strings of memory cells in any pre-pulse recovery phase of the remaining n-1 read operations.

[0006] In one embodiment of the present application, each of the strings of memory cells further comprises a source select gate transistor, and performing n read operations on selected memory cells comprised in a selected string of memory cells comprises: turning on the drain select gate transistor and the source select gate transistor of each of the strings of memory cells in a pre-pulse phase of each of the read operations.

[0007] In one embodiment of the present application, the controlling the time for the unselected string of memory cells to turn off from on longer than the time for the unselected string of memory cells to turn off from on during any of the remaining n-1 read operations during the pre-pulse recovery phase of the first read operation includes: applying a first turn-off voltage to the gate of the drain select gate transistor of the unselected string of memory cells that decreases at a first slope during the pre-pulse recovery phase of the first read operation; and applying a second turn-off voltage to the gate of the drain select gate transistor of the unselected string of memory cells that decreases at a second slope during the pre-pulse recovery phase of any of the remaining n-1 read operations, wherein the absolute value of the first slope is less than the absolute value of the second slope.

[0008] In one embodiment of the present application, the non-volatile three-dimensional memory includes a plurality of word lines, each word line coupled to a plurality of the memory cells of a same row of the plurality of strings of memory cells, wherein performing n read operations on selected memory cells included in the selected string of memory cells includes: applying a first pass voltage to the word line corresponding to each row of the memory cells during a pre-pulse phase of each of the read operations; and applying an off voltage to the word line corresponding to the selected memory cells during a pre-pulse recovery phase of each of the read operations.

[0009] In one embodiment of the present application, the controlling the time for the unselected string of memory cells to turn off from on longer than the time for the unselected string of memory cells to turn off from on during any of the remaining n-1 read operations during the pre-pulse recovery phase of the first read operation includes: applying a first turn-off voltage to the gate of the drain select gate transistor of the unselected string of memory cells that decreases at a first slope during the pre-pulse recovery phase of the first read operation; and applying a second turn-off voltage to the gate of the drain select gate transistor of the unselected string of memory cells that decreases at a second slope during the pre-pulse recovery phase of any of the remaining n-1 read operations, wherein the absolute value of the first slope is less than the absolute value of the second slope.

[0010] Another aspect of the present application provides a non-volatile three-dimensional memory, comprising: a plurality of strings of memory cells, each of the strings of memory cells including a plurality of memory cells and a drain select gate transistor; and a peripheral circuit coupled to the strings of memory cells and configured to: receive n read commands after an idle phase of the non-volatile three-dimensional memory to perform n read operations on selected memory cells included in a selected string of memory cells, n > 2 and is a positive integer, wherein during the n read operations, a time for a drain select gate transistor of an unselected string of memory cells to turn off from on during a pre-pulse recovery phase of a first read operation is controlled to be longer than a time for the drain select gate transistor of the unselected string of memory cells to turn off from on during any of the remaining n-1 read operations.

[0011] In one embodiment of the present application, the memory cell string includes a source select gate transistor, and the peripheral circuit includes a control logic unit and a voltage generator and a word line driver coupled to the control logic unit, respectively, the control logic unit being configured to control the voltage generator to apply a select gate signal to the word line driver to apply a turn-on voltage to the gate of the drain select gate transistor and the source select gate transistor of each of the memory cell string via the word line driver at a pre-pulse phase of each of the read operations.

[0012] In one embodiment of the present application, the control logic unit is configured to control the voltage generator to apply a first drain select gate signal to the word line driver to apply a first turn-off voltage that decreases at a first slope to the gate of the drain select gate transistor of the unselected memory cell string via the word line driver at the pre-pulse recovery phase of the first read operation, and to control the voltage generator to apply a second drain select gate signal to the word line driver to apply a second turn-off voltage that decreases at a second slope to the gate of the drain select gate transistor of the unselected memory cell string via the word line driver at the pre-pulse recovery phase of any of the remaining n-1 read operations, wherein an absolute value of the first slope is smaller than an absolute value of the second slope.

[0013] Still another aspect of the present application provides a memory system, including the non-volatile three-dimensional memory of any of the above, the non-volatile three-dimensional memory being configured to store data; and a memory controller coupled to the non-volatile three-dimensional memory and configured to issue the read command to the peripheral circuit.

[0014] In one embodiment of the present application, the memory system includes a solid state drive or a memory card.

[0015] One aspect of the present application provides a read method for a non-volatile three-dimensional memory including a plurality of memory cell strings, the method including: after an idle phase of the non-volatile three-dimensional memory, performing n read operations on selected memory cell strings according to received n read commands, n≥2 and being a positive integer, wherein a time from turn-on to turn-off of selected memory cell strings at a pre-pulse recovery phase of a first read operation is longer than a time from turn-on to turn-off of selected memory cell strings at a pre-pulse recovery phase of any of the remaining n-1 read operations during the n read operations.

[0016] In one embodiment of the present application, the non-volatile three-dimensional memory includes a plurality of word lines, each of the word lines coupled with a plurality of the memory cells of a same row, wherein performing the n read operations on the selected memory cell includes, in a pre-pulse phase of each of the read operations, applying a pass voltage to a word line corresponding to the memory cell of each row.

[0017] In one embodiment of the present application, controlling the selected memory cell to turn off later in the pre-pulse recovery phase of the first read operation than in any of the pre-pulse recovery phases of the remaining n-1 read operations includes, in the pre-pulse recovery phase of the first read operation, applying a first turn-off voltage to a word line corresponding to the selected memory cell, the first turn-off voltage decreasing at a third slope, and in any of the pre-pulse recovery phases of the remaining n-1 read operations, applying a second turn-off voltage to the word line corresponding to the selected memory cell, the second turn-off voltage decreasing at a fourth slope, wherein an absolute value of the third slope is less than an absolute value of the fourth slope.

[0018] In one embodiment of the present application, the non-volatile three-dimensional memory further includes a plurality of memory cell strings, each of the memory cell strings including a plurality of the memory cells coupled in series, wherein performing the n read operations on the selected memory cell includes, in a pre-pulse phase of each of the read operations, turning on the drain select gate transistor and the source select gate transistor of each of the memory cell strings, and in a pre-pulse recovery phase of each of the read operations, turning off the drain select gate transistor of the unselected memory cell strings.

[0019] In one embodiment of the present application, controlling the selected memory cell to turn off later in the pre-pulse recovery phase of the first read operation than in any of the pre-pulse recovery phases of the remaining n-1 read operations includes controlling the selected memory cell to turn off 2-6 microseconds later in the pre-pulse recovery phase of the first read operation than in any of the pre-pulse recovery phases of the remaining n-1 read operations.

[0020] Another aspect of the present application provides a non-volatile three-dimensional memory, including: a plurality of memory cell strings, each of the memory cell strings including a plurality of memory cells; and a peripheral circuit coupled to the memory cell strings and configured to: receive n read commands after an idle phase of the non-volatile three-dimensional memory to perform n read operations on selected memory cells included in a selected memory cell string, n≥2 and being a positive integer, wherein during the n read operations, a selected memory cell is controlled to turn off later in a pre-pulse recovery phase of a first read operation than in any of pre-pulse recovery phases of the remaining n-1 read operations.

[0021] In one embodiment of the present application, the non-volatile three-dimensional memory includes a plurality of word lines, each of the word lines coupled to a plurality of the memory cells of a same row, and the peripheral circuit includes a control logic unit and a voltage generator and a word line driver coupled to the control logic unit, the word line driver coupled to the word lines, the control logic unit configured to control the voltage generator to apply a word line signal to the word line driver to apply a pass voltage to the word line corresponding to the memory cells of each row via the word line driver at a pre-pulse phase of each of the read operations.

[0022] In one embodiment of the present application, the control logic unit is configured to control the voltage generator to apply a first word line signal to the word line driver to apply a first disconnect voltage dropping at a third slope to the word line corresponding to the selected memory cells via the word line driver at the pre-pulse recovery phase of each of the read operations, and to control the voltage generator to apply a second word line signal to the word line driver to apply a second disconnect voltage dropping at a fourth slope to the word line corresponding to the selected memory cells via the word line driver at the pre-pulse recovery phase of any of the remaining n-1 read operations, wherein an absolute value of the third slope is smaller than an absolute value of the fourth slope.

[0023] Still another aspect of the present application provides a memory system, comprising:

[0024] The non-volatile three-dimensional memory of any of the above, configured to store data; and a memory controller coupled to the non-volatile three-dimensional memory and configured to issue the read command to the peripheral circuit.

[0025] In one embodiment of the present application, the memory system includes a solid state drive or a memory card. BRIEF DESCRIPTION OF DRAWINGS

[0026] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings,

[0027] Figure 1 a block diagram of an exemplary system including a memory according to some embodiments of the present application;

[0028] Figure 2 a schematic diagram of an exemplary memory card having a memory according to some embodiments of the present application;

[0029] Figure 3 a schematic diagram of an exemplary solid state drive (SSD) having a memory according to some embodiments of the present application;

[0030] Figure 4 schematic diagram of a non-volatile three-dimensional memory including a peripheral circuit and a memory array according to some embodiments of the present application;

[0031] Figure 5 schematic equivalent circuit diagram of a memory array included in a non-volatile three-dimensional memory according to some embodiments of the present application;

[0032] Figure 6 statistical distribution diagram of threshold voltages of a plurality of memory cells included in a non-volatile three-dimensional memory according to some embodiments of the present application;

[0033] Figure 7 schematic flow chart diagram of a read method of a non-volatile three-dimensional memory according to some embodiments of the present application;

[0034] Figure 8 voltage waveform timing diagram of a two-time read operation of a non-volatile three-dimensional memory according to some embodiments of the present application;

[0035] Figure 9 comparison diagram of FBC and pre-pulse recovery time for multiple reads at the same temperature of a non-volatile three-dimensional memory according to some embodiments of the present application;

[0036] Figure 10 schematic flow chart diagram of a read method of a non-volatile three-dimensional memory according to some other embodiments of the present application;

[0037] Figure 11 voltage waveform timing diagram of a two-time read operation of a non-volatile three-dimensional memory according to some other embodiments of the present application;

[0038] Figure 12 comparison diagram of FBC and pre-pulse recovery time for multiple reads at the same temperature of a non-volatile three-dimensional memory according to some other embodiments of the present application. DETAILED DESCRIPTION

[0039] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be understood that the detailed description is merely descriptive in nature and is in no way intended to limit the scope of the present application. Throughout the description, like reference numerals refer to like elements.

[0040] Note that reference to "one implementation," "an implementation," "one example implementation," "some implementations," etc., in the specification indicates that the feature, structure, or characteristic being discussed can be included in one or more implementations of the specification, and the specifying use of "one implementation" or "an implementation" or "one example implementation" or "some implementations" is not necessarily intended to refer to a single implementation or example of the disclosure but can include more than one implementation or example of the disclosure.

[0041] In general, terminology can be understood at least in part from usage in context. For example, terms, such as "one or more" as used herein, can be taken to mean that at least one, or there is equivalent to at least one, and that more than one is also a possibility adequate to the modification of a circumstance considered by those of ordinary skill in the art. Similarly, terms, such as "a" or "an," as used herein, can be taken to mean one or more things inclusive of one or a singular or the equivalent of one or a singular, at least the possibility of one or a singular, and at least the possibility of more than one. The singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Further, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and instead can allow for additional factors not necessarily explicitly described herein, again, at least in part, depending on the context.

[0042] It should also be understood that the use of the terms "include," "including," "have," "has," "contain," and / or "containing," when used in this specification, mean that something "may" be included or have, but not necessarily, one or more of the additional features, elements, components, and / or steps described herein.

[0043] Unless defined otherwise, all terms used herein have the same meaning as those commonly understood by one of ordinary skill in the art to which this application belongs. It should be also understood that the terms defined by dictionaries and / or otherwise generally accepted as having a previously-determined meaning take on that ordinarily understood meaning and are not to be construed in a manner that is outside of their ordinarily understood meaning unless clearly defined herein or clearly indicated by context to take on a different meaning.

[0044] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other, as long as there is no conflict. In addition, the specific steps included in the methods described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel, unless clearly limited or contradicted by the context. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0045] Figure 1A block diagram illustrating an exemplary system 400 including a memory in accordance with some embodiments of the present application is shown. The system 400 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1 shown, the system 400 can include a host 408 and a memory system 402 having one or more memories 404 and a memory controller 406. The host 408 can be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 408 can be configured to send or receive data stored in the memory 404.

[0046] According to some embodiments, the memory controller 406 is coupled to the memory 404 and the host 408 and is configured to control the memory 404. The memory controller 406 can manage data stored in the memory 404 and communicate with the host 408. In some embodiments, the memory controller 406 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed for operation in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 406 can be configured to control operations of the memory 404, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions with respect to data stored or to be stored in the memory 404, including bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process error correction codes (ECC) for data read from or written to the memory 404. Any other suitable functions can also be performed by the memory controller 406, e.g., formatting the memory 404. The memory controller 406 can communicate with external devices (e.g., the host 408) according to a particular communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0047] The memory controller 406 and one or more memories 404 can be integrated into various types of memory devices, e.g., included in the same package, such as a universal flash (UFS) package or an eMMC package. That is, the memory system 402 can be implemented as and packaged into different types of end electronic products. In the case of a UFS package, the memory system 402 can be implemented as and packaged into a smartphone, a tablet, a laptop, a digital camera, a personal computer, a server, a network device, etc. Figure 2In one example shown, the memory controller 406 and the single memory 404 can be integrated into a memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 502 can further include a memory card connector 504 that electrically couples the memory card 502 with a host (e.g., the host 408 in Figure 1 FIG. 6A). Figure 3 In another example shown, the memory controller 406 and the multiple memories 404 can be integrated into an SSD 506. The SSD 506 can further include an SSD connector 508 that electrically couples the SSD 506 with a host (e.g., the host 408 in Figure 1 FIG. 6A). In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than that of the memory card 502.

[0048] Figure 4 A schematic diagram of a non-volatile three-dimensional memory 100 including a peripheral circuit and a storage array is shown in accordance with some embodiments of the present application. The non-volatile three-dimensional memory 100 can be as one example of the memory 404 shown in Figure 1 FIG. 6A, as shown in Figure 4 The non-volatile three-dimensional memory 100 includes a coupled storage array 301 and a peripheral circuit, in some embodiments. The storage array 301 can be, for example, a flash memory array, and can be implemented using 3D NAND flash technology, in some embodiments. The peripheral circuit includes, for example, a page buffer / sense amplifier 505, a column decoder / bit line driver 507, a row decoder / word line driver 509, a voltage generator 510, a control logic unit 512, a register 514, an I / F interface 516, and a data bus 518. It should be understood that the peripheral circuit can also include additional peripheral circuits not shown in Figure 4 FIG. 6A, in some examples.

[0049] In some examples, the page buffer / sense amplifier 505 can be configured to read and program (write) data from and to the storage array 301 according to control signals from the control logic unit 512. Optionally, the page buffer / sense amplifier 505 can store a page of program data (write data) to be programmed into one storage page (e.g., the storage page 320 shown in Figure 5 FIG. 6A) of the storage array 301. In another example, the page buffer / sense amplifier 505 can also read data from a bit line (e.g., the bit line 330 shown in Figure 5The low-power signals representing the data bits stored in the memory cells 306 are sensed by the bit lines 316 shown in FIG. 3) and amplified to recognizable logic levels with small voltage swings. The column decoders / bit line drivers 507 can be configured to be controlled by the control logic unit 512 and select one or more strings 308 of memory cells by applying bit line voltages generated by the voltage generator 510.

[0050] In some embodiments, the row decoders / word line (WL) drivers 509 can be configured to be controlled by the control logic unit 512 and select / deselect the memory blocks 304 of the memory array 301 and select / deselect the word lines of the blocks 304 (e.g. Figure 5 The word lines 318 shown in FIG. 3). The row decoders / word line drivers 509 can also be configured to drive the word lines 318 using the word line voltages generated by the voltage generator 510. In some implementations, the row decoders / word line (WL) drivers 509 can also select / deselect and drive the source select lines (SSL) 315( Figure 5 ) and the drain select lines (DSL) 313( Figure 5 ).

[0051] In some embodiments, the voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate various voltages (e.g., read voltages, turn-on voltages, turn-off voltages, pass voltages, etc.) to be provided to the memory array 301 and suitable for read operations. For example, in a read phase of a read operation, a read voltage is provided to the row decoders 509 to drive the word lines (WL) to read the memory cells 306( Figure 5 ) coupled thereto.

[0052] In some embodiments, the control logic unit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The control logic unit 512 can perform the operation methods of the flash memory described below. The registers 514 can be coupled to the control logic unit 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits.

[0053] In some embodiments, the I / F interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer commands and data from a host (e.g., Figure 1The host 408 (shown in the diagram) receives control commands and forwards them to the control logic unit 512, and buffers status information received from the control logic unit 512 and forwards it to the host 408. The I / F interface 516 can also be coupled to the column decoder / bit line driver 507 via the data bus 518, and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory array 301.

[0054] In some embodiments, the storage array 301 may include one or more storage planes, concurrent operations may occur at different storage planes, and each storage plane may include multiple storage blocks (e.g., Figure 5 (Storage block 304 shown). In some examples, storage block 304 may be the smallest unit for performing an erase operation. See also... Figure 5 The storage block 304 may include multiple storage cell strings 308. In some embodiments, each storage cell string 308 includes multiple storage cells 306 that are series-coupled and vertically stacked. Each storage cell 306 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage cell 306. Each storage cell 306 may be a floating-gate type storage cell including a floating-gate transistor, or a charge-trapping type storage cell including a charge-trapping transistor.

[0055] In some implementations, the non-volatile three-dimensional memory 100 includes three types: SLC, MLC, and TLC. SLC type indicates that each memory cell 306 stores 1 bit of data, and the memory cell 306 has only two data states: "0" and "1". MLC type indicates that each memory cell stores 2 bits of data, and the memory cell 306 has four data states: "00", "01", "10", and "11". TLC type indicates that each memory cell stores 3 bits of data, and the memory cell 306 has eight data states: "000", "001", "010", "011", "100", "101", "110", and "111". It is understood that in some examples, the memory cell 306 of the non-volatile three-dimensional memory 100 may also store more than 3 bits of data.

[0056] Continue to refer to Figure 5Each memory cell string 308 can also include a drain select gate transistor (in some cases also referred to as a "top select gate transistor, TSG transistor") 312 at its drain end and a source select gate transistor (in some cases also referred to as a "bottom select gate transistor, BSG transistor") 310 at its source end. The TSG transistor 312 and the BSG transistor 310 can be controlled by corresponding top select gate TSG and bottom select gate BSG and configured to activate the corresponding memory cell string 308 during a read operation. In some embodiments, the sources of the memory cell strings 308 in the same memory block 304 can be coupled by the same source line 314. In other words, according to some embodiments, all memory cell strings 308 in the same memory block 304 have an array common source (ACS). For example, a common source voltage can be applied to the ACS by the voltage generator 510 shown in FIG. 5. According to some embodiments, the drains of each memory cell string 308 are coupled to a respective bit line 316. In some embodiments, a turn-on voltage or a turn-off voltage can be applied to the gates of the respective drain select gate transistor 312 via one or more drain select lines 313. In some embodiments, a turn-on voltage or a turn-off voltage can also be applied to the gates of the respective source select gate transistor 310 via one or more source select lines 315. Figure 4

[0057] In other examples, the memory cell string 308 can also include dummy memory cells (not shown) for process and electrical buffering, which can be optionally located between the TSG transistor 312 and the memory cell 306 in the corresponding memory cell string 308, or alternatively, between the BSG transistor 310 and the memory cell 306.

[0058] In some examples, for instance in the same memory block 304 of the SLC type of the non-volatile three-dimensional memory 100, a plurality of memory cells 306 in the same row in each memory cell string 308 can constitute a memory page 320, and the plurality of memory cells 306 in the same memory page 320 can be coupled by the same word line 318. In some examples, the memory page 320 can be a basic unit of data for a read operation.

[0059] As shown in FIG. 5, in the TLC type of the non-volatile three-dimensional memory 100, for instance, the same word line 318 can be coupled to three memory pages 320 in the same row. Figure 6 Figure 5 Figure 5 ​​​The three memory pages 320 may include, for example, a lower page, a middle page, and an up page. Each memory cell 306 has eight data states. This is achieved by designing multiple sets of threshold voltages, thereby dividing the memory cell into multiple data states. Figure 6 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells 306 that are at that threshold voltage. After data is written to memory cells 306, the statistical distribution of the threshold voltage approximates a normal distribution. For example... Figure 6 As shown, the non-volatile three-dimensional memory 100 includes eight data states p0 to p7, where p0 is the erase state and p1 to p6 are different programming states, each with a different threshold voltage. When performing a read operation on the non-volatile three-dimensional memory 100, different read voltages V need to be applied to the corresponding memory cells 306. _rd The threshold voltage of the memory cell 306 is sensed to read data from the memory cell 306, thereby determining the data state of the memory cell 306. In some examples, the threshold voltage of the memory cell 306 can be sensed to read data from the memory cell 306. Figure 6 The seven reading voltages V shown _rd1 To V _rd7 Read from storage unit 306.

[0060] Storage unit (e.g., Figure 5The memory cell 306 shown contains a certain number of grain boundary traps (GBTs). During the programming operation, the programming voltage applied to the gate of the memory cell to be programmed causes the grain boundary traps to capture a large number of electrons. During the idle phase from the end of the programming operation to the start of the first read operation, the non-volatile three-dimensional memory 100 is in standby mode. In order to reduce power consumption, except for the voltage supply necessary for the memory cell, other voltage supplies are stopped, so the programmed memory cell is in a floating state. The grain boundary traps release the captured electrons, and the threshold voltage of the memory cell 306 shifts. In the first read operation, a large number of failure bit counts (FBCs) will be read. By comparing the FBCs of two consecutive read operations, it can be further determined whether the first read operation was erroneous. For example, for the same memory page 320, after a few hours of standby following a programming operation, two consecutive reads are performed. The number of failed bits in the first read is FBC1, and the number of failed bits in the second read is FBC2. If the ratio of the difference between FBC1 and FBC2 to FBC2 is greater than a preset value, the result of the first read will be unreliable. For example, if the difference between FBC1 and FBC2 is greater than 20%, the first read can be considered an error, i.e., a first read issue occurs, thus affecting the reliability of the non-volatile three-dimensional memory 100. Typically, the read voltage of the first read operation allows the grain boundary traps to recapture electrons, and the filling state of the grain boundary traps is close to the state at the end of the programming operation. In the second read, which is not long after the initial interval, FBC2 will return to normal.

[0061] Continue to refer to Figure 6 , Figure 6 The solid lines shown represent the threshold voltage distribution of the actual data state, which can be applied as follows: Figure 6 The reading voltage V shown _rd1 ~V _rd7 To read different data states. The dashed line represents the threshold voltage distribution that causes the first read phenomenon. Typically, the threshold voltage for data states P1 to P4 shifts to the left, while the threshold voltage for data states P5 to P7 shifts to the right. If the original read voltage V is still used at this time... _rd1 ~V _rd7 An attempt to read the data will result in a read error.

[0062] To cope with the first read phenomenon, in some examples, the read result of the first read operation can be discarded, thus the first read is also called a dummy read operation, but the dummy read operation will prolong the read preparation time (Tr) and slow down the read speed. In other examples, when a read error occurs, it is easy to cause a large number of error codes of the memory, and each error code can trigger a series of error correction mechanisms that need to be performed. Due to the large number of FBC1s caused by the first read phenomenon, uncorrectable error correction codes (UECCs) will be triggered, and the memory controller (for example, the memory controller 406 in Figure 1 determines that the first read fails, and the memory recovery firmware (FW) built in the memory controller 406 will start the repair work of the non-volatile three-dimensional memory 100, thereby increasing the power consumption of the storage system, for example, any example of the system 400 shown in Figure 1 , the FW is not shown in the figure.

[0063] Figure 7 A schematic block diagram of a read method 300 for the non-volatile three-dimensional memory 100 described above according to some embodiments of the present application is shown, which will be described in detail below in combination with Figures 7 to 9 the read method 300 described above.

[0064] As shown in Figure 7 , the read method 300 includes operation S310, after an idle phase of the non-volatile three-dimensional memory, performing n read operations on selected memory cells included in a selected memory cell string according to a received n read command, n≥2 and is a positive integer, wherein during the n read operations, the time from turning on to turning off of the drain select gate transistor of the unselected memory cell string in the pre-pulse recovery phase of the first read operation is longer than the time from turning on to turning off of the drain select gate transistor of the unselected memory cell string in any pre-pulse recovery phase of the remaining n-1 read operations.

[0065] In the read operation, the memory cell string in which the memory cell to be read is located as the selected memory cell string, and the remaining memory cell strings as the unselected memory cell string; the TSG for controlling the selected memory cell string as the selected TSG (SelTSG), and the remaining TSG as the unselected TSG (Unsel TSG); and the word line coupled with the memory cell to be read as the selected word line (Sel WL), and the remaining word line as the unselected word line (Unsel WL).

[0066] As shown in Figure 8As shown, n read operations can be performed on the selected memory cell. In the pre-pulse phase of each read operation, the selected memory cell string 308 can be activated by turning on the TSG transistor controlling the memory cell string 308. In some examples, a turn-on voltage Vtsg greater than the threshold voltage of the corresponding TSG transistor can be applied to the gates of the Sel TSG and the Unsel TSG controlling the selected memory cell string and the unselected memory cell string, respectively. In some examples, the BSG of the selected memory cell string and the unselected memory cell string can be controlled by the same bottom gate. A turn-on voltage Vbsg, which can have the same value as Vtsg, can be applied to the bottom gate controlling the BSG while Vtsg is applied to the gates of the Sel TSG and the Unsel TSG. Vtsg and Vbsg can have values greater than the threshold voltage of the corresponding TSG transistor and the threshold voltage of the BSG transistor, respectively, to turn on the TSG transistor and the BSG transistor of each memory cell string 308. In some examples, a pass voltage Vpass can be applied to the Sel WL and the Unsel WL to open the channel of each memory cell 306 in the pre-pulse phase of each read operation. After the above operations, the channel of each memory cell string 308 is turned on, and a current path is established for the selected memory cell string and the unselected memory cell string. Meanwhile, the BL and the ACS can be at a low voltage, such as 0 V.

[0067] In examples in which the memory cell string 308 includes dummy memory cells, the same operations as described above for the Unsel WL and the Sel WL can be performed on the dummy word lines corresponding to the dummy memory cells, which will not be described herein.

[0068] In some examples of read operations, the channel potential of each memory cell string 308 is at, for example, 0 V, and the grain boundary shallow traps of the memory cell 306 correspond to a negative potential in the pre-pulse phase, making it difficult for the electrons released from the grain boundary traps to fill, and it should be understood that the filling of the grain boundary traps by electrons is a slow process. Typically, in a short pre-pulse recovery phase after the pre-pulse phase, the Unsel TSG of the unselected memory cell string can be quickly turned off, and the BSG remains on and the ACS is grounded, causing the channel charge of the unselected memory cell string to be discharged through the ACS, the channel potential of the unselected memory cell string decreases quickly, reducing the read disturbance of the unselected memory cell string, and the Sel WL is quickly turned off. Exemplarily, the voltage generator 510 Figure 4 ) can be controlled to apply a voltage to the word line driver 509 Figure 4A word line signal (which is a disconnect voltage applied to SelWL) is applied to prepare for the read phase. However, the pre-pulse recovery phase is relatively short, and the channel electrons cannot fully fill the grain boundary traps of the memory cell 306, causing the threshold voltage of the memory cell 306 to remain in a state of large deviation. In the read phase described below, the first read phenomenon will be difficult to avoid.

[0069] In some examples of this application, the on-to-off time of the Unsel TSG can be extended during the pre-pulse recovery phase of the first read operation. Taking six consecutive read operations as an example, the on-to-off time of the Unsel TSG during the pre-pulse recovery phase of a normal read (e.g., the second read) can be used as a reference to control the on-to-off time of the Unsel TSG during the pre-pulse recovery phase of the first read operation to be longer than the on-to-off time during any of the pre-pulse recovery phases of the remaining five read operations. Optionally, during the pre-pulse recovery phase of the first read operation, the on-to-off time of the Unsel TSG is t1, where t1 ranges from 6 μs to 25 μs. During the pre-pulse recovery phase of the second read operation, the on-to-off time of the Unsel TSG is t2, where t2 ranges from 1 μs to 5 μs. Optionally, t1 can be 2 μs to 6 μs longer than t2.

[0070] In some examples, during the pre-pulse recovery phase of the first read operation, a first turn-off voltage with a first decreasing slope is applied to the Unsel TSG; and during any of the pre-pulse recovery phases of the remaining five read operations, a second turn-off voltage with a second decreasing slope is applied to the Unsel TSG, wherein the absolute value of the first slope is less than the absolute value of the second slope. For example, as... Figure 8 As shown, during the pre-pulse recovery phase of the first read operation, a first turn-off voltage V with a first slope k1 decreasing can be applied to the Unsel TSG. off1 Furthermore, during the pre-pulse recovery phase of the second read operation, a second turn-off voltage V, decreasing with a second slope k2, is applied to the Unsel TSG. off2 .

[0071] In read method 300, it can be done via memory controller (e.g., Figure 1 The memory controller 406 shown sends n read commands consecutively to the non-volatile three-dimensional memory 100, where n ≥ 2 and is a positive integer. When sending the first read command, the first read command can be distinguished from the remaining n-1 read commands by sending a read command with a specific prefix. For example, the memory controller 406 can send two read commands consecutively to the non-volatile three-dimensional memory 100, where the first read command has a specific prefix, and the first read command with this specific prefix will trigger the control logic unit 512 ( Figure 4) control voltage generator 510 Figure 4 ) to word line driver 509 Figure 4 ) a first selection gate signal, which is a first turn-off voltage Voff1 applied to the DSL corresponding to Unsel TSG with a first slope k1, the second read command will trigger control logic unit 512 to control voltage generator 510 to apply a second selection gate signal to word line driver 509 Figure 4 ) a first turn-off voltage Voff2 applied to the DSL corresponding to Unsel TSG with a second slope k2.

[0072] During the slow turn-off process of Unsel TSG, the channel potential of unselected memory cell string 308 is slowly reduced. Before the read stage, since Unsel TSG has a greater time from turn-on to turn-off in the first read operation than in the second read operation, the channel potential of unselected memory cell string 308 can even be reduced to below the negative potential of the grain boundary shallow trap, so that the electrons in the channel can sufficiently fill the grain boundary trap of memory cell 306, improve the shift of the threshold voltage, and thus in the read stage, the FBC of the first read can be reduced, the first read phenomenon can be avoided, and the reliability of non-volatile three-dimensional memory 100 can be improved.

[0073] For method 300, Figure 9 An exemplary relationship between the time t from turn-on to turn-off of Unsel TSG and the FBC of multiple read operations is shown, where Base FBC is the average of the FBC of the second to sixth read operations. The time of non-volatile three-dimensional memory 100 in the idle stage (e.g., standby) is set to 30 minutes, and the temperature of non-volatile three-dimensional memory 100 when in standby is 85°C. As can be seen from the figure, when t is in the range of 0-20 μs, as the time from turn-on to turn-off of Unsel TSG increases, the FBC1 produced by the first read operation is greater than the Base FBC produced by the subsequent five read operations, and as t increases, the rate at which FBC1 decreases is faster than the rate at which Base FBC decreases. For the first read operation, when t≥10 μs, FBC1≤800, while Base FBC can be less than 800 when t≤5 μs, therefore, under the above standby time and temperature, considering the read preparation time Tr and the effect of t on FBC1 and Base FBC, in each pre-pulse recovery stage of the second to sixth read operations, the time from turn-on to turn-off of Unsel TSG can be considered to be 3 μs-5 μs, and in the pre-pulse recovery stage of the first read operation, the time from turn-on to turn-off of Unsel TSG can be considered to be 10 μs-20 μs.

[0074] Continuing to refer toFigure 8 During the read phase of read method 300, a drive voltage Vdr can be applied to BL, the Unsel TSG transistor remains off, and the Sel TSG transistor, BSG transistor, and Unsel WL remain on. During the read phase, pulsed read voltages Vpv1 and Vpv2 can be applied to SelWL. The values ​​of Vpv1 and Vpv2 can be less than the value of Vpass, which keeps Unsel WL on, to turn on unselected memory cells coupled to Unsel WL. Because the grain boundary traps of memory cell 306 receive sufficient charge replenishment during the pre-pulse recovery phase, the threshold voltage offset of memory cell 306 is improved. During the read phase of the first read operation, when the applied read voltages Vpv1 and Vpv2 read the selected memory cell, fewer FBCs will be generated.

[0075] The read method 300 also includes a pre-shutdown phase following the read phase. In the pre-shutdown phase, the drive voltage applied to the BL is stopped, keeping the BL voltage at a low potential, and the ACS is grounded. The read voltage applied to SelWL is increased to the Vpass voltage, which keeps UnselWL on, and SelTSG remains on, connecting the channel of the selected memory cell string to the low potential of the corresponding BL. The ACS remains grounded, allowing the charge in the channel of the selected memory cell string to be discharged via the ACS, thereby rapidly pulling the channel potential of the selected memory cell string down to a reference state to facilitate subsequent read or erase / write operations.

[0076] Figure 10 A schematic block diagram of a reading method 500 for the above-described non-volatile three-dimensional memory 100 according to some embodiments of this application is shown below, which will be discussed in conjunction with... Figures 10 to 12 The above reading method 500 is explained in detail.

[0077] like Figure 10 As shown, in the reading method 500, after the idle phase of the non-volatile three-dimensional memory, n read operations can be performed on the selected memory cell according to the received n read commands, where n ≥ 2 and is a positive integer. During the execution of the n read operations, the time from turn-on to turn-off of the selected memory cell in the pre-pulse recovery phase of the first read operation is controlled to be longer than the time from turn-on to turn-off in any pre-pulse recovery phase of the remaining n-1 read operations.

[0078] Similar operations as in the read method 300 can be performed in the pre-pulse phase of each read operation of the read method 500, which will not be repeated here. Taking the example of performing six read operations in succession, in the read method 500, the time for Sel WL to turn off from turning on to turning off in the pre-pulse recovery phase of the first read operation can be longer than the time for Sel WL to turn off from turning on to turning off in the pre-pulse recovery phase of any of the remaining five read operations. Optionally, the time for Sel WL to turn off from turning on to turning off in the pre-pulse recovery phase of the first read operation is t3, and t3 is in the range of 6 μs to 25 μs. In the pre-pulse recovery phase of the second read operation, the time for Sel WL to turn off from turning on to turning off is t4, and t4 is in the range of 1 μs to 5 μs. Optionally, t3 can be 2 μs to 6 μs longer than t4.

[0079] In some examples, in the pre-pulse recovery phase of the first read operation, a first turn-off voltage that decreases at a third slope can be applied to Sel WL; and in the pre-pulse recovery phase of any of the remaining five read operations, a second turn-off voltage that decreases at a fourth slope can be applied to Sel WL, where the absolute value of the third slope is smaller than the absolute value of the fourth slope. Illustratively, as shown in FIG. 5B, in the pre-pulse recovery phase of the first read operation, a first turn-off voltage Vcutl that decreases at a third slope k3 can be applied to Sel WL, and in the pre-pulse recovery phase of the second read operation, a second turn-off voltage Vcut2 that decreases at a fourth slope k4 can be applied to Sel WL. Illustratively, in the pre-pulse recovery phase, Unsel TSG can be turned off. Illustratively, the voltage generator 510 can be controlled to apply a select gate signal to the word line driver 509, which is the turn-off voltage applied to the DSL corresponding to Unsel TSG. The time for turning off Unsel TSG can be the same as the time t2 for turning off from turning on to turning off in the second read operation of the method 300, for example. Figure 11 Figure 4 Figure 4

[0080] In the read method 500, the memory controller 406 can send two read commands to the non-volatile three-dimensional memory 100 similar to the read method 500, such that the first read command triggers the control logic unit 512 to control the voltage generator 510 to generate the above-mentioned first turn-off voltage Vcutl that decreases at the third slope k3, and the second read command triggers the control logic unit 512 to control the voltage generator 510 to generate the above-mentioned first turn-off voltage Vcut2 that decreases at the fourth slope k4.

[0081] ​​​During the slow decrease of the first disconnect voltage Vcut1 applied to Sel WL, the grain boundary trap of the memory cell 306 is always controlled by the first disconnect voltage Vcut1. By controlling the slow decrease of Vcut1 to be relatively extended, the shallow grain boundary trap of the memory cell 306 can capture a sufficient number of electrons from the channel, thereby improving the threshold voltage offset of the memory cell 306, thus avoiding the first read phenomenon and improving the reliability of the non-volatile three-dimensional memory 100.

[0082] For method 500, Figure 12 A schematic diagram showing the relationship between the time t from Sel WL's on-to-off state and the FBC of multiple read operations is presented. The standby time of the non-volatile three-dimensional memory 100 is 30 minutes, and the standby temperature is 85°C. Figure 12 It can be seen that when t is between 0 and 20 μs, as t increases, the FBC1 generated in the first read operation is greater than the Base FBC generated in the subsequent five read operations. Furthermore, as t increases, the rate of decrease of FBC1 is faster than the rate of decrease of Base FBC. For the first read operation, when t ≥ 10 μs, FBC1 ≤ 800, while Base FBC is less than 800 when t ≤ 5 μs. Therefore, considering the read preparation time Tr and the influence of t on FBC1 and Base FBC under the aforementioned standby time and temperature, the time from Sel WL to disconnection in each pre-pulse recovery phase from the second to the sixth read operation can be considered to be 3 μs to 5 μs. In the pre-pulse recovery phase of the first read operation, the time from Sel WL to disconnection can be considered to be 10 μs to 20 μs.

[0083] The reading method 500 may include a reading phase and a shutdown phase similar to those of the reading method 300, which will not be described in detail in this application.

[0084] In some examples, methods 300 and 500 can be performed simultaneously. That is, while controlling the Unsel TSG to have a longer on-to-off time in the pre-pulse recovery phase of the first read operation than the on-to-off time in the pre-pulse recovery phase of the remaining n-1 read operations, the Sel WL to have a longer on-to-off time in the pre-pulse recovery phase of the first read operation than the on-to-off time in the pre-pulse recovery phase of the remaining n-1 read operations is also controlled. This application does not limit this.

[0085] In some examples, the row decoder (word line driver) 509 is a drive transistor, and the source of the drive transistor is applied with a first voltage signal by the voltage generator 510 when the non-volatile three-dimensional memory 100 is in an idle stage, such as in a standby state, so that the voltage of the source after the first voltage signal is applied is equal to the voltage of the drain as the output electrode D of the drive transistor. The source of the drive transistor is raised to the voltage equal to the drain by applying the first voltage signal, i.e. Vss = Vdd, which can effectively prevent the leakage of the drive transistor. At the first reading, the voltage of the word line is stabilized at Vdd without starting from a low voltage (such as 0V) to increase, so as to ensure that the channel charge of the storage unit 306 is kept in a stable state, and the FBC of the first reading is reduced.

[0086] The specific embodiments described above are further to the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reading from a non-volatile three-dimensional memory, the non-volatile three-dimensional memory comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells and a drain-select gate transistor, characterized in that, The method includes: After the idle phase of the non-volatile three-dimensional memory, based on the received n read commands, n read operations are performed on the selected memory cells included in the selected memory cell string, where n ≥ 2 and is a positive integer. During the execution of the n read operations, the drain-select gate transistor controlling the unselected memory cell string takes longer to turn on and off during the pre-pulse recovery phase of the first read operation than it does during any of the pre-pulse recovery phases of the remaining n-1 read operations.

2. The reading method according to claim 1, wherein, Each of the memory cell strings also includes a source-select gate transistor, and performing n read operations on selected memory cells included in the selected memory cell string includes: During the pre-pulse phase of each read operation, the drain-select gate transistor and the source-select gate transistor of each memory cell string are turned on.

3. The reading method according to claim 1, wherein, Controlling the drain-select gate transistor of the unselected memory cell string to have a longer on-to-off time during the pre-pulse recovery phase of the first read operation than the on-to-off time during any of the remaining n-1 read operations includes: During the pre-pulse recovery phase of the first read operation, a first turn-off voltage with a first decreasing slope is applied to the gate of the drain-select gate transistor of the unselected memory cell string; and During any of the pre-pulse recovery phases of the remaining n-1 read operations, a second turn-off voltage with a second decreasing slope is applied to the gate of the drain-select gate transistor of the unselected memory cell string. Wherein, the absolute value of the first slope is less than the absolute value of the second slope.

4. The reading method according to claim 1, wherein the non-volatile three-dimensional memory comprises multiple word lines, each word line being coupled to multiple memory cells in the same row of the multiple memory cell strings, wherein, Performing n read operations on the selected memory cells included in the selected memory cell string includes: During the pre-pulse phase of each read operation, a first pass voltage is applied to the word line corresponding to each row of memory cells; and During the pre-pulse recovery phase of each read operation, a disconnect voltage is applied to the word line corresponding to the selected memory cell.

5. The reading method according to claim 1, wherein, The time from turn-on to turn-off of the unselected memory cell string in the first read operation is 2μs-6μs longer than the time from turn-on to turn-off in any pre-pulse recovery phase of the remaining n-1 read operations.

6. Non-volatile three-dimensional memory, including: Multiple memory cell strings, each of the memory cell strings including multiple memory cells and drain-select-gate transistors; as well as The peripheral circuitry, coupled to the memory cell string, is configured as follows: After the idle phase of the non-volatile three-dimensional memory, n read commands are received to perform n read operations on the selected memory cells included in the selected memory cell string, where n ≥ 2 and is a positive integer. During the execution of the n read operations, the drain-select gate transistor controlling the unselected memory cell string takes longer to turn on and off during the pre-pulse recovery phase of the first read operation than it does during any of the pre-pulse recovery phases of the remaining n-1 read operations.

7. The non-volatile three-dimensional memory according to claim 6, wherein the memory cell string includes a source-select gate transistor, and the peripheral circuitry includes: A control logic unit, and a voltage generator and a word line driver respectively coupled to the control logic unit, wherein the control logic unit is configured to: During the pre-pulse phase of each read operation, the voltage generator is controlled to apply a select gate signal to the word line driver to apply an on-state voltage to the gates of the drain select gate transistor and the source select gate transistor of each memory cell string via the word line driver.

8. The non-volatile three-dimensional memory according to claim 7, wherein, The control logic unit is configured as follows: During the pre-pulse recovery phase of each read operation, the voltage generator is controlled to apply a first drain select gate signal to the word line driver to apply a first turn-off voltage with a first slope decreasing to the gate of the drain select gate transistor of the unselected memory cell string via the word line driver. as well as During any pre-pulse recovery phase of the remaining n-1 read operations, the voltage generator is controlled to apply a second drain-select gate signal to the word line driver to apply a second turn-off voltage with a second decreasing slope to the gate of the drain-select gate transistor of the unselected memory cell string via the word line driver. Wherein, the absolute value of the first slope is less than the absolute value of the second slope.

9. A memory system, including: The non-volatile three-dimensional memory as described in claim 6, wherein the non-volatile three-dimensional memory is configured to store data; A memory controller, coupled to the non-volatile three-dimensional memory, is configured to issue the read command to the peripheral circuitry.

10. The memory system of claim 9, comprising: Solid-state drive or memory card.

11. A method for reading from a non-volatile three-dimensional memory, the non-volatile three-dimensional memory comprising a plurality of storage cells, characterized in that, The method includes: After the idle phase of the non-volatile three-dimensional memory, n read operations are performed on the selected memory cell according to the received n read commands, where n ≥ 2 and is a positive integer. During the execution of the n read operations, the selected memory cell is controlled to have a longer time from being turned on to being turned off during the pre-pulse recovery phase of the first read operation than the time from being turned on to being turned off during any of the pre-pulse recovery phases of the remaining n-1 read operations.

12. The reading method according to claim 11, wherein the non-volatile three-dimensional memory comprises multiple word lines, each word line being coupled to multiple memory cells in the same row, wherein, Performing n read operations on the selected storage unit includes: During the pre-pulse phase of each read operation, a pass voltage is applied to the word line corresponding to each row of the memory cell.

13. The reading method according to claim 11, wherein, Controlling the selected memory cell to have a longer on-to-off time during the pre-pulse recovery phase of the first read operation than the on-to-off time during any of the remaining n-1 read operations includes: During the pre-pulse recovery phase of the first read operation, a first disconnect voltage with a third decreasing slope is applied to the word line corresponding to the selected memory cell; and During any of the pre-pulse recovery phases of the remaining n-1 read operations, a second disconnect voltage with a fourth decreasing slope is applied to the word line corresponding to the selected memory cell. The absolute value of the third slope is less than the absolute value of the fourth slope.

14. The read method according to claim 11, wherein the non-volatile three-dimensional memory further comprises a memory cell string composed of a plurality of said memory cells connected in series, each memory cell string comprising a drain-select gate transistor and a source-select gate transistor, wherein, Performing n read operations on the selected storage unit includes: During the pre-pulse phase of each read operation, the drain-select gate transistor and the source-select gate transistor of each memory cell string are turned on; and During the pre-pulse recovery phase of each read operation, the drain-select gate transistor of the unselected memory cell string is turned off.

15. The reading method according to claim 11, wherein, The selected storage cell is controlled to have a turn-on to turn-off time during the pre-pulse recovery phase of the first read operation that is 2μs-6μs longer than the turn-on to turn-off time during any of the pre-pulse recovery phases of the remaining n-1 read operations.

16. Non-volatile three-dimensional memory, including: Multiple storage unit strings, each of the storage unit strings comprising multiple storage units; as well as The peripheral circuitry, coupled to the memory cell string, is configured as follows: After the idle phase of the non-volatile three-dimensional memory, n read commands are received to perform n read operations on selected memory cells included in the selected memory cell string, where n ≥ 2 and is a positive integer. During the execution of the n read operations, the selected memory cell is controlled to have a longer time from being turned on to being turned off during the pre-pulse recovery phase of the first read operation than the time from being turned on to being turned off during any of the pre-pulse recovery phases of the remaining n-1 read operations.

17. The non-volatile three-dimensional memory according to claim 16, wherein the non-volatile three-dimensional memory comprises a plurality of word lines, each word line being coupled to a plurality of memory cells in the same row, and the peripheral circuitry comprising: The control logic unit includes a voltage generator and a word line driver coupled to the control logic unit, the word line driver being coupled to the word line, and the control logic unit is configured to: During the pre-pulse phase of each read operation, the voltage generator is controlled to apply a word line signal to the word line driver to apply a pass voltage to the word line corresponding to each row of memory cells via the word line driver.

18. The non-volatile three-dimensional memory according to claim 17, wherein, The control logic unit is configured as follows: During the pre-pulse recovery phase of each read operation, the voltage generator is controlled to apply a first word line signal to the word line driver to apply a first disconnect voltage with a third slope to the word line corresponding to the selected memory cell via the word line driver. as well as During any pre-pulse recovery phase of the remaining n-1 read operations, the voltage generator is controlled to apply a second word line signal to the word line driver to apply a second disconnect voltage with a fourth decreasing slope to the word line corresponding to the selected memory cell via the word line driver. The absolute value of the third slope is less than the absolute value of the fourth slope.

19. A memory system, comprising: The non-volatile three-dimensional memory as described in claim 16, wherein the non-volatile three-dimensional memory is configured to store data; as well as A memory controller, coupled to a non-volatile three-dimensional memory, is configured to issue the read command to the peripheral circuitry.

20. The memory system of claim 19, comprising: Solid-state drive or memory card.

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