Memory device with dynamic program verify levels

Abstract

This application relates to memory devices with dynamic program verify levels. A memory device can include an array of memory cells and a controller configured to access the array of memory cells. The controller can sense a first threshold voltage of a selected memory cell. In response to the sensed first threshold voltage being between a first pre-program verify level and a first program verify level, the controller can bias the selected memory cell for SSPC programming. The first pre-program verify level can be less than a final pre-program verify level, and the first program verify level can be less than a final program verify level. In response to the sensed first threshold voltage being less than the first pre-program verify level, the controller can bias the selected memory cell for non-SSPC programming. In response to the sensed first threshold voltage being greater than the first program verify level, the controller can inhibit the selected memory cell from programming.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 131,823, filed on December 30, 2020, which is hereby incorporated in its entirety by reference. Technical Field

[0003] This disclosure generally relates to memory, and more particularly, in one or more embodiments, to dynamic pre-programming verification and programming verification levels within a memory device. Background Technology

[0004] Memory (e.g., memory devices) is typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has become a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells with high memory density, high reliability, and low power consumption. By programming (often referred to as writing) a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase transitions or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., the data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, hence the term refers to the logical form arranged by the basic memory cell configuration. Typically, the memory cell array of a NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns of the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates (e.g., source select transistors and drain select transistors). Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate are known between the memory cell string and the source and / or between the memory cell string and the data line.

[0007] When programming memory, memory cells are typically programmed as either single-level cells (SLCs) or multi-level cells (MLCs). An SLC can use a single memory cell to represent a data digit (e.g., a bit). For example, in an SLC, a Vt of 2.5V can indicate a programmed memory cell (e.g., representing logic 0), while a Vt of -0.5V can indicate an erased cell (e.g., representing logic 1). As an example, the erased state in an SLC can be represented by any threshold voltage less than or equal to 0V, while the programmed data state can be represented by any threshold voltage greater than 0V.

[0008] MLCs use more than two Vt ranges, each indicating a different data state. It is well known that margins such as dead time (e.g., a certain number of volts) can separate adjacent Vt ranges, for example, to distinguish data states. Multilevel cells can utilize the analog characteristics of conventional non-volatile memory cells to assign bit patterns to specific Vt ranges. While MLCs typically use memory cells to represent one data state in binary numbers (e.g., 4, 8, 16, ...), memory cells used for MLC operation can be used to represent non-binary data states. For example, in the case where an MLC uses three Vt ranges, two memory cells can be used together to represent one of eight data states.

[0009] When programming MLC memory, data values ​​are typically programmed in multiple passes, for example, programming one or more numbers in each pass. For instance, in a four-level MLC (often simply called an MLC), a first number (e.g., the least significant bit (LSB)) typically referred to as fast page (LP) data can be programmed into the memory cell in the first pass, resulting in two (e.g., first and second) threshold voltage ranges. Subsequently, a second number (e.g., the most significant bit (MSB)) typically referred to as slow page (UP) data can be programmed into the memory cell in the second pass, typically moving a portion of those memory cells in the first threshold voltage range to the third threshold voltage range and a portion of those memory cells in the second threshold voltage range to the fourth threshold voltage range. Similarly, an eight-level MLC (often called a TLC) can represent a three-bit pattern comprising: a first number, such as the least significant bit (LSB) or fast page (LP) data; a second number, such as slow page (UP) data; and a third number, such as the most significant bit (MSB) or extra page (XP) data. When operating a TLC, LP data can be programmed into memory cells in the first pass, resulting in two threshold voltage ranges. Then, UP and XP data are programmed in the second pass, resulting in eight threshold voltage ranges. Similarly, a 16-level MLC (often referred to as a QLC) can represent a four-bit mode, while a 32-level MLC (often referred to as a PLC) can represent a five-bit mode.

[0010] A read window, also known as the read window width, refers to the distance (e.g., in voltage form) between adjacent Vt distributions at a specific localization error rate (BER). The read window budget (RWB) can refer to the cumulative value of read windows across a set of programmed cells (e.g., one or more pages). For example, a TLC memory cell configured to store three bits of data per cell can be programmed to be one of eight different Vt distributions, each corresponding to a specific data state. In this example, the RWB could be the cumulative value (e.g., in voltage form) of seven read windows across the eight Vt distributions. Summary of the Invention

[0011] In one aspect, this application provides a memory device comprising: a memory cell array; and a controller configured to access the memory cell array to program selected memory cells in the memory cell array to a target level, wherein the controller is further configured to: sense a first threshold voltage of the selected memory cells; bias the selected memory cells for selective slow programming convergence (SSPC) programming in response to the sensed first threshold voltage being between a first pre-programming verification level and a first programming verification level, wherein the first pre-programming verification level is less than a final pre-programming verification level and the first programming verification level is less than a final programming verification level; bias the selected memory cells for non-SSPC programming in response to the sensed first threshold voltage being less than the first pre-programming verification level; disable programming of the selected memory cells in response to the sensed first threshold voltage being greater than the first programming verification level; and apply a specific programming pulse to the selected memory cells.

[0012] In another aspect, this application provides a memory device comprising: a memory cell array; and a controller configured to access the memory cell array to program selected memory cells in the memory cell array, wherein the controller is further configured to: apply a specific programming pulse to the selected memory cell; sense whether the selected memory cell has been programmed to a first programming verification level lower than a final programming verification level; apply a first subsequent programming pulse to the selected memory cell; sense whether the selected memory cell has been programmed to a second programming verification level lower than the final programming verification level and greater than the first programming verification level; apply a second subsequent programming pulse to the selected memory cell; and sense whether the selected memory cell has been programmed to the final programming verification level.

[0013] In another aspect, this application provides a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of access lines, each of the plurality of access lines being connected to a control gate of a corresponding memory cell in each of the plurality of serially connected memory cell strings; and a controller configured to program each corresponding memory cell connected to a selected access line of the plurality of access lines to a corresponding target level, wherein the controller is further configured to: sense a first threshold voltage of each corresponding memory cell connected to the selected access line; and, in response to the sensed first threshold voltage of each corresponding memory cell connected to the selected access line being greater than a first programming verification level of the corresponding memory cell, disable programming of the corresponding memory cell, wherein the first programming verification level of the corresponding memory cell is less than the first threshold voltage of the selected access line. The following steps are taken: a final programming verification level for the corresponding memory cell; enabling programming of the corresponding memory cell in response to a sensed first threshold voltage of each corresponding memory cell connected to the selected access line being less than the first programming verification level of the corresponding memory cell; applying a specific programming pulse to the selected access line; sensing a second threshold voltage of each corresponding memory cell connected to the selected access line; disabling programming of the corresponding memory cell in response to a sensed second threshold voltage of each corresponding memory cell connected to the selected access line being greater than the final programming verification level of the corresponding memory cell; enabling programming of the corresponding memory cell in response to a sensed second threshold voltage of each corresponding memory cell connected to the selected access line being less than the final programming verification level of the corresponding memory cell; and applying a first subsequent programming pulse to the selected access line. Attached Figure Description

[0014] Figure 1 This is a simplified block diagram of a memory that communicates with a processor as part of an electronic system, according to an embodiment.

[0015] Figure 2A-2C It can be used for reference. Figure 1 A schematic diagram of a portion of the memory cell array in the memory of the aforementioned type.

[0016] Figure 3 A group of memory cells of a TLC memory according to an embodiment is described.

[0017] Figure 4 This is a timing diagram depicting a portion of a programming operation that programs a selected TLC memory cell to a target threshold voltage, according to an embodiment.

[0018] Figure 5A group of memory cells is depicted during a programming operation that programs selected memory cells to a target level, according to an embodiment.

[0019] Figure 6 A group of memory cells is depicted during a programming operation that programs selected memory cells to a target level, according to another embodiment.

[0020] Figure 7 A group of memory cells of a TLC memory is depicted according to an embodiment during a programming operation that programs selected TLC memory cells to a target threshold voltage.

[0021] Figures 8A-8D This is a flowchart of a method for operating a memory according to an embodiment.

[0022] Figure 9A and 9B This is a flowchart of a method for operating a memory according to another embodiment.

[0023] Figure 10A-10D This is a flowchart of a method for operating a memory according to another embodiment. Detailed Implementation

[0024] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and in which specific embodiments are illustrated by way of description. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded in a limiting sense.

[0025] For example, as used herein, the term "semiconductor" can refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0026] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0027] This article should recognize that even when expected values ​​are equal, the variability and precision of industrial processing and operation can lead to differences from the expected values. These variability and precision typically depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then these values ​​are considered equal regardless of their actual results.

[0028] Figure 1 This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100 according to an embodiment, which communicates as part of a third device in the form of an electronic system with a second device in the form of a processor 130. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and so on. The processor 130 is, for example, a controller external to the memory device 100; it can be a memory controller or another external host device.

[0029] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access lines (often referred to as word lines), while memory cells in logical columns are typically selectively connected to the same data lines (often referred to as bit lines). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the image) can be programmed into one of at least two target data states.

[0030] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 100 and outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0031] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a group of memory cells in memory cell array 104, e.g., a reserved block of memory cells.

[0032] Control logic 116 can also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, as directed by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; new data from I / O control circuitry system 112 can then be latched in cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry system 112 for output to external processor 130; new data can then be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 can form a page buffer of memory device 100 (e.g., can form a portion thereof). The page buffer can further include sensing devices ( Figure 1(Not shown in the image) is used to sense the data status of memory cells in memory cell array 104, for example, by sensing the status of data lines connected to the memory cells. Status register 122 can communicate with I / O control circuitry system 112 and control logic 116 to latch status information for output to processor 130.

[0033] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may also be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134, and outputs data to the processor 130 via I / O bus 134.

[0034] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then the commands can be written to command register 124. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then the addresses can be written to address register 114. Data can be received via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device at I / O control circuitry system 112, and then the data can be written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and the data can be written directly to data register 120. Data can also be output via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device. While references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via an external device (e.g., processor 130).

[0035] Those skilled in the art should understand that additional circuitry and signals can be provided, and Figure 1 The memory device 100 has been simplified. It should be recognized that the reference... Figure 1The functionality of the described individual block components may not necessarily need to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be used to perform... Figure 1 The functionality can exceed that of a single block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0036] Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0037] Figure 2A It can be used for reference. Figure 1 A schematic diagram of a portion of a memory cell array 200A (e.g., a NAND memory array) of the aforementioned type, for example, as part of memory cell array 104. Memory array 200A includes access lines (e.g., word lines) 2020 to 202... N and data lines (e.g., bit lines) 2040 to 204 M Access line 202 can be connected to a global access line (e.g., a global word line) in a many-to-one relationship. Figure 2A Not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity, for example forming a p-well, or n-type conductivity, for example forming an n-well.

[0038] The memory array 200A can be arranged in rows (each row corresponds to access lines 202) and columns (each column corresponds to data lines 204). Each column can contain a string of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and further include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory and are often alternatively incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0039] The memory cells 208 of each NAND string 206 may be connected in series between select gate 210 (e.g., a field-effect transistor) and select gate 212 (e.g., a field-effect transistor), wherein the select gate 210 is, for example, select gate 2100 to 210. M One of them (e.g., a source-select transistor, often referred to as a select-gate-source transistor), wherein the select gate 212 is, for example, select gates 2120 to 212. M One of them (for example, a drain-select transistor, often referred to as a select-gate drain). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0040] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0041] The drain of each select gate 212 can be connected to the data line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the selected gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0042] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally flat structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2AThe memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the data line 204, and the data line can extend substantially parallel to the plane containing the common source 216.

[0043] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as Figure 2A As shown in the diagram. Data storage structure 234 may include conductive and dielectric structures, while control gate 236 is generally formed of one or more conductive materials. In some cases, memory cell 208 may further have defining source / drain (e.g., source) 230 and defining source / drain (e.g., drain) 232. Memory cells 208 connect their control gate 236 to (and in some cases form) access lines 202.

[0044] A column of memory cells 208 may be one or more NAND strings 206 selectively connected to a given data line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may, but need not, contain all memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given access line 202. For example, commonly connected to access line 202 N Memory cells 208, selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.), can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while being commonly connected to access line 202. N Memory cells 208, selectively connected to odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.), can be another physical page of memory cell 208 (e.g., odd-numbered memory cells). Although data lines 2043-2045 are... Figure 2A Although not explicitly depicted in the diagram, it is clear from the figure that the data lines 204 of the memory cell array 200A can be consecutively numbered from data line 2040 to data line 204. MOther groups of memory cells 208 commonly connected to a given access line 202 may also define physical pages of memory cells 208. For a given memory device, all memory cells commonly connected to a given access line may be considered physical pages of the memory cells. A portion of the physical page of a memory cell (e.g., the upper or lower page of the memory cell) that is read during a single read operation or programmed during a single programmable operation (in some embodiments, it may still be an entire row) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, reference to a memory cell page herein refers to a memory cell within a memory cell logical page.

[0045] Although discussed in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0046] Figure 2B It can be used for reference. Figure 1 Another schematic diagram of a portion of the memory cell array 200B in the memory of the aforementioned type, for example, as part of the memory cell array 104. Figure 2B The similar numbered elements in the text correspond to, for example, regarding... Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may have a vertical structure, which may include semiconductor pillars, a portion of which may serve as channel regions for the memory cells of the NAND string 206. The NAND string 206 may be selectively connected to data lines 2040-204 via select transistors 212 (e.g., which may be drain select transistors, commonly referred to as select gate drain). M And selectively connected to the common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of NAND strings 206 can be connected via select lines 2150-215. KBias selectively activates specific select transistors 212, each located between NAND string 206 and data line 204, to connect to their respective data lines 204. Select transistors 210 can be activated by biasing select line 214. Each access line 202 can be connected to multiple rows of memory cells in memory array 200B. Multiple rows of memory cells that are commonly connected to each other via specific access lines 202 can be collectively referred to as a layer.

[0047] A three-dimensional NAND memory array 200B may be formed above a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used to access the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor structure due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0048] Figure 2C It can be used as a reference, for example, as part of memory cell array 104. Figure 1 Another schematic diagram of a portion of the memory cell array 200C in the memory of the aforementioned type. Figure 2C Elements with similar numbers in the middle correspond to about Figure 2A The provided description indicates that the memory cell array 200C may include a series-connected string of memory cells (e.g., a NAND string) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216, as shown below. Figure 2A As depicted in the diagram. For example, a portion of memory cell array 200A may be a portion of memory cell array 200C. Figure 2C The NAND string is divided into 206 segments to form memory cell blocks 250, for example, memory cell blocks 2500-250. L Memory cell block 250 may be a group of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 that are associated with a single select line 215, such as select line 2150. The source 216 of memory cell block 250 may be associated with memory cell block 250. L The source 216 are all from the same source. For example, each memory cell block 2500-250 LThey can be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 may not be directly connected to memory cell blocks 2500-250 respectively. L Access lines 202 and select lines 214 and 215 for any other memory cell blocks.

[0049] Data cable 2040-204 M It can be connected (e.g., selectively connected) to buffer section 240, which may be part of a data buffer for memory. Buffer section 240 may correspond to a memory plane (e.g., a set of memory cell blocks 2500-250). L ). Buffer section 240 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the image).

[0050] although Figure 2C Each memory cell block 250 is depicted with only one select line 215, but the memory cell block 250 may contain NAND strings 206 that are associated with more than one select line 215. For example, the select line 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2B Selection line 2151-215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 commonly associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to the buffer section 240 in response to its respective select line 215.

[0051] Figure 3 A group of memory cells 300 according to an embodiment is depicted. For simplicity, Figure 3 and afterwards Figure 4-7 The programming operations of TLC memory cells will be assumed to be, for example, an eight-level memory cell using eight threshold voltage ranges to represent data states L0, L1, L2, L3, L4, L5, L6, and L7, each threshold voltage range representing a data state corresponding to a three-digit mode. Although discussed with reference to TLC memory cells, the same applies to programming operations performed on memory cells with lower storage density (e.g., SLC (two data states)) or higher storage density (e.g., QLC (16 data states) or PLC (32 data states) memory cells).

[0052] In this example, memory cell group 310 may be an erased memory cell and represent the logical data value '111', memory cell group 311 may represent the logical data value '011', memory cell group 312 may represent the logical data value '001', memory cell group 313 may represent the logical data value '101', memory cell group 314 may represent the logical data value '100', memory cell group 315 may represent the logical data value '000', memory cell group 316 may represent the logical data value '010', and memory cell group 317 may represent the logical data value '110'. The rightmost digit may represent fast page data of a memory cell having a threshold voltage within the threshold voltage range of its respective memory cell group, the middle digit may represent slow page data of the memory cell, and the leftmost digit may represent additional page data of the memory cell. Although a specific example of binary representation is provided, embodiments may use other arrangements of bit patterns to represent various data states.

[0053] The read window indication between memory cell groups 310 and 311 is 320, which is the distance (e.g., in voltage form) between the neighboring Vt distributions of memory cells representing data states L0 and L1. The read window indication between memory cell groups 311 and 312 is 321, which is the distance (e.g., in voltage form) between the neighboring Vt distributions of memory cells representing data states L1 and L2. Similarly, the read windows between memory cell groups 312, 313, 314, 315, and 316 and memory cell groups 313, 314, 315, 316, and 317 are indicated as 322, 323, 324, 325, and 326, respectively, which are the distances between the neighboring Vt distributions of memory cells representing data states L2, L3, L4, L5, L6, and L7. The read window budget (RWB) may refer to the cumulative value of the read windows of a set of programmed cells (e.g., one or more pages of cells). In this example, RWB can be the cumulative value (e.g., in voltage form) of the seven reading windows 320-326 between the eight Vt distributions.

[0054] Figure 4 According to the description of the embodiment, selected TLC memory cells are programmed to target levels L0 to L7 (e.g., as shown in the example). Figure 3This is a timing diagram of a portion of the programming operation shown. Once the selected memory cell has been programmed to its target level, further programming of the memory cell is prohibited. Before time t0, the selected memory cell for programming can be erased such that each selected memory cell has a threshold voltage corresponding to level L0. At time t0, a first programming pulse is applied to the selected access line (e.g., 236) connected to the control gate (e.g., 208) of the selected memory cell (e.g., 208). Figure 2A (202). After the first programming pulse, a programming verification operation can be performed to verify whether the target group of selected memory cells has been programmed to level L1 or L2. At time t1, a second programming pulse, for example higher than the first programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the second programming pulse, a programming verification operation can be performed to verify whether the target group of selected memory cells has been programmed to level L1 or L2.

[0055] At time t2, a third programming pulse, for example higher than the second programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the third programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L1, L2, or L3. At time t3, a fourth programming pulse, for example higher than the third programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the fourth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L2, L3, or L4. At time t4, a fifth programming pulse, for example higher than the fourth programming pulse, is applied to the selected access line connected to the control gate of the selected memory cell. After the fifth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L2, L3, L4, or L5.

[0056] At time t5, a sixth programming pulse, for example higher than the fifth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the sixth programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L3, L4, L5, or L6. At time t6, a seventh programming pulse, for example higher than the sixth programming pulse, is applied to a selected access line connected to the control gate of the selected memory cell. After the seventh programming pulse, a programming verification operation can be performed to verify whether the target group of the selected memory cells has been programmed to level L3, L4, L5, L6, or L7. At time t7, an eighth programming pulse, for example higher than the seventh programming pulse, can be applied to a selected access line connected to the control gate of the selected memory cell, and this process can be repeated until the selected memory cells have been programmed to their target levels.

[0057] Figure 5 A group of memory cells is depicted during a programming operation that programs selected memory cells to a target level, according to an embodiment. Figure 5 This includes the group of memory cells following the specific programming pulse indicated at 340, the group of memory cells following the first subsequent programming pulse indicated at 342, and the group of memory cells following the second subsequent programming pulse indicated at 344. Although Figure 5 The illustration shows a group of memory cells being programmed to a target level after three programming pulses. However, in other instances, any suitable number of programming pulses can be used to program the group of memory cells to the target level. The specific programming pulse can be the first programming pulse of the programming operation or a subsequent programming pulse. The first subsequent programming pulse may immediately follow the specific programming pulse, and the second subsequent programming pulse may immediately follow the first subsequent programming pulse. For example, refer back to the reference. Figure 4 For the target level L3, the specific pulse can be the third programming pulse at time t2, the first subsequent programming pulse can be the fourth programming pulse at time t3, and the second subsequent programming pulse can be the fifth programming pulse at time t4.

[0058] In a programming scheme known as Selective Slow Programming Convergence (SSPC), different voltage levels may be used on the data lines to enable programming. Memory cells closer to their expected data states (e.g., partially enabled programming) are programmed more slowly than those farther away (e.g., fully enabled programming), while receiving the same voltage level at their respective control gates. The target level may correspond to a minimum threshold voltage (PV) of the target level. TARGET 350, which can be referred to as the final programming verification level of the target level. Final Pre-programmed Verification Level (PPV) TARGET 352 can be selected to be less than the final pre-programming verification level 350 to enable SSPC programming. Following the specific programming pulse, a programming verification operation is performed to sense the threshold voltage of each memory cell within the memory cell group 340. Memory cells with threshold voltages less than the final pre-programming verification level 352 are biased for non-SSPC programming. Memory cells with threshold voltages between the final pre-programming verification level 352 and the final programming verification level 350 are biased for SSPC programming because the memory cells fall within the SSPC range indicated at 354. Memory cells with threshold voltages greater than the final programming verification level 350 are disabled for further programming.

[0059] When each memory cell within memory cell group 340 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a first subsequent programming pulse is applied to memory cell group 340 to provide memory cell group 342. Following the first subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell group 342. Memory cells with threshold voltages less than the final pre-programming verification level 352 (e.g., no memory cells in this example) are biased for non-SSPC programming. Memory cells with threshold voltages between the final pre-programming verification level 352 and the final programming verification level 350 are biased for SSPC programming because the memory cells are within the SSPC range 354. Memory cells with threshold voltages greater than the final programming verification level 350 are disabled for further programming.

[0060] When each memory cell within memory cell group 342 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a second subsequent programming pulse is applied to memory cell group 342 to provide memory cell group 344. Following the second subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell group 344. Memory cells with threshold voltages less than the final pre-programming verification level 352 (e.g., no memory cells in this example) are biased for non-SSPC programming. Memory cells with threshold voltages between the final pre-programming verification level 352 and the final programming verification level 350 (e.g., no memory cells in this example) are biased for SSPC programming. Memory cells with threshold voltages greater than the final programming verification level 350 (e.g., all memory cells in this example) are disabled for further programming.

[0061] During a programming pulse, a memory cell can be biased for SSPC programming by biasing the data line connected to the memory cell to an SSPC level. During a programming pulse, a memory cell can be biased for non-SSPC programming by biasing the data line connected to the memory cell to a non-SSPC level. During a programming pulse, a memory cell can be disabled from programming by biasing the data line connected to the memory cell to an disable level. The SSPC level (e.g., 1V) can be greater than the non-SSPC level (e.g., 0V) and less than the disable level (e.g., 3V).

[0062] The state width of a memory cell group is the difference between the minimum and maximum threshold voltages of the memory cell group programmed to the target level. The state width of memory cell group 344 is indicated as 356. State width affects RWB. A larger state width results in a smaller RWB, while a smaller state width results in a larger RWB. Therefore, it may be necessary to reduce the state width of the memory cell group to improve the RWB, as referenced below. Figure 6 As described.

[0063] Figure 6 A group of memory cells is depicted during a programming operation that programs selected memory cells to a target threshold voltage, according to another embodiment. Figure 6 This includes the group of memory cells following the specific programming pulse indicated at 360, the group of memory cells following the first subsequent programming pulse indicated at 362, and the group of memory cells following the second subsequent programming pulse indicated at 364. Although Figure 6 The illustration shows a group of memory cells being programmed to a target level after three programming pulses. However, in other instances, any suitable number of programming pulses can be used to program the group of memory cells to the target level. The specific programming pulse can be the first programming pulse of the programming operation or a subsequent programming pulse. The first subsequent programming pulse may immediately follow the specific programming pulse, and the second subsequent programming pulse may immediately follow the first subsequent programming pulse. For example, refer back to the reference. Figure 4 For the target level L3, the specific pulse can be the third programming pulse at time t2, the first subsequent programming pulse can be the fourth programming pulse at time t3, and the second subsequent programming pulse can be the fifth programming pulse at time t4.

[0064] The target level can correspond to the minimum threshold voltage (PV) of the target level. TARGET )370, which can be called the final programming verification level of the target level. Final pre-programmed verification level (PPV) TARGET )372 can be selected to be less than the final programming verification level 370 to enable SSPC programming. However, compared to Figure 5 An embodiment further includes a first programming verification level (PV1) 380 selected to be less than the final programming verification level 370 and a first pre-programming verification level (PPV1) 382 selected to be less than the final pre-programming verification level 372. In one instance, the first programming verification level 380 may be equal to the final programming verification level 370 minus 1V.

[0065] although Figure 6The diagram illustrates two programming verification levels 370 and 380 and two corresponding pre-programming verification levels 372 and 382. However, in other embodiments, more than two programming verification levels and more than two corresponding pre-programming verification levels may be used. For example, one, two, three, or more additional programming verification levels may be included between the first programming verification level 380 and the final programming verification level 370, and additional corresponding pre-programming verification levels may be included between the first pre-programming verification level 382 and the final pre-programming verification level 372. The additional programming verification levels may be equally spaced between the first programming verification level 380 and the final programming verification level 370, and the additional corresponding pre-programming verification levels may be equally spaced between the first pre-programming verification level 382 and the final pre-programming verification level 372.

[0066] Following the specific programming pulse, a programming verification operation is performed to sense the threshold voltage of each memory cell within the memory cell group 360. Memory cells with threshold voltages less than the first pre-programming verification level 382 are biased for non-SSPC programming. Memory cells with threshold voltages between the first pre-programming verification level 382 and the first programming verification level 380 are biased for SSPC programming because the memory cells fall within the first SSPC range indicated at 384. Memory cells with threshold voltages greater than the first programming verification level 380 are disabled for programming.

[0067] When each memory cell within memory cell group 360 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a first subsequent programming pulse is applied to memory cell group 360 to provide memory cell group 362. Following the first subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell group 362. Memory cells with threshold voltages less than the final pre-programming verification level 372 are biased for non-SSPC programming. Memory cells with threshold voltages between the final pre-programming verification level 372 and the final programming verification level 370 are biased for SSPC programming because the memory cell falls within the final SSPC range indicated at 374. Memory cells with threshold voltages greater than the final programming verification level 370 are disabled for further programming.

[0068] When each memory cell within memory cell group 362 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a second subsequent programming pulse is applied to memory cell group 362 to provide memory cell group 364. Following the second subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell group 364. Memory cells with threshold voltages less than the final pre-programming verification level 372 (e.g., no memory cells in this example) are biased for non-SSPC programming. Memory cells with threshold voltages between the final pre-programming verification level 372 and the final programming verification level 370 (e.g., no memory cells in this example) are biased for SSPC programming. Memory cells with threshold voltages greater than the final programming verification level 370 (e.g., all memory cells in this example) are disabled for further programming.

[0069] exist Figure 6 In one embodiment, the first pre-programming verification level 382 and the first programming verification level 380 are used for programming verification operations after the specific programming pulse, and the final pre-programming verification level 372 and the final programming verification level 370 are used for programming verification operations after the first subsequent programming pulse. In embodiments using additional pre-programming verification levels and corresponding programming verification levels, the pre-programming verification level and programming verification level for each programming verification operation are increased for each subsequent programming pulse until the final pre-programming verification level 372 and the final programming verification level 370 are reached. Compared to Figure 5 In some embodiments, these dynamic pre-programming verification and programming verification levels increase the number of memory cells within the SSPC range (e.g., SSPC range 384 or 374), thereby slowing down the programming of the increased number of memory cells. By slowing down the programming of the increased number of memory cells, the memory cell group 364 has a smaller overshoot within the final programming verification level 370.

[0070] The state width indication for the group of 364 memory cells programmed to the target level is 386. Compared to... Figure 5 The state width of memory cell group 344 is 356, while the state width of memory cell group 364 is 386, which is smaller. Therefore, compared to according to Figure 5 Compared to RWB of memory cell groups programmed using fixed pre-programmed verification and programming verification levels, according to Figure 6 The RWB of memory cell groups using dynamic pre-programmed verification and programmed verification level programming has been improved.

[0071] Figure 7The diagram depicts a group of memory cells 400 of a TLC memory during a programming operation that programs selected TLC memory cells to a target threshold voltage, according to an embodiment. After programming is complete, group 410 is programmed (e.g., erased) to level L0, group 411 is programmed to level L1, group 412 is programmed to level L2, group 413 is programmed to level L3, group 414 is programmed to level L4, group 415 is programmed to level L5, group 416 is programmed to level L6, and group 417 is programmed to level L7.

[0072] In this example, at least four programming pulses are used to program memory cell groups 411-417. However, in other examples, fewer than four or more programming pulses may be used, and the number of programming pulses may depend on the type of programmable memory (e.g., SLC, QLC, PLC). Figure 7 It also includes memory cell groups 421-427 after a specific programming pulse, memory cell groups 431-437 after a first subsequent programming pulse, and memory cell groups 441-447 after a second subsequent programming pulse, wherein memory cell groups 411-417 may be reached after a third subsequent programming pulse. Although Figure 7 This illustration shows that each group of memory cells is programmed to the target level after at least four programming pulses. However, in other instances, any suitable number of programming pulses can be used to program each group of memory cells to the target level. A first subsequent programming pulse may immediately follow the specific programming pulse, a second subsequent programming pulse may immediately follow the first subsequent programming pulse, and a third subsequent programming pulse may immediately follow the second subsequent programming pulse.

[0073] The first programming verification level for each level, L1 to L7, is indicated as PV. L1,1 To PV L7,1 The second programming verification level for each level, L1 to L7, is indicated as PV. L1,2 To PV L7,2 The final programming verification level for each level, L1 to L7, is indicated as PV. L1 To PV L7 Each first programming verification level PV L1,1 To PV L7,1 It can be selected to be less than the corresponding second programming verification level PV L1,2 To PV L7,2 And each second programming verification level PV L1,2 To PV L7,2 It can be selected to be less than the corresponding final programming verification level PV. L1 To PV L7 .Although Figure 7Not shown, but each programming verification level may correspond to a corresponding pre-programmed verification level as previously described to enable SSPC programming. Although Figure 7 The diagram shows three programming verification levels for each target level L1 to L7, but in other embodiments, more than three programming verification levels (and more than three corresponding pre-programmed verification levels) may be used.

[0074] Following the specific programming pulse, a programming verification operation is performed to sense the threshold voltage of each memory cell within memory cell groups 421-427. Memory cells with threshold voltages lower than the corresponding first pre-programming verification level are biased for non-SSPC programming. The threshold voltage is at the corresponding first pre-programming verification level and the corresponding first programming verification level PV. L1,1 To PV L7,1 The memory cells between are biased for SSPC programming. The threshold voltage is greater than the corresponding first programming verification level PV. L1,1 To PV L7,1 The memory cells are prohibited from being programmed.

[0075] When each memory cell within memory cell groups 421-427 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a first subsequent programming pulse is applied to memory cell groups 421-427 to provide memory cell groups 431-437. Following the first subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell groups 431-437. Memory cells with threshold voltages lower than the corresponding second pre-programming verification level are biased for non-SSPC programming. The threshold voltage is at the corresponding second pre-programming verification level and the second programming verification level PV. L1,2 To PV L7,2 The memory cells between them are biased for SSPC programming. The threshold voltage is greater than the corresponding second programming verification level PV. L1,2 To PV L7,2 The memory cells are prohibited from being programmed.

[0076] When each memory cell within memory cell groups 431-437 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a second subsequent programming pulse is applied to memory cell groups 431-437 to provide memory cell groups 441-447. Following the second subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell groups 441-447. Memory cells with threshold voltages lower than the corresponding final pre-programming verification level are biased for non-SSPC programming. The threshold voltage is at the corresponding final pre-programming verification level and the final programming verification level PV. L1 To PV L7The memory cells between them are biased for SSPC programming. The threshold voltage is greater than the corresponding final programming verification level PV. L1 To PV L7 The memory cells are prohibited from being programmed further.

[0077] When each memory cell within memory cell groups 441-447 is biased for non-SSPC programming, SSPC programming, or is disabled for programming, a third subsequent programming pulse is applied to memory cell groups 441-447 to provide memory cell groups 411-417. Following the third subsequent programming pulse, a programming verification operation is performed to sense a threshold voltage for each memory cell within memory cell groups 411-417. Memory cells with threshold voltages lower than the corresponding final pre-programming verification level (e.g., in this example, no memory cells) are biased for non-SSPC programming. The threshold voltage at the corresponding final pre-programming verification level and the final programming verification level PV... L1 To PV L7 Memory cells between (e.g., in this example, no memory cells) are biased for SSPC programming. The threshold voltage is greater than the corresponding final programming verification level PV. L1 To PV L7 The memory cells (e.g., all memory cells in this example) are disabled from further programming. It should be noted that memory cells may be disabled from programming during a programming pulse due to a lower programming verification level, and may not be disabled from programming during subsequent programming pulses due to a higher programming verification level.

[0078] exist Figure 7 In the embodiment, the first programming verification level PV L1,1 To PV L7,1 For programming verification operations following the specific programming pulse, the second programming verification level PV L1,2 To PV L7,2 Used for programming verification operations following the first subsequent programming pulse, and the final programming verification level PV L1 To PV L7 Used for programming verification operations following the second subsequent programming pulse. However, in other embodiments, the first programming verification level PV L1,2 To PV L7,2 and final programming verification level PV L1 To PV L7 Additional programmed verification levels (and pre-programmed verification levels) may be included between them.

[0079] For memory cells representing data states L0 and L1, the read window between memory cell group 410 and memory cell group 411 is indicated as 450. For memory cells representing data states L1 and L2, the read window between memory cell group 411 and memory cell group 412 is indicated as 451. Similarly, for memory cells representing data states L2, L3, L4, L5, L6, and L7, the read windows between memory cell groups 412, 413, 414, 415, and 416 and memory cell groups 413, 414, 415, 416, and 417 are indicated as 452, 453, 454, 455, and 456, respectively. In this example, RWB can be the cumulative value (e.g., in voltage form) of the seven read windows 450-456 between the eight Vt distributions. Due to the use of dynamically programmed verification levels, Figure 7 Compared to the RWB of the embodiment Figure 3 The RWB of the embodiments is improved. Furthermore, the improved RWB can be obtained without increasing programming time, since the same number of programming pulses can be used in either embodiment.

[0080] Figures 8A-8D This is a flowchart of a method 500 for operating a memory according to an embodiment. Method 500 may at least partially correspond to Figure 6 and 7 .For example, Figures 8A-8D This can represent a method of performing a programming operation, such as programming one or more memory cells to a target level. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0081] Method 500 can be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array (e.g., TLC memory cells, QLC memory cells, or PLC memory cells) to program selected memory cells (e.g., 208) in the memory cell array to a target level. Figure 8A As shown, at 502, the controller can sense a first threshold voltage of the selected memory cell. At 504, the controller can respond to the sensed first threshold voltage at a first pre-programmed verification level (e.g., Figure 6 382) and the first programming verification level (e.g., Figure 6 Between 380 and 380, the selected memory cell bias is used for selective slow programming convergence (SSPC) programming, where the first pre-programming verification level is less than the final pre-programming verification level (e.g., Figure 6(372) and the first programming verification level is less than the final programming verification level (e.g., Figure 6 (370). At 506, the controller may bias the selected memory cell for non-SSPC programming in response to a sensed first threshold voltage being less than a first pre-programming verification level. At 508, the controller may disable programming of the selected memory cell in response to a sensed first threshold voltage being greater than a first programming verification level. At 510, the controller may apply a specific programming pulse to the selected memory cell.

[0082] In one instance, the difference between the first programming verification level and the final programming verification level may be less than or equal to 1V. The difference between the first pre-programming verification level and the final pre-programming verification level may be equal to the difference between the first programming verification level and the final programming verification level. The difference between the first pre-programming verification level and the first programming verification level may be equal to the difference between the final pre-programming verification level and the final programming verification level.

[0083] like Figure 8B As shown, at 512, the controller may further sense (e.g., after the specific pulse) a second threshold voltage for the selected memory cell. At 514, the controller may further, in response to the sensed second threshold voltage between a second pre-programming verification level and a second programming verification level, bias the selected memory cell for SSPC programming, wherein the second pre-programming verification level is less than a final pre-programming verification level and greater than a first pre-programming verification level, and the second programming verification level is less than a final programming verification level and greater than a first programming verification level. At 516, the controller may further, in response to the sensed second threshold voltage being less than the second pre-programming verification level, bias the selected memory cell for non-SSPC programming. At 518, the controller may further, in response to the sensed second threshold voltage being greater than the second programming verification level, disable programming of the selected memory cell. At 520, the controller may further apply a first subsequent programming pulse to the selected memory cell. The first subsequent programming pulse may immediately follow the specific programming pulse.

[0084] In one instance, the difference between the first programming verification level and the second programming verification level may be equal to the difference between the second programming verification level and the final programming verification level. Similarly, the difference between the first pre-programming verification level and the second pre-programming verification level may be equal to the difference between the second pre-programming verification level and the final pre-programming verification level.

[0085] like Figure 8CAs shown, at 522, the controller may further sense (e.g., after the first subsequent pulse) a third threshold voltage of the selected memory cell. At 524, the controller may further, in response to the sensed third threshold voltage being between a third pre-programming verification level and a third programming verification level, bias the selected memory cell for SSPC programming, wherein the third pre-programming verification level is less than a final pre-programming verification level and greater than a second pre-programming verification level, and the third programming verification level is less than a final programming verification level and greater than a second programming verification level. At 526, the controller may further, in response to the sensed third threshold voltage being less than the third pre-programming verification level, bias the selected memory cell for non-SSPC programming. At 528, the controller may further, in response to the sensed third threshold voltage being greater than the third programming verification level, disable programming of the selected memory cell. At 530, the controller may further apply a second subsequent programming pulse to the selected memory cell. The second subsequent programming pulse may immediately follow the first subsequent programming pulse.

[0086] In one instance, the differences between the first and second programming verification levels, the differences between the second and third programming verification levels, and the differences between the third and final programming verification levels can be equal. The differences between the first and second pre-programming verification levels, the differences between the second and third pre-programming verification levels, and the differences between the third and final pre-programming verification levels can also be equal.

[0087] like Figure 8D As shown, at 532, the controller may alternatively sense (e.g., after the first subsequent pulse) a third threshold voltage of the selected memory cell. At 534, the controller may further bias the selected memory cell for SSPC programming in response to the sensed third threshold voltage being between the final pre-programming verification level and the final programming verification level. At 536, the controller may further bias the selected memory cell for non-SSPC programming in response to the sensed third threshold voltage being less than the final pre-programming verification level. At 538, the controller may further disable further programming of the selected memory cell in response to the sensed third threshold voltage being greater than the final programming verification level.

[0088] Figure 9A and 9B This is a flowchart of a method 600 for operating a memory according to another embodiment. Method 600 may at least partially correspond to Figure 6 and 7 .For example, Figure 9A and 9B This can represent a method of performing a programming operation, such as programming one or more memory cells to a target level. The method may be, for example, stored in... Figure 1The instruction register 128 contains computer-readable instructions. Such computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0089] Method 600 can be implemented within a memory device (e.g., 100) comprising a memory cell array (e.g., 104) and a controller (e.g., 116) configured to access the memory cell array (e.g., TLC memory cells, QLC memory cells, or PLC memory cells) to program selected memory cells (e.g., 208) in the memory cell array to a target level. Figure 9A As shown, at 602, the controller can apply a specific programming pulse to the selected memory cell. At 604, the controller can sense whether the selected memory cell has been programmed to a level lower than the final programming verification level (e.g., Figure 7 PV L4 The first programming verification level (e.g., Figure 7 PV L4,1 At 606, the controller may apply a first subsequent programming pulse to the selected memory cell. At 608, the controller may sense whether the selected memory cell has been programmed to a second programming verification level that is less than the final programming verification level and greater than the first programming verification level (e.g., Figure 7 PV L4,2 At 610, the controller may apply a second subsequent programming pulse to the selected memory cell. At 612, the controller may sense whether the selected memory cell has been programmed to the final programming verification level. The first subsequent programming pulse may immediately follow the specific programming pulse, and the second subsequent programming pulse may immediately follow the first subsequent programming pulse. In one example, the difference between the first programming verification level and the second programming verification level may be equal to the difference between the second programming verification level and the final programming verification level.

[0090] The memory device implementing method 600 may further include, as previously referenced Figure 2A-2C The described data lines (e.g., 204) are selectively connected to selected memory cells. In this embodiment, as... Figure 9BAs shown, at 614, the controller may further respond to sensing that the selected memory cell has been programmed to a level between the first pre-programming verification level and the first programming verification level by biasing the data line to a Selective Slow Programming Convergence (SSPC) level during the first subsequent programming pulse, wherein the first pre-programming verification level is less than the first programming verification level. At 616, the controller may further respond to sensing that the selected memory cell has been programmed to a level less than the first pre-programming verification level by biasing the data line to a non-SSPC level during the first subsequent programming pulse. At 618, the controller may further respond to sensing that the selected memory cell has been programmed to a level greater than the first programming verification level by biasing the data line to an inhibit level during the first subsequent programming pulse. The SSPC level may be greater than the non-SSPC level and less than the inhibit level.

[0091] The memory device implementing method 600 may further include, as previously referenced Figure 2A-2C The described access line (e.g., 202) is connected to the control gate (e.g., 236) of the selected memory cell. In this embodiment, the controller may further apply the specific programming pulse, the first subsequent programming pulse, and the second subsequent programming pulse to the access line.

[0092] Figure 10A-10D This is a flowchart of a method 700 for operating a memory according to another embodiment. Method 700 may at least partially correspond to Figure 6 and 7 .For example, Figure 10A-10D This can represent a method of performing a programming operation, such as programming one or more memory cells to a target level. The method may be, for example, stored in... Figure 1 The instruction register 128 contains computer-readable instructions. Such computer-readable instructions can be executed by a controller (e.g., control logic 116) to cause the memory device 100 to perform the method.

[0093] Method 700 can be implemented within a memory device (e.g., 100) comprising: a memory cell array (e.g., 104) including a plurality of serially connected strings of memory cells (e.g., 206); a plurality of access lines (e.g., 202), wherein each access line is connectable to a control gate (e.g., 236) of a corresponding memory cell (e.g., 208) in each serially connected string of memory cells (e.g., a NAND string); and a controller (e.g., 116) configured to program each corresponding memory cell connected to a selected access line to a corresponding target level. Figure 10AAs shown, at 702, the controller can sense a first threshold voltage for each corresponding memory cell connected to the selected access line. At 704, the controller can disable programming of the corresponding memory cell in response to the sensed first threshold voltage for each corresponding memory cell connected to the selected access line being greater than a first programming verification level for the corresponding memory cell, wherein the first programming verification level for the corresponding memory cell is less than a final programming verification level for the corresponding memory cell. At 706, the controller can enable programming of the corresponding memory cell in response to the sensed first threshold voltage for each corresponding memory cell connected to the selected access line being less than the first programming verification level for the corresponding memory cell. At 708, the controller can apply a specific programming pulse to the selected access line. At 710, the controller can sense a second threshold voltage for each corresponding memory cell connected to the selected access line. At 712, the controller can disable programming of the corresponding memory cell in response to the sensed second threshold voltage for each corresponding memory cell connected to the selected access line being greater than the final programming verification level for the corresponding memory cell. At 714, the controller may enable programming of a corresponding memory cell in response to a sensed second threshold voltage connected to each corresponding memory cell on the selected access line being less than the final programming verification level of the corresponding memory cell. At 716, the controller may apply a first subsequent programming pulse to the selected access line.

[0094] like Figure 10B As shown, at 718, the controller may further enable Selective Slow Programming Convergence (SSPC) programming of the corresponding memory cell in response to a sensed first threshold voltage of each corresponding memory cell connected to the selected access line being greater than a first pre-programming verification level and less than a first programming verification level of the corresponding memory cell. At 720, the controller may further enable SSPC programming of the corresponding memory cell in response to a sensed second threshold voltage of each corresponding memory cell connected to the selected access line being greater than a final pre-programming verification level and less than a final programming verification level of the corresponding memory cell, wherein the final pre-programming verification level of the corresponding memory cell is greater than the first pre-programming verification level of the corresponding memory cell.

[0095] In one instance, the difference between the first preprogrammed verification level and the first programming verification level of each corresponding memory cell may be equal to the difference between the final preprogrammed verification level and the final programming verification level of each corresponding memory cell.

[0096] The memory device implementing method 700 may further include a plurality of data lines (e.g., 204), wherein each serially connected string of memory cells is selectively electrically connected to a corresponding data line, as previously referenced. Figure 2A-2C Description. In this embodiment, as Figure 10C As shown, at 722, the controller may further bias the corresponding data line connected to the corresponding memory cell of the selected access line during the specific programming pulse and the first subsequent programming pulse, based on whether each corresponding memory cell connected to the selected access line is enabled for programming, enabled for SSPC programming, or disabled for programming.

[0097] like Figure 10D As shown, at 724, the controller may further sense (e.g., after the first subsequent programming pulse) a third threshold voltage for each corresponding memory cell connected to the selected access line. At 726, the controller may further disable programming of the corresponding memory cell in response to the sensed third threshold voltage for each corresponding memory cell connected to the selected access line being greater than a second programming verification level for the corresponding memory cell, wherein the second programming verification level for the corresponding memory cell is less than the final programming verification level for the corresponding memory cell and greater than the first programming verification level for the corresponding memory cell. At 728, the controller may further enable programming of the corresponding memory cell in response to the sensed third threshold voltage for each corresponding memory cell connected to the selected access line being less than the second programming verification level for the corresponding memory cell. At 730, the controller may further apply a second subsequent programming pulse to the selected access line. Method 700 may continue until each corresponding memory cell connected to the selected access line is verified to have a sensed threshold voltage greater than the final programming verification level for the corresponding memory cell.

[0098] In one instance, the difference between the first programming verification level and the second programming verification level of each corresponding memory cell may be equal to the difference between the second programming verification level and the final programming verification level of each corresponding memory cell. The difference between the first programming verification level and the final programming verification level of each corresponding memory cell may be less than or equal to 1V.

[0099] in conclusion

[0100] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that any arrangement is expected to achieve the same purpose in lieu of the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory device comprising: Memory cell array; as well as A controller configured to access the memory cell array to program selected memory cells in the memory cell array to a target level. The controller is further configured to: Sensing a first threshold voltage of the selected memory cell; In response to the sensed first threshold voltage between a first pre-programming verification level and a first programming verification level, the selected memory cell is biased for selective slow programming convergence SSPC programming, wherein the first pre-programming verification level is less than the final pre-programming verification level and the first programming verification level is less than the final programming verification level. In response to the sensed first threshold voltage being less than the first pre-programmed verification level, the selected memory cell is biased for non-SSPC programming; In response to the sensed first threshold voltage being greater than the first programming verification level, programming of the selected memory cell is prohibited; as well as A predetermined programming pulse is applied to the selected memory cell.

2. The memory device of claim 1, wherein the controller is further configured to: Sensing the second threshold voltage of the selected memory cell; In response to a sensed second threshold voltage between a second pre-programming verification level and a second programming verification level, the selected memory cell is biased for SSPC programming, wherein the second pre-programming verification level is less than the final pre-programming verification level and greater than the first pre-programming verification level, and the second programming verification level is less than the final programming verification level and greater than the first programming verification level. In response to the sensed second threshold voltage being less than the second pre-programmed verification level, the selected memory cell is biased for non-SSPC programming; In response to the sensed second threshold voltage being greater than the second programming verification level, programming of the selected memory cell is prohibited; as well as The first subsequent programming pulse is applied to the selected memory cell.

3. The memory device of claim 2, wherein the first subsequent programming pulse is immediately following the predetermined programming pulse.

4. The memory device of claim 2, wherein the difference between the first programming verification level and the second programming verification level is equal to the difference between the second programming verification level and the final programming verification level, and The difference between the first preprogrammed verification level and the second preprogrammed verification level is equal to the difference between the second preprogrammed verification level and the final preprogrammed verification level.

5. The memory device of claim 2, wherein the controller is further configured to: Sensing the third threshold voltage of the selected memory cell; In response to the sensed third threshold voltage being between a third pre-programming verification level and a third programming verification level, the selected memory cell is biased for SSPC programming, wherein the third pre-programming verification level is less than the final pre-programming verification level and greater than the second pre-programming verification level, and the third programming verification level is less than the final programming verification level and greater than the second programming verification level. In response to the sensed third threshold voltage being less than the third pre-programmed verification level, the selected memory cell is biased for non-SSPC programming; In response to the sensed third threshold voltage being greater than the third programming verification level, programming of the selected memory cell is prohibited; as well as A second subsequent programming pulse is applied to the selected memory cell.

6. The memory device of claim 5, wherein the second subsequent programming pulse immediately follows the first subsequent programming pulse.

7. The memory device of claim 5, wherein the difference between the first programming verification level and the second programming verification level, the difference between the second programming verification level and the third programming verification level, and the difference between the third programming verification level and the final programming verification level are equal, and The differences between the first preprogrammed verification level and the second preprogrammed verification level, the differences between the second preprogrammed verification level and the third preprogrammed verification level, and the differences between the third preprogrammed verification level and the final preprogrammed verification level are equal.

8. The memory device of claim 2, wherein the controller is further configured to: Sensing the third threshold voltage of the selected memory cell; In response to the sensed third threshold voltage between the final pre-programming verification level and the final programming verification level, the selected memory cell is biased for SSPC programming; In response to the sensed third threshold voltage being less than the final pre-programmed verification level, the selected memory cell is biased for non-SSPC programming; as well as In response to the sensed third threshold voltage being greater than the final programming verification level, further programming of the selected memory cell is prohibited.

9. The memory device of claim 1, wherein the difference between the first programming verification level and the final programming verification level is less than or equal to 1V, and The difference between the first preprogrammed verification level and the final preprogrammed verification level is equal to the difference between the first programming verification level and the final programming verification level.

10. The memory device of claim 1, wherein the difference between the first preprogramming verification level and the first programming verification level is equal to the difference between the final preprogramming verification level and the final programming verification level.

11. The memory device according to claim 1, wherein the memory unit comprises a TLC memory unit, a QLC memory unit, or a PLC memory unit.

12. A memory device comprising: Memory cell array; as well as A controller configured to access the memory cell array to program selected memory cells within the memory cell array. The controller is further configured to: A predetermined programming pulse is applied to the selected memory cell; Sensing whether the selected memory cell has been programmed to a first programming verification level lower than the final programming verification level; A first subsequent programming pulse is applied to the selected memory cell; Sensing whether the selected memory cell has been programmed to a second programming verification level that is lower than the final programming verification level and higher than the first programming verification level; A second subsequent programming pulse is applied to the selected memory cell; as well as Sensing whether the selected memory cell has been programmed to the final programming verification level.

13. The memory device of claim 12, wherein the first subsequent programming pulse is immediately following the predetermined programming pulse, and the second subsequent programming pulse is immediately following the first subsequent programming pulse.

14. The memory device of claim 12, further comprising: Data lines, which are selectively connected to the selected memory cells, The controller is further configured to: In response to sensing that the selected memory cell has been programmed to a level between a first pre-programming verification level and a first programming verification level, the data line is biased to a Selective Slow Programming Convergence (SSPC) level during the first subsequent programming pulse, wherein the first pre-programming verification level is less than the first programming verification level. In response to sensing that the selected memory cell has been programmed to a level lower than the first pre-programming verification level, the data line is biased to a non-SSPC level during the first subsequent programming pulse; as well as In response to sensing that the selected memory cell has been programmed to a level greater than the first programming verification level, the data line is biased to an inhibit level during the first subsequent programming pulse.

15. The memory device of claim 14, wherein the SSPC level is greater than the non-SSPC level and less than the disable level.

16. The memory device of claim 12, further comprising: Access lines, which are connected to the control gate of the selected memory cell, The controller is further configured to apply the predetermined programming pulse, the first subsequent programming pulse, and the second subsequent programming pulse to the access line.

17. The memory device of claim 12, wherein the difference between the first programming verification level and the second programming verification level is equal to the difference between the second programming verification level and the final programming verification level.

18. A memory device comprising: A memory cell array comprising multiple strings of memory cells connected in series; Multiple access lines, each of the multiple access lines being connected to the control gate of a corresponding memory cell in each of the multiple series-connected memory cell strings; as well as The controller is configured to program each corresponding memory cell connected to a selected access line of the plurality of access lines to a corresponding target level. The controller is further configured to: Sensing a first threshold voltage for each corresponding memory cell connected to the selected access line; In response to a sensed first threshold voltage of each corresponding memory cell connected to the selected access line being greater than a first programming verification level of the corresponding memory cell, programming of the corresponding memory cell is prohibited, wherein the first programming verification level of the corresponding memory cell is less than the final programming verification level of the corresponding memory cell. In response to a sensed first threshold voltage of each corresponding memory cell connected to the selected access line being less than the first programming verification level of the corresponding memory cell, programming of the corresponding memory cell is enabled; Apply a predetermined programming pulse to the selected access line; Sensing a second threshold voltage for each corresponding memory cell connected to the selected access line; In response to a sensed second threshold voltage for each corresponding memory cell connected to the selected access line being greater than the final programming verification level of the corresponding memory cell, programming of the corresponding memory cell is prohibited; In response to a sensed second threshold voltage of each corresponding memory cell connected to the selected access line being less than the final programming verification level of the corresponding memory cell, programming of the corresponding memory cell is enabled; as well as Apply a first subsequent programming pulse to the selected access line.

19. The memory device of claim 18, wherein the controller is further configured to: In response to a sensed first threshold voltage of each corresponding memory cell connected to the selected access line being greater than a first pre-programming verification level of the corresponding memory cell and less than a first programming verification level of the corresponding memory cell, selective slow programming convergence (SSPC) programming of the corresponding memory cell is enabled; and In response to a sensed second threshold voltage of each corresponding memory cell connected to the selected access line being greater than the final pre-programming verification level of the corresponding memory cell and less than the final programming verification level of the corresponding memory cell, SSPC programming of the corresponding memory cell is enabled, wherein the final pre-programming verification level of the corresponding memory cell is greater than the first pre-programming verification level of the corresponding memory cell.

20. The memory device of claim 19, further comprising: Multiple data lines, wherein each of the multiple series-connected memory cell strings is selectively electrically connected to a corresponding data line among the multiple data lines. The controller is further configured to bias the corresponding data line of the corresponding memory cell connected to the selected access line during the predetermined programming pulse and the first subsequent programming pulse, based on whether each corresponding memory cell connected to the selected access line is enabled for programming, enabled for SSPC programming, or disabled for programming.

21. The memory device of claim 19, wherein the difference between the first preprogramming verification level of each corresponding memory cell and the first programming verification level of each corresponding memory cell is equal to the difference between the final preprogramming verification level of each corresponding memory cell and the final programming verification level of each corresponding memory cell.

22. The memory device of claim 18, wherein the controller is further configured to: Sensing a third threshold voltage for each corresponding memory cell connected to the selected access line; In response to a sensed third threshold voltage of each corresponding memory cell connected to the selected access line being greater than a second programming verification level of the corresponding memory cell, programming of the corresponding memory cell is prohibited, wherein the second programming verification level of the corresponding memory cell is less than the final programming verification level of the corresponding memory cell and greater than the first programming verification level of the corresponding memory cell. In response to a sensed third threshold voltage of each corresponding memory cell connected to the selected access line being less than the second programming verification level of the corresponding memory cell, programming of the corresponding memory cell is enabled; as well as A second subsequent programming pulse is applied to the selected access line.

23. The memory device of claim 22, wherein the difference between the first programming verification level of each corresponding memory cell and the second programming verification level of each corresponding memory cell is equal to the difference between the second programming verification level of each corresponding memory cell and the final programming verification level of each corresponding memory cell.

24. The memory device of claim 18, wherein the difference between the first programming verification level of each respective memory cell and the final programming verification level of each respective memory cell is less than or equal to 1V.

25. The memory device of claim 18, wherein the plurality of serially connected memory cell strings comprise a plurality of NAND strings.

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