Quadrupole control device, quadrupole equipment and mass spectrometer

Abstract

The present application relates to a quadrupole control device, a quadrupole device and a mass spectrometer. The quadrupole control device includes a host computer, a data processor and an amplifier circuit. The host computer configures the scanning parameters and sends them to the data processor. The data processor divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit, which generates different voltages according to the scanning signal to drive the quadrupole to work. The host computer configures the parameters, and the data processor parses the parameters, internally constructs a scanning sequence generated for different scanning coefficients, generates a scanning signal, so that the amplifier circuit can generate different voltages according to the scanning signal, drives the quadrupole to work, and can quickly switch the voltage that excites the quadrupole, so that the quadrupole can scan a variety of ions. It is flexible to use, has a fast voltage switching speed, high work efficiency, and is convenient and reliable to use.

Description

Technical Field

[0001] The present application relates to the technical field of mass spectrometers, and in particular to a quadrupole control device, a quadrupole device and a mass spectrometer. Background Art

[0002] A mass spectrometer, also known as a mass spectrometer, is an instrument that separates and detects the composition of matter based on the mass difference of atoms, molecules or molecular fragments of matter, based on the principle that charged particles can be deflected in an electromagnetic field. The quadrupole is the main component of a mass spectrometer. Ions are focused near the central axis of the quadrupole under the action of an electric field. The voltage is applied in such a way that a set of opposite poles are applied with voltages of the same polarity and adjacent poles are applied with voltages of opposite polarity. Under the combined action of the radio frequency electric field and the direct current electric field, a complex oscillating motion is initiated, and ions of different mass-to-charge ratios are selected using the electric field that changes over time.

[0003] In the traditional method of controlling the voltage of the quadrupole, the quadrupole scanning is usually controlled by building an analog circuit. However, this method has poor flexibility, complex circuit debugging, low work efficiency, and unreliable use. Summary of the invention

[0004] Based on this, it is necessary to provide a quadrupole control device, a quadrupole device and a mass spectrometer to address the problem that the traditional method of controlling the voltage of the quadrupole is unreliable.

[0005] A quadrupole control device, comprising:

[0006] Configure scanning parameters and send the scanning parameters to the host computer of the data processor; the scanning parameters include scanning mode;

[0007] Divide the scanning parameters into blocks according to the scanning mode, configure them into scanning coefficients, and form a scanning sequence according to the scanning coefficients, generate a scanning signal according to the scanning sequence, and transmit the scanning signal to the data processor of the amplification circuit;

[0008] The amplifier circuit generates different voltages according to the scanning signal to drive the quadrupole to work;

[0009] The host computer is connected to the data processor, the data processor is connected to the amplifier circuit, and the amplifier circuit is connected to the quadrupole.

[0010] A quadrupole device comprises a quadrupole and the quadrupole control device as described above.

[0011] A mass spectrometer comprises the quadrupole device as described above.

[0012] The above-mentioned quadrupole control device, quadrupole equipment and mass spectrometer, the quadrupole control device includes a host computer, a data processor and an amplifier circuit, the host computer is connected to the data processor, the data processor is connected to the amplifier circuit, and the amplifier circuit is connected to the quadrupole. The host computer configures the scanning parameters and sends the scanning parameters to the data processor. The scanning parameters include the scanning mode. The data processor divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit, and the amplifier generates different voltages according to the scanning signal to drive the quadrupole to work. The host computer configures the parameters and sends them to the data processor, the data processor parses the parameters, internally constructs a scanning sequence generated for different scanning coefficients, and generates a scanning signal according to the scanning sequence, so that the amplifier circuit can generate different voltages according to the scanning signal, drive the quadrupole to work, and can quickly switch the voltage of the excitation quadrupole, so that the quadrupole can scan a variety of ions, flexible to use, fast voltage switching speed, high work efficiency, convenient and reliable use.

[0013] In one embodiment, the host computer further includes a host computer scanning execution module that sends execution commands to the data processor, and the execution commands include start scanning and stop scanning.

[0014] In one embodiment, the data processor further comprises a processor scanning execution module which builds a scanning sequence according to the scanning coefficients based on the execution command.

[0015] In one of the embodiments, the host computer further includes a host computer communication protocol module that encapsulates the information to be sent to the data processor into a data packet according to a preset transmission protocol, and the host computer communication protocol module is connected to the data processor.

[0016] In one of the embodiments, the data processor further includes a processor communication protocol module for parsing received data packets and extracting data, and the processor communication protocol module is connected to the host computer communication protocol module.

[0017] In one embodiment, the data processor further includes a state control module, and the state control module is connected to the amplification circuit.

[0018] In one embodiment, the amplification circuit includes a digital-to-analog converter and a radio frequency circuit module, the data processor is connected to the digital-to-analog converter, the digital-to-analog converter is connected to the radio frequency circuit module, and the radio frequency circuit module is connected to a quadrupole.

[0019] In one embodiment, the data processor is a FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a structural block diagram of a quadrupole control device in one embodiment;

[0021] Figure 2 is a schematic structural diagram of a quadrupole control device in one embodiment;

[0022] Figure 3 FIG. 4 is a flowchart of a quadrupole control device in one embodiment. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is described more comprehensively below through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0024] In one embodiment, see Figure 1 A quadrupole control device is provided, including a host computer 110, a data processor 120 and an amplifier circuit 130. The host computer 110 is connected to the data processor 120, the data processor 120 is connected to the amplifier circuit 130, the amplifier circuit 130 is connected to the quadrupole 200, the host computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120. The scanning parameters include a scanning mode. The data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit 130. The amplifier generates different voltages according to the scanning signal to drive the quadrupole 200 to work. The parameters are configured by the host computer 110 and sent to the data processor 120. The data processor 120 analyzes the parameters, internally constructs a scanning sequence generated for different scanning coefficients, and generates a scanning signal according to the scanning sequence, so that the amplifier circuit 130 can generate different voltages according to the scanning signal to drive the quadrupole 200 to work. The voltage that excites the quadrupole 200 can be quickly switched, so that the quadrupole 200 can scan a variety of ions. The use is flexible, the voltage switching speed is fast, the work efficiency is high, and the use is convenient and reliable.

[0025] The quadrupole 200 is one of the main components of the mass spectrometer. The basic principle of the quadrupole 200 scanning technology is that ions are focused near the central axis of the quadrupole 200 under the action of the electric field. The voltage is applied in a manner that a set of opposite poles apply voltages of the same polarity and adjacent poles apply voltages of opposite polarity. Under the combined action of the radio frequency electric field and the direct current electric field, complex oscillation motions are initiated, and ions of different mass-to-charge ratios are selected using the electric field that changes with time. The ions coming out of the quadrupole 200 hit the high-energy dynode to generate electrons, and the electrons generate electrical signals through the electron multiplier. The electrical signals coming out of the multiplier are sent to the computer for storage. After these signals are processed by the computer, chromatograms, mass spectra and other information can be obtained.

[0026] Specifically, the type and structure of the host computer 110 are not unique. In the present embodiment, the host computer 110 is a visualization platform that can realize human-computer interaction, for example, it may include a main processing chip and a touch screen, the main processing chip is used for data processing, the touch screen is used for displaying data, and receiving operation instructions input by the user. The host computer 110 is the main control device of the quadrupole control device, and the data processor 120 is used as a slave execution. The system is generally a non-visual platform, and all functions are implemented by the code development of the research and development personnel, with high confidentiality and security. The mode of connection and communication between the host computer 110 and the data processor 120 is not unique. In the present embodiment, the host computer 110 and the data processor 120 have only a unique interface to transmit data to each other. The host computer 110 is responsible for sending commands, and the data processor 120 is responsible for executing commands to complete the work of the entire scanning system. The host computer 110 and the data processor 120 use a private protocol to communicate, which increases the security of the system. The host computer 110 is flexible in control and operation, and can realize efficient scheduling of the entire system.

[0027] For further information, see Figure 2 , the part related to data processing in the host computer 110 can include a host computer parameter configuration module 111, the host computer parameter configuration module 111 configures scanning parameters, and sends the scanning parameters to the data processor 120, the scanning parameters are parameters that need to be executed, and are configured to the host computer 110 in a simple form, and the type of scanning parameters is not unique. In the present embodiment, the scanning parameters include scanning modes, and the scanning modes mainly include full scanning and point scanning, but are not limited to these two scanning modes, and can also be expanded to more scanning modes. The scanning parameters can also include initial voltage, scanning proton number, difference voltage, scanning trend, initial stabilization time, voltage interval stabilization time, single proton scanning time and single / cycle scanning selection, wherein the user can only set the scanning parameters used for this scanning, and the others all keep the default values. The scanning parameters are selected and configured according to user needs, and all parameters can be sent as 2Byte, and 2Byte is the agreement between the host computer 110 and the slave computer. After configuration, the slave computer will use 2Byte as the configuration value of the parameter. It is understandable that in other embodiments, the structure of the host computer 110, the structure of the scanning parameters, or the configuration of the scanning parameters may be other and may be adjusted according to actual needs as long as those skilled in the art consider it achievable.

[0028] The data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit 130. Figure 2The data processor 120 includes a parameter analysis module 122, a processor parameter configuration module 123 and an amplifier circuit control module 125. The parameter analysis module 122 divides the scanning parameters into blocks according to the scanning mode. The processor parameter configuration module 123 places the content of the parameter block into the corresponding scanning coefficient according to the current configuration requirements, configures it into the scanning coefficient, and waits for the scanning trigger. The parameter analysis module 122 also forms a scanning sequence according to the scanning coefficient, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit 130. Specifically, the parameter analysis module 122 is used to analyze and divide the scanning parameters issued by the host computer 110, distinguish different parameter blocks of the scanning parameters according to the scanning mode, calculate the value sent to the amplifier circuit 130 according to the voltage parameter, and query the corresponding gain and bias voltage, calculate the real time corresponding to each time parameter according to the issued time parameter and the clock count itself, and form the overall scanning sequence according to the initial voltage, the number of scanned protons, the difference voltage, and the scanning trend. The amplifier circuit control module 125 generates a scanning signal according to the scanning sequence and transmits the scanning signal to the amplifier circuit 130.

[0029] The amplifier circuit control module 125 has different structures and actions according to the different structures of the amplifier circuit 130. In this embodiment, when the amplifier circuit 130 includes a DAC (Digital-to-Analog Converter), the amplifier circuit control module 125 is a DAC control module. During the scanning process, the DAC control module sends the digital signal to the DAC according to the scanning requirements according to the timing requirements of different DACs, so as to control the voltage output in sequence by the data processor 120.

[0030] The amplifier circuit 130 generates different voltages according to the scanning signal to drive the quadrupole 200 to work. The structure of the amplifier circuit 130 is not unique. Figure 2 The amplification circuit 130 includes a DAC module and a radio frequency circuit module 132. The DAC module converts the digital signal from the data processor 120 into an analog voltage signal. The radio frequency circuit module 132 amplifies the analog signal sent by the DAC module to the voltage amplitude required by the quadrupole 200 to drive the quadrupole 200 to work.

[0031] The type of data processor 120 is not unique. In this embodiment, data processor 120 is FPGA (Field Programmable Gate Array). The quadrupole control device adopts the architecture of host computer 110 + FPGA to realize the control scanning of quadrupole 200. FPGA can realize the high-speed response of the system. For the scanning voltage switching control, it can be realized as nanosecond level control. In this embodiment, FPGA uses a 100MHz system clock, which can achieve 10ns level of precise control. The host computer 110 is flexible in control and operation, and can realize efficient scheduling of the entire system. Using FPGA to realize scanning in the system belongs to hardware programming implementation, which has strong portability and strong security and confidentiality. In addition, the quadrupole 200 scanning system designed by FPGA can adapt to the implementation environment under a variety of host computer 110 platforms according to the different interfaces of different host computers 110, saving development costs.

[0032] In one embodiment, see Figure 2 The host computer 110 also includes a host computer scanning execution module 112 that sends execution commands to the data processor 120, and the execution commands include starting scanning and stopping scanning.

[0033] The host computer scanning execution module 112 can send an execution command to the data processor 120, and the execution command includes starting scanning and stopping scanning, so as to control the data processor 120 to start working or stop working. Further, when the host computer 110 also includes a host computer parameter configuration module 111, the host computer scanning execution module 112 is connected to the host computer parameter configuration module 111, and the host computer parameter configuration module 111 configures the scanning parameters to be executed to the host computer 110 in a simple form. The host computer scanning execution module 112 is an execution command sent from the host computer 110 to the data processor 120, including starting scanning and stopping scanning.

[0034] In one embodiment, see Figure 2 The data processor 120 also includes a processor scan execution module 124 that builds a scan sequence according to the scan coefficients based on the execution command.

[0035] When the host computer 110 includes a host computer scanning execution module 112 that sends an execution command to the data processor 120, the data processor 120 is also provided with a corresponding processor scanning execution module 124, which is used to form a scanning timing according to the scanning coefficient after receiving the execution command, so as to realize the on-demand work of the processor scanning execution module 124 and reduce the workload. Specifically, the processor scanning execution module 124 executes the scanning operation according to the start scanning command issued by the host computer 110, specifically, sends different voltage values ​​to the amplifier circuit 130 according to the time agreement and sequence, and forcibly stops the scanning process according to the stop scanning command issued by the host computer 110, and the scanning parameters remain unchanged. Furthermore, when the data processor 120 also includes a parameter analysis module 122, a processor parameter configuration module 123 and an amplifier circuit control module 125, the parameter analysis module 122 is connected to the processor parameter configuration module 123, the processor parameter configuration module 123 is connected to the processor scanning execution module 124, and the processor scanning execution module 124 is connected to the amplifier circuit control module 125. The functions of each module have been described in detail before and will not be repeated here.

[0036] In one embodiment, see Figure 2 The host computer 110 also includes a host computer communication protocol module 113 that encapsulates the information to be sent to the data processor 120 into a data packet according to a preset transmission protocol, and the host computer communication protocol module 113 is connected to the data processor 120. After the host computer communication protocol module 113 encapsulates the information to be sent to the data processor 120 into a data packet according to the preset transmission protocol, the data packet is sent to the data processor 120, which can improve the security and stability of communication.

[0037] Specifically, the host computer communication protocol module 113 encapsulates the information sent to the data processor 120 according to the preset transmission protocol, and the preset transmission protocol can be a private protocol with higher security. The communication mode of the host computer 110 and the data processor 120 is not unique. In the present embodiment, the host computer 110 and the data processor 120 use the rg45 network transmission, and the protocol uses the udp transmission protocol to realize the Gigabit Ethernet transmission. It can be understood that in other embodiments, the host computer 110 and the data processor 120 can also communicate in other ways, as long as those skilled in the art think that it can be realized. Expandably, when the host computer 110 also includes a host computer parameter configuration module 111 and a host computer scanning execution module 112, the host computer parameter configuration module 111 is connected to the host computer scanning execution module 112, and the host computer scanning execution module 112 is connected to the host computer communication protocol module 113, and the role of each module has been described in detail before, and will not be repeated here.

[0038] In one embodiment, see Figure 2The data processor 120 also includes a processor communication protocol module 121 that parses the received data packet and extracts data. The processor communication protocol module 121 is connected to the host computer communication protocol module 113.

[0039] When the host computer 110 also includes a host computer communication protocol module 113 that encapsulates the information to be sent to the data processor 120 into a data packet according to a preset transmission protocol, correspondingly, the data processor 120 also includes a processor communication protocol module 121 connected to the host computer communication protocol module 113, and the processor communication protocol module 121 parses the received data packet and extracts data. The protocol content adopted by the host computer communication protocol module 113 and the processor communication protocol module 121 can be the same to better transmit data. The processor communication protocol module 121 can implement the parsing of the data packet sent by the host computer 110 at the data processor 120 end, and extract the actual data. In addition to the UDP transmission protocol, the protocol can also add a private protocol to define the header and tail and the verification of the packet to further improve the security of the transmitted data.

[0040] Expandably, when the data processor 120 also includes a parameter analysis module 122, a processor parameter configuration module 123, an amplifying circuit control module 125 and a processor scanning execution module 124, the processor communication protocol module 121 is connected to the parameter analysis module 122, the parameter analysis module 122 is connected to the processor parameter configuration module 123, the processor parameter configuration module 123 is connected to the processor scanning execution module 124, and the processor scanning execution module 124 is connected to the amplifying circuit control module 125. The functions of each module have been described in detail before and will not be repeated here.

[0041] In one embodiment, see Figure 2 The data processor 120 further includes a state control module 126, which is connected to the amplifier circuit 130. The state control module 126 can monitor the working state of the amplifier circuit 130. Furthermore, the state control module 126 can also be connected to the host computer 110, and report abnormal information to the host computer 110 when an abnormality is found. The host computer 110 can display the abnormal situation, or report the abnormal situation to other devices for display, so as to remind the staff to deal with it in time.

[0042] Specifically, the state control module 126 is connected to the amplifier circuit 130, and can be specifically connected to the DAC in the amplifier circuit 130. The state control module 126 is also connected to the host computer 110. The state control module 126 can monitor the overall system status before, during and after the scanning process, including monitoring parameter configuration status, transmission timing status, DAC transmission status, etc. Among them, parameter configuration monitoring refers to the lower computer transmitting the received parameter configuration back to the host computer 110, and the host computer 110 compares and determines whether the parameters sent are received normally by the data processor 120. After the host computer 110 sends the parameters, the data processor 120 does not respond or the responded parameters are inconsistent with the sent parameters. The host computer 110 determines that the parameters sent this time are wrong and will re-send them. Transmission timing status monitoring is to monitor the check bit in the transmission protocol. If the check bit is abnormal, it is determined whether there is transmission or not, and the status is notified to the host computer 110. DAC transmission status monitoring refers to monitoring the abnormal indication pin of the DAC chip, and notifying the host computer 110 when an abnormality is detected. It is understandable that in other embodiments, the state control module 126 may also be connected to other devices to implement other functions, as long as those skilled in the art consider it achievable.

[0043] In one embodiment, see Figure 2 The amplification circuit 130 includes a digital-to-analog converter 131 and a radio frequency circuit module 132 , the data processor 120 is connected to the digital-to-analog converter 131 , the digital-to-analog converter 131 is connected to the radio frequency circuit module 132 , and the radio frequency circuit module 132 is connected to the quadrupole 200 .

[0044] Specifically, the digital-to-analog converter 131 is a DAC module, which converts the digital signal from the data processor 120 into an analog voltage signal, and the radio frequency circuit module 132 amplifies the analog signal sent by the DAC module to the voltage amplitude required by the quadrupole 200 to drive the quadrupole 200 to work. Further, the voltage value is multiplied to the voltage required to drive the quadrupole 200, and an oscillation circuit is used to drive the quadrupole 200 to work. The oscillation circuit is a sine wave generated by DDS (Direct Digital Frequency Synthesis, direct digital frequency synthesizer algorithm) and a DC amplifier to generate an alternating current with a peak value of 1000V, and its oscillation frequency is 1MHz. It can be understood that in other embodiments, the amplifier circuit 130 can also be other structures, as long as those skilled in the art believe that it can be implemented.

[0045] In one embodiment, the data processor 120 is an FPGA. The quadrupole control device adopts the architecture of the host computer 110+FPGA to realize the control scanning of the quadrupole 200. The FPGA can realize the high-speed response of the system, and can realize the control of the scanning voltage switching control at the nanosecond level. In this embodiment, the FPGA uses a 100MHz system clock, which can achieve precise control at the 10ns level. The host computer 110 is flexible in control and operation, and can realize efficient scheduling of the entire system. The use of FPGA to realize scanning in the system belongs to hardware programming implementation, which has strong portability and strong security and confidentiality. In addition, the quadrupole 200 scanning system designed by FPGA can adapt to the implementation environment under a variety of host computer 110 platforms according to the different interfaces of different host computers 110, saving development costs.

[0046] In order to better understand the above embodiment, a detailed explanation is given below in conjunction with a specific embodiment. In one embodiment, see Figure 2 The quadrupole control device includes a host computer 110, a data processor 120 and an amplifier circuit 130, and the data processor 120 is an FPGA. The host computer 110 is used as the main control to realize human-computer interaction and a visualization platform. The FPGA is used as a slave execution. The system is an invisible platform. All functions are implemented by the code development of the R&D personnel, and have high confidentiality and security. The host computer 110 and the FPGA have only one interface to transmit data to each other. The host computer 110 is responsible for sending commands, and the FPGA is responsible for executing commands to complete the work of the entire scanning system. The host computer 110 and the FPGA use a private protocol to communicate, which increases the security of the system. The amplifier circuit 130 and the quadrupole 200 are function realization units. The host computer 110 is connected to the FPGA chip through a hardware interface, the FPGA chip is connected to the amplifier circuit 130 through a hardware interface, and the amplifier circuit 130 is connected to the quadrupole 200.

[0047] Host computer 110 includes host computer parameter configuration module 111, host computer scanning execution module 112, and host computer communication protocol module 113. The host computer parameter configuration module 111 configures the parameters to be executed to the host computer 110 in a simple form. Basic parameters include scanning mode, initial voltage, number of scanned protons, difference voltage, scanning trend, initial stable time, voltage interval stable time, single proton scanning time, single / cycle scanning selection. All parameters are selected and configured according to user needs. All parameters are sent as 2Byte. The user only needs to set the parameters used in this scan, and the others are kept as default values. 2Byte is the agreement between the host computer 110 and the slave computer. After configuration, the slave computer will use 2Byte as the configuration value of the parameter. The host computer scanning execution module 112 sends the execution command to FPGA at the host computer 110 end, including starting scanning and stopping scanning. The host computer communication protocol module 113 encapsulates the information sent to the FPGA according to the transmission protocol. In this embodiment, the host computer 110 and the FPGA use the rg45 network transmission, and the protocol uses the udp transmission protocol to achieve Gigabit Ethernet transmission. The information transmitted between the host computer 110 and the FPGA can be encapsulated and parsed according to the protocol to ensure the security and stability of communication.

[0048] FPGA includes a processor communication protocol module 121, a parameter parsing module 122, a processor parameter configuration module 123, a processor scan execution module 124, an amplifier circuit control module 125 and a state control module 126. The content of the processor communication protocol module 121 is the same as that of the host computer communication protocol module 113, which implements the parsing of the data packets sent by the host computer on the FPGA side and extracts the actual data. In addition to the UDP transmission protocol, the protocol adds a private protocol, defines the packet header and packet tail and packet verification.

[0049] The parameter parsing module 122 parses and divides the scanning parameters sent by the host computer 110, distinguishes different parameter blocks according to the scanning mode, calculates the value sent to the DAC and the corresponding gain and bias voltage according to the voltage parameter, calculates the real time corresponding to each time parameter according to the time parameter sent and the clock count itself, and builds the overall scanning sequence according to the initial voltage, the number of scanned protons, the difference voltage, and the scanning trend. The parameter parsing module 122 divides the received parameters into different parameter blocks according to the mode at the FPGA end. In the embodiment, there are mainly full scan and point scan, but it is not limited to these two scan modes and can also be expanded to more scan modes.

[0050] The processor scan execution module 124 executes the scan operation according to the start command issued by the host computer 110, specifically sending different voltage values ​​to the DAC module according to the time agreement and sequence, and monitoring the process in real time to see if it is correct. According to the stop command issued by the host computer 110, the scanning process is forcibly stopped, and the scanning parameters remain unchanged. After receiving the scan command issued by the host computer 110, the scan timing is constructed according to the current scan coefficient. The FPGA uses a 100MHz system clock, which can achieve 10ns level of precise control.

[0051] The amplifier circuit control module 125 can be specifically a DAC control module. During the scanning process, according to the timing requirements of different DACs, the digital signal is sent to the DAC according to the scanning requirements, so as to complete the FPGA to control the voltage output in sequence. Specifically, according to the different voltage values ​​given by the scanning timing and the queried voltage gain value and voltage bias value, the DAC is transmitted according to the required timing of the DAC.

[0052] The state control module 126 monitors the overall system status before, during and after the scanning process, including monitoring the parameter configuration status, transmission timing status and DAC transmission status. Among them, the parameter configuration monitoring is: the lower computer will transmit the received parameter configuration back to the upper computer 110, and the upper computer 110 will compare and determine whether the sent parameters are received normally by the FPGA. After the upper computer 110 sends the parameters, the FPGA does not respond or the responded parameters are inconsistent with the sent parameters. The upper computer 110 determines that the sent parameters are wrong and will resend them. The transmission timing status monitoring is to monitor the check bit in the transmission protocol. If the check bit is abnormal, it is determined whether there is transmission or not, and the status is notified to the upper computer 110. DAC transmission status monitoring refers to monitoring the abnormal indication pin of the DAC chip, and notifying the upper computer 110 when an abnormality is detected.

[0053] The amplifier circuit 130 includes a digital-to-analog converter 131 and a radio frequency circuit module 132. The DAC module converts the digital signal of the FPGA into an analog voltage signal. The radio frequency circuit module 132 amplifies the analog signal sent by the DAC to the voltage amplitude required by the quadrupole 200, and generates an oscillation circuit to drive the quadrupole 200 to work. The oscillation circuit is composed of the sine wave generated by the DDA and the DC amplifier to generate an alternating current with a peak value of 1000V and an oscillation frequency of 1MHz. The quadrupole 200 is a device for screening ions in a mass spectrometer. Oscillating voltages of different amplitudes can allow different protons to pass through.

[0054] See also Figure 3 , the workflow of the quadrupole control device includes the following steps:

[0055] Step S201, the host computer is in a waiting state;

[0056] Step S202, configure the required parameters on the host computer, encapsulate the protocol, and send it down;

[0057] Step S203, FPGA decodes the data packet according to the communication protocol, parses the valid data sent according to the private protocol, and extracts the parameters therein;

[0058] Step S204, dividing the parameters into blocks and configuring them into scanning coefficients;

[0059] Step S205, FPGA waits for the execution command from the host computer;

[0060] Step S206, the FPGA executes the scanning logic according to the scanning coefficients, and controls the transmission of different values ​​to the DAC at different time points;

[0061] Step S207, if the scanning is completed, return to step S201, otherwise continue scanning;

[0062] Step S208, if a stop command is received, return to step S201, otherwise continue scanning;

[0063] Step S209, the DAC converts the digital signal into an analog signal and transmits it to the RF circuit;

[0064] In step S210 , the radio frequency circuit multiplies the voltage value to the voltage required to drive the quadrupole, and uses an oscillation circuit to drive the quadrupole to work.

[0065] The above-mentioned quadrupole control device includes a host computer 110, a data processor 120 and an amplifier circuit 130, wherein the host computer 110 is connected to the data processor 120, the data processor 120 is connected to the amplifier circuit 130, and the amplifier circuit 130 is connected to the quadrupole 200. The host computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120. The scanning parameters include a scanning mode. The data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit 130, which generates different voltages according to the scanning signal to drive the quadrupole 200 to work. The parameters are configured by the host computer 110 and sent to the data processor 120. The data processor 120 analyzes the parameters, internally constructs a scanning sequence generated for different scanning coefficients, and generates a scanning signal according to the scanning sequence, so that the amplifier circuit 130 can generate different voltages according to the scanning signal to drive the quadrupole 200 to work. The voltage that excites the quadrupole 200 can be quickly switched, so that the quadrupole 200 can scan a variety of ions. The use is flexible, the voltage switching speed is fast, the work efficiency is high, and the use is convenient and reliable.

[0066] In one embodiment, a quadrupole device is provided, including a quadrupole 200 and a quadrupole control device as described above.

[0067] The above-mentioned quadrupole device includes a host computer 110, a data processor 120 and an amplifier circuit 130, wherein the host computer 110 is connected to the data processor 120, the data processor 120 is connected to the amplifier circuit 130, and the amplifier circuit 130 is connected to the quadrupole 200. The host computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120, wherein the scanning parameters include a scanning mode, the data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit 130, which generates different voltages according to the scanning signal to drive the quadrupole 200 to work. The parameters are configured by the host computer 110 and sent to the data processor 120. The data processor 120 analyzes the parameters, internally constructs a scanning sequence generated for different scanning coefficients, and generates a scanning signal according to the scanning sequence, so that the amplifier circuit 130 can generate different voltages according to the scanning signal to drive the quadrupole 200 to work. The voltage that excites the quadrupole 200 can be quickly switched, so that the quadrupole 200 can scan a variety of ions. The use is flexible, the voltage switching speed is fast, the work efficiency is high, and the use is convenient and reliable.

[0068] In one embodiment, a mass spectrometer is provided, comprising the quadrupole device as described above.

[0069] The mass spectrometer includes a host computer 110, a data processor 120 and an amplifier circuit 130. The host computer 110 is connected to the data processor 120, the data processor 120 is connected to the amplifier circuit 130, and the amplifier circuit 130 is connected to the quadrupole 200. The host computer 110 configures scanning parameters and sends the scanning parameters to the data processor 120. The scanning parameters include a scanning mode. The data processor 120 divides the scanning parameters into blocks according to the scanning mode, configures them into scanning coefficients, and forms a scanning sequence according to the scanning coefficients, generates a scanning signal according to the scanning sequence, and transmits the scanning signal to the amplifier circuit 130. The amplifier generates different voltages according to the scanning signal to drive the quadrupole 200 to work. The parameters are configured by the host computer 110 and sent to the data processor 120. The data processor 120 analyzes the parameters, internally constructs a scanning sequence generated for different scanning coefficients, and generates a scanning signal according to the scanning sequence, so that the amplifier circuit 130 can generate different voltages according to the scanning signal to drive the quadrupole 200 to work. The voltage that excites the quadrupole 200 can be quickly switched, so that the quadrupole 200 can scan a variety of ions. The use is flexible, the voltage switching speed is fast, the work efficiency is high, and the use is convenient and reliable.

[0070] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A quadrupole control device, characterized in that: include: Configure scanning parameters and send the scanning parameters to the host computer of the data processor; the scanning parameters include scanning mode; the scanning mode includes full scanning and point scanning; the scanning parameters also include initial voltage, number of scanning protons, difference voltage, scanning trend, initial stabilization time, voltage interval stabilization time, single proton scanning time and single / cycle scanning selection; The scanning parameters are divided into blocks according to the scanning mode, configured into scanning coefficients, and a scanning sequence is formed according to the scanning coefficients, a scanning signal is generated according to the scanning sequence, and the scanning signal is transmitted to the data processor of the amplification circuit; the host computer and the data processor transmit data through a unique interface and communicate using a private protocol; the scanning sequence is formed according to the initial voltage, the number of scanned protons, the difference voltage and the scanning trend; The amplifier circuit generates different voltages according to the scanning signal to drive the quadrupole to work; The data processor is connected to the amplifier circuit, and the amplifier circuit is connected to the quadrupole.

2. The quadrupole control device according to claim 1, characterized in that: The host computer further comprises a host computer scanning execution module which sends an execution command to the data processor, wherein the execution command comprises starting scanning and stopping scanning.

3. The quadrupole control device according to claim 2, characterized in that: The data processor also includes a processor scanning execution module that builds a scanning sequence according to the scanning coefficients based on the execution command.

4. The quadrupole control device according to claim 1, characterized in that: The host computer also includes a host computer communication protocol module that encapsulates the information to be sent to the data processor into a data packet according to a preset transmission protocol, and the host computer communication protocol module is connected to the data processor.

5. The quadrupole control device according to claim 4, characterized in that: The data processor also includes a processor communication protocol module that parses the received data packets and extracts data, and the processor communication protocol module is connected to the host computer communication protocol module.

6. The quadrupole control device according to claim 1, characterized in that: The data processor further comprises a state control module, and the state control module is connected to the amplifying circuit.

7. The quadrupole control device according to claim 1, characterized in that: The amplification circuit includes a digital-to-analog converter and a radio frequency circuit module, the data processor is connected to the digital-to-analog converter, the digital-to-analog converter is connected to the radio frequency circuit module, and the radio frequency circuit module is connected to the quadrupole.

8. The quadrupole control device according to any one of claims 1 to 7, characterized in that: The data processor is FPGA.

9. A quadrupole device, characterized in that The invention comprises a quadrupole and a quadrupole control device as claimed in any one of claims 1 to 8.

10. A mass spectrometer, characterized in that: Comprising the quadrupole device as claimed in claim 9.

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