Enhanced semiconductor device packaging and related systems and methods

Abstract

This application relates to enhanced semiconductor device packages and related systems and methods. Systems and methods are provided for semiconductor devices having enhanced packages. The devices generally include a substrate and one or more integrated circuit dies electrically coupled to the substrate by wirebonds. The devices include a sealant encapsulating the one or more dies and the wirebonds. The package can include a reinforcement layer on one or more surfaces of the sealant, a reinforcement wire extending through the sealant, or portions of an embedded reinforcement fiber throughout the sealant. The reinforcement layer can be a textile woven from synthetic or natural fibers such as aramid, carbon, or glass. The package can be formed by disposing a reinforcement textile layer in a mold, placing the dies and substrate in the mold with a liquid sealant, and hardening the liquid sealant to adhere the reinforcement textile layer, the sealant, the dies, and the substrate together.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, and in several embodiments, more specifically to systems and methods of enhancing the packaging of semiconductor devices. BACKGROUND

[0002] Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, often include one or more semiconductor dies mounted to a substrate and encased in a protective covering. The semiconductor dies include functional features such as memory cells, processor circuitry, interconnect circuitry, and the like. Semiconductor die manufacturers are under increasing pressure to reduce the volume occupied by semiconductor dies while increasing the capacity and / or speed of the resulting sealed assemblies. To meet these and other demands, semiconductor die manufacturers often vertically stack multiple semiconductor dies on top of one another to increase the capacity or performance of the microelectronic device.

[0003] The overall height of a microelectronic device package can be limited based on packaging specifications, intended applications, and / or physical constraints of the circuit board or other element on which the semiconductor device is mounted. When die stacking is maximized within a single package, the protective covering thickness is correspondingly reduced, and the package is structurally weakened. Such semiconductor devices can suffer damage during handling, packaging, shipping, assembly, use, and the like, which can lead to premature failure of integrated circuits, wire bonds, and the like. By minimizing the thickness of the substrate, the package strength is further reduced. SUMMARY

[0004] In one aspect, the present application relates to a semiconductor device comprising: a substrate having a front side with substrate contacts; a die attached to the front side of the substrate; wire bonds electrically coupling bond pads of the die to the substrate contacts; a sealant encapsulating the die and the wire bonds; and a layer of reinforcing textile extending over at least a portion of the sealant.

[0005] In another aspect, the present application relates to a semiconductor device comprising: a substrate having a front side with substrate contacts; a die attached to the front side of the substrate; conductive members electrically coupling bond pads of the die to the substrate contacts; and a sealant containing a plurality of portions of entrained fibers, the sealant encapsulating the die and wire bonds.

[0006] In another aspect, the application relates to a method of forming a semiconductor device package, comprising: attaching a die to a front side of a substrate; electrically coupling bond pads of the die to substrate contacts on the front side of the substrate with conductive members; disposing a layer of reinforcing textile in a mold; placing the die and substrate in the mold with a liquid encapsulant; and hardening the liquid encapsulant to adhere the layer of reinforcing textile, the encapsulant, the die, and the substrate together. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a cross-sectional view illustrating a semiconductor device configured in accordance with embodiments of the present technology before application of an encapsulant.

[0008] Figures 2A to 2D is a cross-sectional view illustrating a semiconductor package of the semiconductor device having Figure 1 various package reinforcement configurations after application of an encapsulant.

[0009] Figure 3 is a flow diagram illustrating a method of forming a semiconductor device package in accordance with embodiments of the present technology.

[0010] Figure 4 is a schematic diagram of a system incorporating a semiconductor device in accordance with embodiments of the present technology. DETAILED DESCRIPTION

[0011] The technology disclosed herein relates to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Moreover, the term “semiconductor device” can refer to a finished device or to a component or other structure at various processing stages before becoming a finished device. In some embodiments, a single semiconductor device can be “packaged” and include a molding material or encapsulant that encases components and conductive connections in the device. The encapsulant can be applied using a mold cavity or other suitable method.

[0012] Depending on the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate, or to an individual die-level substrate, or another die for a die-stacking application. Appropriate steps of the methods described herein can be performed at the wafer level or at the die level. Moreover, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques, unless the context indicates otherwise. For example, materials can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, electroplating, and / or other suitable techniques. Similarly, materials can be removed using, for example, plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.

[0013] The technology includes semiconductor devices with enhanced package configurations. Integrated circuit packages can include enhancements such that the semiconductor devices can withstand greater external forces without damaging the device. Conventional semiconductor device packages use encapsulants without structural enhancements. As die stack heights are maximized, the thickness of the encapsulant and / or substrate is correspondingly minimized - weakening the structure of the package. Similarly, single-die integrated circuits are structurally weakened. Likewise, exposure to handling, retail and shipping packaging, transportation, assembly, use, thermal cycling and / or other forces can cause stresses, strains and fatigue that overcome the strength and / or flexibility of the package and result in premature failure of the semiconductor device.

[0014] The technology generally relates to a bonded semiconductor device having semiconductor dies or die stacks attached to a package substrate and covered with an encapsulant. The package substrate has a mounting surface to which the dies are attached. In one embodiment, each semiconductor die has an active side with bond pads facing away from the mounting surface of the substrate. The bond pads are typically located at the edges of the dies, and the dies are arranged on the mounting surface such that the bond pads on the edges of the dies can be wire bonded to bond pads on the mounting surface of the substrate. In a stacked configuration, the dies can be laterally offset or stepped to allow front side access to the bond pads of each die in the stack. After the dies are electrically coupled to the substrate, the encapsulant encases at least a portion of the exposed surfaces of the die stack, wire bonds and substrate. The encapsulation process can be performed in a mold cavity. Prior to encapsulation, a textile reinforcement layer can be disposed in the mold cavity to provide at least partially embedded reinforcement on one or more outer surfaces of the encapsulant after the encapsulant hardens (e.g., as a liquid molding compound at least partially, and in some cases completely, penetrates the weave of the textile reinforcement layer). In some embodiments, the technology allows for reduced package size of semiconductor devices with higher mechanical strength and flexibility characteristics.

[0015] Figure 1A cross-sectional view of a semiconductor device 100 ("device 100") is shown prior to the application of encapsulant to the device 100. The device 100 can be a memory array, such as a stack of NAND memory dies, which can further include one or more logic dies. The device 100 includes a silicon substrate 110 having a front side 112 (e.g., a die mounting surface) and a back side 114. The thickness of the substrate 110 can depend on packaging constraints, the number of dies in the device 100, etc. The device 100 has a first die 120 attached to the front side 112 of the substrate 110. The first die 120 has a bond pad 122 along an edge of the first die 120 that faces away from the front side 112 of the substrate 110. The first die 120 can be positioned laterally away from a contact 116 on the front side 112 of the substrate 110 to allow access to a wire bond 124 that is configured to electrically couple the bond pad 122 of the first die 120 and the contact 116 of the substrate 110. Although only a single bond pad 122 and a single contact 116 are shown in the cross-sectional view of Figure 1 The device 100 typically has a large number of bond pads 122 and contacts 116.

[0016] The device 100 can have a second die 130 bonded to the first die 120 in a laterally offset configuration, and having a bond pad 132 along an edge of the second die 130 that faces away from the front side 112 of the substrate 110. The bond pad 132 is configured to accept a wire bond 134 to electrically couple the second die 130 to a contact 116 on the substrate 110. The device 100 can similarly include any number of additional dies, such as a third die 140 and a fourth die 150. The third die 140 can be bonded to the first die 120 and the second die 130 in a laterally offset configuration, and having a bond pad 142 along an edge of the third die 140 that faces away from the front side 112 of the substrate 110. The bond pad 142 is configured to accept a wire bond 144 and electrically couple the third die 140 to a contact 118 on the substrate 110. The fourth die 150 can be bonded to the first die 120, the second die 130, and the third die 140 in a laterally offset configuration, and having a bond pad 152 along an edge of the fourth die 150 that faces away from the front side 112 of the substrate 110. The bond pad 152 is configured to accept a wire bond 154 and electrically couple the fourth die 150 to a contact 118 on the substrate 110.

[0017] Although four dies are shown in a stacked and laterally offset stepped configuration, any number of dies packaged with an edge notched substrate are within the scope of the present technology. Furthermore, although an exemplary configuration of the device 100 is depicted in Figures 1 to 2D Any suitable configuration of a device is also within the scope of the present technology, such as multiple integrated circuits on the same substrate, a stack of devices and / or dies, etc.

[0018] Figures 2A to 2D is a cross-sectional view of the device 100 after the application of a sealant and having various package enhancement configurations. Figure 2A A semiconductor package 102 ("package 102") is shown having the device 100 and a package molding material 160 ("sealant 160") that covers the components of the device 100 after the dies 120, 130, 140, and 150 are bonded to and electrically coupled to the substrate 110. The sealant 160 is applied by flowing a liquid molding material through the mounting components of the device 100 within the confines of a molding slot (not shown). The molding slot is configured to constrain the outer shape of the package and maintain that form until the liquid molding material solidifies. The package 102 has an enhancement layer 162 applied to the upper surface 161a of the sealant 160. The enhancement layer 162 can be inserted into the molding slot with the molding material to bond the enhancement layer 162 with the sealant 160. In other embodiments, the enhancement layer 162 is coupled to a release film and applied to the molding slot prior to forming the package 102. The enhancement layer 162 can be any suitable textile material, such as cloth, sheet, fabric, etc. In some embodiments, the enhancement layer 162 is a woven cloth woven with synthetic or natural fibers having the material properties of strength, elasticity, heat resistance, etc. as required. Examples of fibers suitable for use in the present technology include aramid (e.g., Kevlar®, Nomex®, etc.), carbon, and / or glass. Embodiments having a cloth enhancement layer can have a single fiber material or any suitable mixture of fiber materials. Further, any number of cloth layers can form the enhancement layer 162. and .

[0019] Figure 2B A semiconductor package 104 ("package 104") is shown having the device 100 and the sealant 160 that covers the components of the device 100 after the dies 120, 130, 140, and 150 are bonded and electrically coupled to the substrate 110. The package 104 has an enhancement layer 164 applied to the upper surface 161a and one or more side surfaces 161b of the sealant 160. The package 104 is generally similar to the package 102 except that the enhancement layer 164 covers at least some of the side surfaces 161b of the sealant 160. In this regard, the material of the enhancement layer 164 (e.g., cloth, sheet, board, etc.) can be a single piece with folded regions or cutouts at the corners of the sealant 160 to allow the material to accommodate the shape of the sealant 160. The enhancement layer 164 can be inserted into the molding slot with the molding material to bond the enhancement layer 164 with the sealant 160. In other embodiments, the enhancement layer 164 is coupled to a release film and applied to the molding slot prior to forming the package 104.

[0020] Figure 2CA semiconductor package 106 ("package 106") is shown having the device 100 and an encapsulant 160 that covers the components of the device 100 after the dies 120, 130, 140, and 150 are bonded and electrically coupled to the substrate 110. The package 106 has at least one reinforcement wire 166 that extends through the encapsulant 160 and is attached to the front side 112 of the substrate 110 at a first pad 167 and a second pad 168. The first and second pads 167 and 168 can be grounded such that the reinforcement wire 166 does not electrically alter the device 100. In some embodiments, the reinforcement wire 166 is bonded to the substrate 110 after the dies 120, 130, 140, and 150 are bonded to the substrate 110. The reinforcement wire 166 can have any suitable material, such as copper, steel, aluminum, etc. In these embodiments, the diameter of the reinforcement wire 166 can be thicker than the wire bonds of the dies of the device 100 and can be between about 20 pm and 100 pm. Although a single reinforcement wire 166 is shown in cross-section, any number of reinforcement wires can be included in the encapsulant 160 of the package 106 and the wires can be positioned apart along the length of the wire, one or more wires can cross, or any combination thereof. Figure 2C Although a single reinforcement wire 166 is shown in cross-section, any number of reinforcement wires can be included in the encapsulant 160 of the package 106 and the wires can be positioned apart along the length of the wire, one or more wires can cross, or any combination thereof.

[0021] Figure 2D A semiconductor package 108 ("package 108") is shown having the device 100 and a fiber-reinforced encapsulant 170 that covers the components of the device 100 after the dies 120, 130, 140, and 150 are bonded and electrically coupled to the substrate 110. The fiber-reinforced encapsulant 170 includes a molding material mixed with a plurality of entrained synthetic or natural fiber portions (e.g., aramid, carbon, glass, etc.) that create a slurry. The encapsulant 170 is formed using a molding slot and when the material sets, the fiber portions entrained within the slurry are randomly oriented, increasing the mechanical strength of the encapsulant 170.

[0022] Although described herein with reference to dies wire-bonded to a substrate and die stacks, in other embodiments, dies attached to a substrate in several other ways can also benefit from a textile reinforcement layer similar to those shown in the figures and described above. For example, dies attached to a substrate using a direct chip attach (DCA) method, in which the active surface of the die is directly interconnected to a bond pad on the upper surface of the substrate through, for example, solder, can also be similarly configured. Alternatively or additionally, with necessary modifications, semiconductor device packages in which a die stack is interconnected with a through-substrate via (TSV) can also be similarly configured.

[0023] The bond pads 122, 132, 142, and 152, and the contacts 116 and 118 can be copper pads, and can be bonded using copper-copper bonding or other suitable techniques. Although not shown in the figures, the packages 102, 104, 106, and 108 can be electrically coupled to other components through BGA or other suitable interconnects.

[0024] Figure 3 is a flowchart illustrating a method 200 of forming a semiconductor device package according to embodiments of the present technology. At block 202, the method includes attaching the die 120 to the front side 112 of the substrate 110. At block 204, the method includes electrically coupling the bond pads 122 of the die 120 to the substrate contacts 116 on the front side 112 of the substrate 110 with the conductive members 124. At block 206, the method includes disposing a reinforcing layer 162 of a textile woven with synthetic or natural fibers in a mold. At block 208, the method includes placing the die 120 and the substrate 110 in the mold with the liquid encapsulant 160. At block 210, the method includes spacing the die 120 apart from the reinforcing textile layer 162 in the mold such that the liquid encapsulant 160 flows between the die 120 and the reinforcing textile layer 162. At block 212, the method includes hardening the liquid encapsulant 160 to adhere the reinforcing textile layer 162, the encapsulant 160, the die 120, and the substrate 110 together.

[0025] Figure 4 is a block diagram illustrating a system incorporating a semiconductor device according to embodiments of the present technology. Any of the semiconductor devices having the features described above with reference to Figures 1 to 3 Any of the semiconductor devices having the features described above with reference to Figure 4 may be incorporated into any of a myriad of larger and / or more complex systems, representative examples of which are schematically shown in the system 400 shown in Figures 1 to 3 The semiconductor components, devices, and device packages described above with reference to Figure 4 Figure 4The illustrated system 400 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 400 include, but are not limited to, computers and / or other data processors such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 400 include lamps, video cameras, vehicles, and the like. In these and other examples, system 400 can be placed in a single unit, or distributed across multiple interconnected units, e.g., over a communications network. Accordingly, the components of system 400 can include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0026] As used in the foregoing description, the terms "vertical," "lateral," "upper," and "lower" can refer to the relative orientation or position of features in a semiconductor device, given the orientation shown in the figures. For example, "upper" or "uppermost" can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations, e.g., inverted or tilted orientations, where top / bottom, over / under, higher / lower, upward / downward, left / right, and distal / proximal can be interchanged depending on the orientation. Moreover, for ease of reference, throughout the disclosure, the same reference numbers are used to identify like or similar components or features, but the use of the same reference number does not imply that the features should be understood as the same. In fact, in many of the examples described herein, the same numbered features have multiple embodiments that are structurally and / or functionally different from one another. Moreover, unless specifically noted herein, the same shading can be used to indicate materials that can be compositionally similar in cross-section, but the use of the same shading does not imply that the materials should be understood as the same.

[0027] The foregoing disclosure can also refer to quantities and numbers. Unless specifically stated, these quantities and numbers should not be construed as limiting but rather as examples of possible quantities or numbers relevant to the new technology. Additionally, in this regard, the disclosure can use the term "plurality" to refer to a quantity or number. In this regard, the term "plurality" means any number greater than one, such as two, three, four, five, etc. For the purpose of the disclosure, the phrase "at least one of A, B, and C," for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when more than three elements are listed.

[0028] From the foregoing, it will be appreciated that specific embodiments of the new technology have been described herein for purposes of illustration, but that various modifications can be made without deviating from the disclosure. Thus, the present disclosure is not limited except as by the appended claims. Moreover, certain aspects of the new technology described in the context of a particular embodiment can also be combined or removed in other embodiments. Furthermore, although advantages of the new technology associated with certain embodiments can be described with reference to particular embodiments and expressed as being the best mode contemplated, such an expression is used only in the sense that the present disclosure and associated technology are the best mode contemplated at the time of this disclosure and associated technology, and is not a limitation as to the scope of the disclosure and associated technology. Accordingly, it is not intended that the present disclosure and associated technology be limited, except as by the appended claims.

Claims

1. A semiconductor device comprising: a substrate having a front side, the front side having a substrate contact; a die attached to the front side of the substrate; a wire bond electrically coupling a bond pad of the die to the substrate contact; an encapsulant encapsulating the die and the wire bond; and a reinforcing textile layer extending over at least a portion of the encapsulant, wherein the reinforcing textile layer extends across an upper surface of the encapsulant.

2. The semiconductor device of claim 1, wherein the reinforcing textile layer extends across the upper surface of the encapsulant and a side surface of the encapsulant.

3. The semiconductor device of claim 1, wherein the reinforcing textile layer is at least partially embedded in the portion of the encapsulant.

4. The semiconductor device of claim 1, wherein the reinforcing textile layer comprises a cloth woven from synthetic or natural fibers.

5. The semiconductor device of claim 4, wherein the fibers comprise aramid, carbon, glass, or combinations thereof.

6. The semiconductor device of claim 1, wherein: the die is a first die, the bond pad is a first bond pad, and the wire bond is a first wire bond; the semiconductor device further comprises a second die attached to the first die, the second die having a second bond pad electrically coupled to the substrate contact by a second wire bond; and the second die and the second wire bond are encapsulated within the encapsulant.

7. The semiconductor device of claim 1, further comprising a reinforcing wire coupled to the front side of the substrate at a first end and at a second end, the reinforcing wire extending over at least a portion of the die through the encapsulant.

8. The semiconductor device of claim 7, wherein the substrate further comprises: a first ground pad on the front side for coupling the first end of the reinforcing wire to the substrate; and a second ground pad on the front side for coupling the second end of the reinforcing wire to the substrate.

9. The semiconductor device of claim 7, wherein the reinforcing wire comprises a plurality of wires extending through the encapsulant.

10. The semiconductor device of claim 9, wherein at least one of the plurality of wires spans another of the plurality of wires along a length of the encapsulant.

11. The semiconductor device of claim 7, wherein the reinforcing wire comprises copper, steel, aluminum, or combinations thereof.

12. A semiconductor device comprising: a substrate having a front side, the front side having a substrate contact; a die attached to the front side of the substrate; a conductive member electrically coupling a bond pad of the die to the substrate contact; and an encapsulant containing a plurality of entrained fiber portions, the encapsulant encapsulating the die and the conductive member, wherein a reinforcing textile layer extends across an upper surface of the encapsulant.

13. The semiconductor device of claim 12, wherein the plurality of fiber portions comprise synthetic or natural fibers.

14. The semiconductor device of claim 12, wherein the plurality of fiber portions comprise at least one of aramid, carbon, and glass.

15. The semiconductor device of claim 12, wherein: the die is a first die, the bond pad is a first bond pad, and the conductive member is a first wire bond; the semiconductor device further comprises a second die attached to the first die, the second die having a second bond pad electrically coupled to a substrate contact by a second wire bond; and the second die and the second wire bond are encapsulated within the encapsulant.

16. A method of forming a semiconductor device package, comprising: attaching a die to a front side of a substrate; electrically coupling a bond pad of the die to a substrate contact on the front side of the substrate with a conductive member; disposing a layer of reinforcing textile in a mold; placing the die and substrate in the mold with a liquid encapsulant; and hardening the liquid encapsulant to adhere the layer of reinforcing textile, the encapsulant, the die, and the substrate together such that the layer of reinforcing textile extends across an upper surface of the encapsulant.

17. The method of claim 16, further comprising spacing the die apart from the layer of reinforcing textile in the mold such that the liquid encapsulant flows between the die and the layer of reinforcing textile prior to hardening the liquid encapsulant.

18. The method of claim 16, wherein the layer of reinforcing textile comprises cloth woven from synthetic or natural fibers.

19. The method of claim 18, wherein the fibers comprise aramid, carbon, or glass.

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