Semiconductor structure and method of forming a semiconductor structure

Abstract

This invention discloses a semiconductor structure and a method for forming the semiconductor structure, aiming to solve the technical problem that dielectric thin films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures. The semiconductor structure includes: a metal structure; and a dielectric thin film disposed between the metal structures. The dielectric thin film includes: a preferred orientation layer and an amorphous non-crystalline layer disposed on the preferred orientation layer. The preferred orientation layer is a crystal-oriented film layer, and the amorphous non-crystalline layer is a crystal-unoriented film layer. Due to the presence of the lower preferred orientation layer, the dielectric constant of the dielectric thin film in this structure is reduced, thereby effectively reducing the dielectric constant of the preferred orientation layer and the amorphous non-crystalline layer, and thus reducing the overall dielectric constant of the dielectric thin film.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] With the miniaturization and increasing integration of components, single-layer metal semiconductor structures can no longer meet the current performance and speed requirements of semiconductor materials. The semiconductor structure has evolved from the original single-layer metal layer to a multi-layer metal layer, and the number of interconnecting metal wires in the semiconductor structure is also constantly increasing.

[0003] As the number of metal layers and metal wires increases, the parasitic effects of resistance (R) and capacitance (C) in semiconductor structures increase. This increased parasitic effect causes significant transmission delay (RC delay), which becomes a major factor limiting signal transmission speed in circuits at 130 nm and more advanced technologies. Current semiconductor processes utilize novel low-resistance materials like copper as interconnect wires and dielectric films with low k-values ​​(low dielectric constants) as insulating materials within and between metal layers to reduce transmission delay.

[0004] However, the dielectric films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the semiconductor structure, which solves the technical problem that the dielectric thin films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0006] On the one hand, this application provides the following technical solution through one embodiment:

[0007] A semiconductor structure includes: a metal structure; and a dielectric thin film disposed between the metal structures, wherein the dielectric thin film includes: a preferred orientation layer and an amorphous non-crystalline layer disposed on the preferred orientation layer, the preferred orientation layer being a crystal-oriented film layer, and the amorphous non-crystalline layer being a crystal-unoriented film layer.

[0008] In one embodiment, the thickness of the preferred orientation layer accounts for 5%-50% of the total thickness of the dielectric film, wherein the total thickness of the dielectric film refers to the sum of the thicknesses of the preferred orientation layer and the amorphous non-crystalline layer.

[0009] On the other hand, this application provides the following technical solution through one embodiment:

[0010] A method for forming a semiconductor structure, the semiconductor structure including a metal structure and a dielectric thin film disposed between the metal structures, the method for forming the dielectric thin film including: forming a preferred orientation layer, the preferred orientation layer being a crystal-oriented film layer; and forming an amorphous non-crystalline layer on the preferred orientation layer, the amorphous non-crystalline layer being a crystal-unoriented film layer.

[0011] In one embodiment, forming the preferred orientation layer includes depositing a precursor in an atomic layer deposition apparatus to form the preferred orientation layer.

[0012] In one embodiment, when performing the step of forming the preferred orientation layer, the temperature of the process chamber of the atomic layer deposition apparatus is 400°C to 700°C, and the power of the atomic layer deposition apparatus is 1000W to 3000W.

[0013] In one embodiment, when performing the step of forming the preferred orientation layer, if the dielectric film is silicon dioxide, the atomic ratio of silicon atoms to oxygen atoms provided by the precursor is 0.6 to 1.

[0014] In one embodiment, when performing the step of forming the preferred orientation layer, the thickness of the preferred orientation layer is controlled to be 5%-50% of the total thickness of the dielectric film, wherein the total thickness of the dielectric film refers to the sum of the thicknesses of the preferred orientation layer and the amorphous non-crystalline layer.

[0015] In one embodiment, forming an amorphous amorphous layer on the preferred orientation layer includes: depositing a precursor in an atomic layer deposition apparatus to form the amorphous amorphous layer.

[0016] In one embodiment, when performing the step of forming the amorphous non-crystalline layer, the temperature of the process chamber of the atomic layer deposition apparatus is 200°C to 400°C, and the power of the atomic layer deposition apparatus is 50W to 1000W.

[0017] In one embodiment, when performing the step of forming the amorphous non-crystalline layer, if the dielectric film is silicon dioxide, the atomic ratio of silicon atoms to oxygen atoms provided by the precursor is 0.1 to 0.7.

[0018] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0019] The semiconductor structure provided in this application includes a dielectric film disposed between metal structures, comprising a preferred orientation layer at the bottom and an amorphous non-crystalline layer above the preferred orientation layer. Due to the presence of the preferred orientation layer at the bottom, the dielectric constant of the dielectric film is reduced, thereby effectively reducing the dielectric constant of the preferred orientation layer and the amorphous non-crystalline layer, and thus reducing the dielectric constant of the entire dielectric film. This solves the technical problem that dielectric films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0020] In the semiconductor structure formation method provided in this application, when forming a dielectric thin film located between metal structures, a preferred alignment layer is first formed at the bottom, and then an amorphous non-crystalline layer is formed above the preferred alignment layer. The dielectric thin film obtained by this process has a reduced inductance due to the presence of the preferred alignment layer at the bottom, thereby effectively reducing the dielectric constant of the preferred alignment layer and the amorphous non-crystalline layer, thus reducing the dielectric constant of the entire dielectric thin film. This solves the technical problem that dielectric thin films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a semiconductor structure provided in Embodiment 1 of this application;

[0023] Figure 2 for Figure 1 Enlarged view of the dielectric thin film in the image;

[0024] Figure 3 This is a flowchart of a method for forming a semiconductor structure provided in Embodiment 2 of this application. Detailed Implementation

[0025] This application provides a semiconductor structure and a method for forming the semiconductor structure, which solves the technical problem that the dielectric thin films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0026] The technical solution of this application embodiment is to solve the above-mentioned technical problems, and the general idea is as follows:

[0027] The semiconductor structure provided in this application includes a dielectric film disposed between metal structures, comprising a preferred orientation layer at the bottom and an amorphous non-crystalline layer above the preferred orientation layer. Due to the presence of the preferred orientation layer at the bottom, the dielectric constant of the dielectric film is reduced, thereby effectively reducing the dielectric constant of the preferred orientation layer and the amorphous non-crystalline layer, and thus reducing the dielectric constant of the entire dielectric film. This solves the technical problem that dielectric films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0028] In the semiconductor structure formation method provided in this application, when forming a dielectric thin film located between metal structures, a preferred alignment layer is first formed at the bottom, and then an amorphous non-crystalline layer is formed above the preferred alignment layer. The dielectric thin film obtained by this process has a reduced inductance due to the presence of the preferred alignment layer at the bottom, thereby effectively reducing the dielectric constant of the preferred alignment layer and the amorphous non-crystalline layer, thus reducing the dielectric constant of the entire dielectric thin film. This solves the technical problem that dielectric thin films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0029] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0030] Example 1

[0031] like Figure 1 As shown, this embodiment provides a semiconductor structure, including:

[0032] Metal structure 1, and dielectric thin film 2 disposed between metal structures 1, such as Figure 1 In the dashed section, during specific implementation, metal structure 1 can refer to a metal layer in a multilayer semiconductor structure, and correspondingly, dielectric film 2 can refer to an interlayer dielectric layer located between two metal layers; metal structure 1 can also refer to a via structure in a semiconductor structure used to deposit conductive material to conduct between two metal layers, and correspondingly, dielectric film 2 can refer to a dielectric layer located between two via structures; metal structure 1 can also refer to an interconnecting metal wire in a single-layer metal layer, and correspondingly, dielectric film 2 can refer to a dielectric layer located between two interconnecting metal wires.

[0033] like Figure 2 As shown, this figure is Figure 1 An enlarged view of dielectric film 2 in the figure, dielectric film 2 includes:

[0034] The preferred orientation layer 21 is disposed on the lower layer, and the amorphous non-crystalline layer 22 is disposed on the preferred orientation layer 21. The preferred orientation layer 21 is a crystal-oriented film layer, and the amorphous non-crystalline layer 22 is a crystal-unoriented film layer.

[0035] In practice, the dielectric film 2 can also be superimposed on the amorphous non-crystalline layer 22 as a dielectric layer in the prior art.

[0036] In this embodiment, the presence of the lower preferred orientation layer reduces the inductive conductivity, thereby effectively reducing the dielectric constant of the preferred orientation layer 21 and the amorphous non-crystalline layer 22, and thus reducing the dielectric constant of the entire dielectric film.

[0037] As an optional embodiment, the thickness of the preferred orientation layer 21 accounts for 5%-50% of the total thickness of the dielectric film 2, wherein the total thickness of the dielectric film 2 refers to the sum of the thicknesses of the preferred orientation layer 21 and the amorphous non-crystalline layer 22.

[0038] In this embodiment, when the thickness of the preferred orientation layer 21 accounts for 5%-50% of the total thickness of the dielectric film 2, the dielectric constant of the preferred orientation layer 21 can reach 1-2.4, and the dielectric constant of the amorphous non-crystalline layer 22 can reach 2.5-5. Compared with dielectric films in the prior art, the dielectric film 2 with this dielectric constant has a lower dielectric constant, which can reduce RC (Resistive-capacitive) delay, improve signal transmission speed, and thus improve the performance of the device.

[0039] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0040] The semiconductor structure provided in this application includes a dielectric film disposed between metal structures, comprising a preferred orientation layer at the bottom and an amorphous non-crystalline layer above the preferred orientation layer. Due to the presence of the preferred orientation layer at the bottom, the dielectric constant of the dielectric film is reduced, thereby effectively reducing the dielectric constant of the preferred orientation layer and the amorphous non-crystalline layer, and thus reducing the dielectric constant of the entire dielectric film. This solves the technical problem that dielectric films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0041] Example 2

[0042] like Figure 2 , 3 As shown, this embodiment provides a method for forming a semiconductor structure, such as... Figure 1 As shown, the semiconductor structure includes a metal structure and a dielectric thin film 2 disposed between the metal structures 1, such as... Figure 1In the dashed section, during specific implementation, metal structure 1 can refer to a metal layer in a multilayer semiconductor structure, and correspondingly, dielectric film 2 can refer to an interlayer dielectric layer located between two metal layers; metal structure 1 can also refer to a via structure in a semiconductor structure used to deposit conductive material to conduct between two metal layers, and correspondingly, dielectric film 2 can refer to a dielectric layer located between two via structures; metal structure 1 can also refer to an interconnecting metal wire in a single-layer metal layer, and correspondingly, dielectric film 2 can refer to a dielectric layer located between two interconnecting metal wires.

[0043] The method for forming dielectric thin film 2 includes:

[0044] Step S101: Form a preferred orientation layer 21, which is a crystal-oriented film.

[0045] As an optional embodiment, step S101 includes:

[0046] The precursor is deposited in an atomic layer deposition apparatus to form a preferred orientation layer 21.

[0047] In the specific implementation process, the deposition process for forming the preferred orientation layer 21 can be achieved through plasma-enhanced chemical vapor deposition (PECVD), specifically executed under the following process conditions:

[0048] When performing step S101, the temperature of the process chamber of the atomic layer deposition equipment is 400℃~700℃. As an example, the temperature can be 401℃, 500℃, 535℃, 603℃, or 695℃. The power of the atomic layer deposition equipment is 1000W~3000W. As an example, the power can be 1005W, 1988W, 2100W, 2530W, or 2983W.

[0049] When performing step S101, if the dielectric film 2 is silicon dioxide, the ratio of silicon atoms to oxygen atoms provided by the precursor is 0.6 to 1. As an example, it can be 0.6, 0.7, 0.8, 0.9, or 1. The precursor can be SiO2. If the dielectric film 2 is aluminum oxide, the ratio of aluminum atoms to oxygen atoms provided by the precursor is 0.7 to 1. As an example, it can be 0.7, 0.8, 0.85, 0.9, or 1. In actual implementation, the dielectric film 2 can also be other types of materials, such as metal oxides or semiconductor materials. The atomic ratio provided by the precursor needs to break the neutral state (for example, when the dielectric film 2 is silicon dioxide, the ratio of silicon atoms to oxygen atoms is 1:2, which is a neutral state), and present a positively charged state, that is, the ratio of atoms that easily lose outer electrons to atoms that easily gain electrons is greater than the ratio in the neutral state.

[0050] Step S102: An amorphous non-crystalline layer 22 is formed on the preferred orientation layer 21. The amorphous non-crystalline layer 22 is a film layer in which the crystals are not oriented.

[0051] As an optional embodiment, step S102 includes:

[0052] The precursor is deposited in an atomic layer deposition apparatus to form an amorphous, non-crystalline layer 22.

[0053] In the specific implementation process, the deposition process for forming the amorphous, non-crystalline layer 22 can be achieved through plasma-enhanced chemical vapor deposition (PECVD), specifically executed under the following process conditions:

[0054] When performing step S102, the temperature of the process chamber of the atomic layer deposition equipment is 200℃~400℃. As an example, the temperature can be 210℃, 280℃, 300℃, 310℃, or 396℃. The power of the atomic layer deposition equipment is 50W~1000W. As an example, the power can be 50W, 300W, 500W, 700W, or 950W.

[0055] When performing step S102, if the dielectric film 2 is silicon dioxide, the ratio of silicon atoms to oxygen atoms provided by the precursor is 0.1 to 0.7. As an example, it can be 0.1, 0.3, 0.4, 0.5, or 0.6. The precursor can be SiO2. If the dielectric film 2 is aluminum oxide, the ratio of aluminum atoms to oxygen atoms provided by the precursor is 0.1 to 0.5. As an example, it can be 0.1, 0.25, 0.3, 0.4, or 0.45. In actual implementation, the dielectric film 2 can also be other types of materials, such as metal oxides or semiconductor materials. The atomic ratio provided by the precursor needs to break the neutral state (for example, when the dielectric film 2 is silicon dioxide, the ratio of silicon atoms to oxygen atoms is 1:2, which is a neutral state), exhibiting a negatively charged state, that is, the ratio of atoms that easily lose outer electrons to atoms that easily gain electrons is less than the ratio in the neutral state.

[0056] Further, as an optional embodiment, when performing step S101, the thickness of the preferred orientation layer 21 is controlled to be 5%-50% of the total thickness of the dielectric film. As an example, it can be 5%, 10%, 25%, 35%, or 45%. The total thickness of the dielectric film 2 refers to the sum of the thicknesses of the preferred orientation layer 21 and the amorphous non-crystalline layer 22.

[0057] In practice, the thickness of the preferred orientation layer 21 can be controlled to be 5%-50% of the total thickness of the dielectric film by controlling the deposition time.

[0058] In this embodiment, when deposition is performed according to the above process, a preferred orientation layer 21 with crystal orientation and an amorphous non-crystalline layer 22 with non-crystalline orientation can be obtained. When the thickness of the preferred orientation layer 21 accounts for 5%-50% of the total thickness of the dielectric film 2, the dielectric constant of the preferred orientation layer 21 can reach 1-2.4, and the dielectric constant of the amorphous non-crystalline layer 22 can reach 2.5-5. Compared with dielectric films in the prior art, the dielectric film 2 with this dielectric constant has a lower dielectric constant, which can reduce RC (Resistive-capacitive) delay, improve signal transmission speed, and thus improve the performance of the device.

[0059] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0060] In the semiconductor structure formation method provided in this application, when forming a dielectric thin film located between metal structures, a preferred alignment layer is first formed at the bottom, and then an amorphous non-crystalline layer is formed above the preferred alignment layer. The dielectric thin film obtained by this process has a reduced inductance due to the presence of the preferred alignment layer at the bottom, thereby effectively reducing the dielectric constant of the preferred alignment layer and the amorphous non-crystalline layer, thus reducing the dielectric constant of the entire dielectric thin film. This solves the technical problem that dielectric thin films formed by existing processes can no longer meet the performance and speed requirements of current semiconductor structures.

[0061] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0062] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0063] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A semiconductor structure, characterized in that, include: Metal structure; as well as A dielectric thin film disposed between the metal structures, wherein... The dielectric film includes: A preferred orientation layer and an amorphous non-crystalline layer disposed on the preferred orientation layer, wherein the preferred orientation layer is a crystal-oriented film layer and the amorphous non-crystalline layer is a crystal-unoriented film layer.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the preferred alignment layer accounts for 5%-50% of the total thickness of the dielectric film, wherein, The total thickness of the dielectric film refers to the sum of the thicknesses of the preferred orientation layer and the amorphous non-crystalline layer.

3. A method for forming a semiconductor structure, characterized in that, The semiconductor structure includes a metal structure and a dielectric thin film disposed between the metal structures, wherein the method for forming the dielectric thin film includes: A preferred orientation layer is formed, wherein the preferred orientation layer is a crystal-oriented film layer; An amorphous non-crystalline layer is formed on the preferred orientation layer, wherein the amorphous non-crystalline layer is a film layer in which the crystals are not oriented.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The formation of the preferred orientation layer includes: The precursor is deposited in an atomic layer deposition apparatus to form the preferred orientation layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, When performing the step of forming the preferred orientation layer, the temperature of the process chamber of the atomic layer deposition equipment is 400°C to 700°C, and the power of the atomic layer deposition equipment is 1000W to 3000W.

6. The method for forming a semiconductor structure according to any one of claims 3 to 5, characterized in that, When performing the step of forming the preferred orientation layer, if the dielectric film is silicon dioxide, the ratio of silicon atoms to oxygen atoms provided by the precursor is 0.6 to 1.

7. The method for forming a semiconductor structure as described in claim 3, characterized in that, When performing the step of forming the preferred orientation layer, the thickness of the preferred orientation layer is controlled to be 5%-50% of the total thickness of the dielectric film, where the total thickness of the dielectric film refers to the sum of the thicknesses of the preferred orientation layer and the amorphous non-crystalline layer.

8. The method for forming a semiconductor structure as described in claim 3, characterized in that, An amorphous, non-crystalline layer is formed on the preferred orientation layer, including: The precursor is deposited in an atomic layer deposition apparatus to form the amorphous, non-crystalline layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, When performing the step of forming the amorphous non-crystalline layer, the temperature of the process chamber of the atomic layer deposition equipment is 200°C to 400°C, and the power of the atomic layer deposition equipment is 50W to 1000W.

10. The method for forming a semiconductor structure according to any one of claims 7 to 9, characterized in that, When performing the step of forming the amorphous non-crystalline layer, if the dielectric film is silicon dioxide, the ratio of silicon atoms to oxygen atoms provided by the precursor is 0.1-0.7.

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