Bootstrap diode and semiconductor device

Abstract

A bootstrap diode including a bootstrap cathode terminal and a bootstrap anode terminal includes a junction field effect transistor, a P-type transistor, and a diode. The junction field effect transistor includes a first gate terminal coupled to a ground terminal, a first source / drain terminal, and a second source / drain terminal coupled to the bootstrap cathode terminal. The P-type transistor includes a second gate terminal coupled to a ground terminal, a third source / drain terminal coupled to a ground terminal, and a fourth source / drain terminal coupled to the bootstrap anode terminal. The diode includes a cathode terminal coupled to the first source / drain terminal of the junction field effect transistor and an anode terminal coupled to the bootstrap anode terminal. The present application helps to reduce circuit complexity and circuit area, can provide considerable forward conduction current, withstand higher reverse bias voltage, and significantly reduce current leakage to the substrate.

Description

Technical Field

[0001] The present invention relates to a bootstrap diode, and more particularly to a bootstrap diode composed of a junction field-effect transistor (JFET), a P-type transistor, and a diode. Background Art

[0002] Improving energy efficiency is gaining increasing attention, and offline power converters that can reduce power consumption are becoming increasingly important. In response to market changes, high-voltage integrated circuits (HVICs) with higher performance and greater cost-effectiveness have gradually been adopted, providing designers with flexible solutions for implementing high-efficiency power converters.

[0003] A high-voltage integrated circuit chip functions as a gate driver, for example, to drive a power metal oxide semiconductor (MOSFET) or an insulated gate bipolar transistor (IGBT). A bootstrap diode, capacitor, and resistor are typically used to form a bootstrap circuit. This circuit uses the floating source voltage level of the power metal oxide semiconductor (MOSFET) in a high-side circuit as a reference to provide the voltage level of the high-voltage integrated circuit.

[0004] However, bootstrap diodes often suffer from leakage into the semiconductor substrate during forward conduction. Furthermore, typical bootstrap diodes cannot withstand high voltages. When the reverse bias voltage on the bootstrap diode is too high, the bootstrap diode collapses and conducts, defeating the bootstrap diode's purpose of unidirectional conduction. Therefore, it is necessary to optimize the bootstrap diode's leakage and withstand voltage, while also increasing its forward current. Summary of the Invention

[0005] The present invention proposes a semiconductor device that functions as a bootstrap diode. Because the semiconductor device of the present invention requires no additional circuit control, it helps reduce circuit complexity and area. Furthermore, the semiconductor device of the present invention can provide substantial forward current, withstand high reverse bias voltages, and significantly reduce current leakage to the substrate.

[0006] In view of this, the present invention proposes a bootstrap diode, comprising a bootstrap cathode terminal and a bootstrap anode terminal. The bootstrap diode comprises a junction field-effect transistor, a P-type transistor, and a diode. The junction field-effect transistor comprises a first gate terminal coupled to a ground terminal, a first source / drain terminal, and a second source / drain terminal coupled to the bootstrap cathode terminal. The P-type transistor comprises a second gate terminal coupled to the ground terminal, a third source / drain terminal coupled to the ground terminal, and a fourth source / drain terminal coupled to the bootstrap anode terminal. The diode comprises a cathode terminal coupled to the first source / drain terminal and an anode terminal coupled to the bootstrap anode terminal.

[0007] According to one embodiment of the present invention, a bootstrap diode further includes a substrate, a first N-type well, a first N-type buried layer, a second N-type buried layer, and a second N-type well. The first N-type well is formed in the substrate. The first N-type buried layer is formed above the first N-type well. The second N-type buried layer is formed above the first N-type well, wherein a distance is provided between the first N-type buried layer and the second N-type buried layer. The second N-type well is formed above the first N-type buried layer and the second N-type buried layer, wherein the junction field-effect transistor, the P-type transistor, and the diode are formed in the second N-type well.

[0008] According to one embodiment of the present invention, the bootstrap diode further includes a first P-type well, a second P-type well, a first P-type doped region, a third N-type well, and a first N-type doped region. The first P-type well is formed in the second N-type well and is located above the spacing. The second P-type well is formed in the first P-type well. The first P-type doped region is formed in the second P-type well, wherein the first P-type doped region forms the first gate terminal. The third N-type well is formed in the second N-type well and is located on one side of the first P-type well. The first N-type doped region is formed in the third N-type well, wherein the first N-type doped region forms the second source / drain terminal, and wherein the second N-type well forms the first source / drain terminal.

[0009] According to one embodiment of the present invention, the bootstrap diode further includes a third P-type well, a second P-type doped region, a first P-type drift region, a second P-type drift region, and a gate structure. The third P-type well is formed in the second N-type well, wherein the third P-type well and the third N-type well are located on opposite sides of the first P-type well. The second P-type doped region is formed in the third P-type well, wherein the second P-type doped region forms the fourth source / drain terminal. The first P-type drift region is formed in the second N-type well and is located between the first P-type doped region and the second P-type doped region, wherein the first P-type drift region is connected to the second P-type doped region. The second P-type drift region is formed between the first P-type doped region and the first N-type doped region. The gate structure is formed above the first P-type drift region and adjacent to the first P-type doped region, wherein the gate structure forms the second gate terminal, and wherein the first P-type doped region also forms the third source / drain terminal.

[0010] According to an embodiment of the present invention, the second P-type doped region forms an anode terminal of the diode, and the second N-type well forms a cathode terminal of the diode.

[0011] According to another embodiment of the present invention, the bootstrap diode further includes a P-type buried layer formed in the gap between the first N-type buried layer and the second N-type buried layer.

[0012] According to another embodiment of the present invention, the bootstrap diode further includes a fourth P-type well. The fourth P-type well is formed in the first N-type well and is located below the gap.

[0013] The present invention further provides a semiconductor device comprising a substrate, a first N-type well, a first N-type buried layer, a second N-type buried layer, a second N-type well, a first P-type doped region, a first N-type doped region, a second P-type doped region, and a gate structure. The first N-type well is formed in the substrate. The first N-type buried layer is formed above the first N-type well. The second N-type buried layer is formed above the first N-type well, with a spacing between the first N-type buried layer and the second N-type buried layer. The second N-type well is formed above the first N-type buried layer and the second N-type buried layer, with a first source / drain terminal of a junction field-effect transistor formed in the second N-type well. The first P-type doped region is formed in the second N-type well and located above the spacing. The first P-type doped region forms a first gate terminal of the junction field-effect transistor and a third source / drain terminal of a P-type transistor. The first P-type doped region is coupled to a ground terminal. The first N-type doped region is formed in the second N-type well, wherein the first N-type doped region forms a second source / drain terminal of the junction field effect transistor. The second P-type doped region is formed in the second N-type well, wherein the first N-type doped region and the second P-type doped region are respectively located on different sides of the first P-type doped region, wherein the second P-type doped region forms a fourth source / drain terminal of the P-type transistor. The gate structure is formed on the second N-type well, located between the first P-type doped region and the second P-type doped region and adjacent to the first P-type doped region, wherein the gate structure forms a second gate terminal of the P-type transistor and is coupled to the ground terminal.

[0014] According to an embodiment of the present invention, the second P-type doped region forms an anode terminal of a diode, and the second N-type well forms a cathode terminal of the diode.

[0015] According to one embodiment of the present invention, the second P-type doped region is coupled to a first node, and the first N-type doped region is coupled to a second node, wherein when the voltage of the first node exceeds the voltage of the second node, the semiconductor device provides the voltage of the first node to the second node.

[0016] According to another embodiment of the present invention, when the voltage of the second node exceeds the voltage of the first node, the semiconductor device electrically isolates the first node from the second node.

[0017] According to one embodiment of the present invention, the semiconductor device further includes a first P-type well, a second P-type well, a third N-type well, a third P-type well, a first P-type drift region, and a second P-type drift region. The first P-type well is formed in the second N-type well. The second P-type well is formed in the first P-type well, wherein the first P-type doped region is formed in the second P-type well. The third N-type well is formed in the second N-type well, wherein the first N-type doped region is formed in the third N-type well. The third P-type well is formed in the second N-type well, wherein the second P-type doped region is formed in the third P-type well. The first P-type drift region is formed in the second N-type well and is located below the gate structure, wherein the first P-type drift region is connected to the second P-type doped region. The second P-type drift region is formed between the first P-type doped region and the first N-type doped region.

[0018] According to another embodiment of the present invention, the semiconductor device further includes a P-type buried layer formed in the gap between the first N-type buried layer and the second N-type buried layer.

[0019] According to another embodiment of the present invention, the semiconductor device further includes a fourth P-type well formed in the first N-type well and located below the gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A circuit diagram showing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 2 A block diagram showing a power driving circuit according to an embodiment of the present invention;

[0022] Figure 3 A cross-sectional view showing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 4 A cross-sectional view showing a semiconductor device according to another embodiment of the present invention; and

[0024] Figure 5 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown.

[0025]

Explanation of symbols

[0026] 100, 300, 400, 500: Semiconductor devices

[0027] 110: Junction Field Effect Transistor

[0028] 120: P-type transistor

[0029] 130: diode

[0030] N1: first node

[0031] N2: Second node

[0032] NA: Anode end

[0033] NC: cathode terminal

[0034] G1: first gate terminal

[0035] G2: second gate terminal

[0036] S1 / D1: First source / drain terminal

[0037] S2 / D2: Second source / drain terminal

[0038] S3 / D3: third source / drain terminal

[0039] S4 / D4: fourth source / drain terminal

[0040] 200: Power drive circuit

[0041] 210: Lower bridge driver

[0042] 220: Upper bridge driver

[0043] MHS: High-side transistor

[0044] MLS: Low-bridge transistor

[0045] SO: output signal

[0046] SLD: driving signal

[0047] CBT: Bootstrap capacitor

[0048] VBT: Bootstrap voltage

[0049] VDD: supply voltage

[0050] VH: upper bridge voltage

[0051] HV: External voltage

[0052] PSUB: substrate

[0053] NW1: First N-type well

[0054] NBL1: first N-type buried layer

[0055] NBL2: Second N-type buried layer

[0056] NW2: Second N-type well

[0057] NW3: The third N-type well

[0058] S: Spacing

[0059] PW1: The first P-type well

[0060] PW2: Second P-type well

[0061] PW3: The third P-type well

[0062] 311: first P-type doping region

[0063] 312: first N-type doping region

[0064] 313: second P-type doping region

[0065] 321: First P-type drift region

[0066] 322: Second P-type drift region

[0067] 331: Gate structure

[0068] 341: First isolation structure

[0069] 342: Second isolation structure

[0070] 343: Third Isolation Structure

[0071] 344: Fourth isolation structure

[0072] PBL: P-type buried layer

[0073] PW4: The fourth P-type well DETAILED DESCRIPTION

[0074] The following is a detailed description of the component substrate, semiconductor device and semiconductor device manufacturing method of some embodiments of the present application. It should be understood that the following description provides many different embodiments or examples for implementing different modes of some embodiments of the present application. The specific components and arrangements described below are only for a simple and clear description of some embodiments of the present application. Of course, these are only for illustrative purposes and are not limitations of the present application. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for a simple and clear description of some embodiments of the present application and do not represent any correlation between the different embodiments and / or structures discussed. Furthermore, when a first material layer is mentioned as being on or above a second material layer, it includes a situation where the first material layer is in direct contact with the second material layer. Alternatively, there may be a situation where there are one or more other material layers in between, in which case the first material layer and the second material layer may not be in direct contact.

[0075] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It is understood that if the device in the drawings is turned upside down, the element described as being on the "lower" side will become the element on the "upper" side.

[0076] Here, the terms "about," "approximately," and "substantially" generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given herein are approximate quantities, that is, in the absence of specific indication of "about," "approximately," or "substantially," the meaning of "about," "approximately," or "substantially" may still be implied.

[0077] It is understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are merely used to distinguish different elements, components, regions, layers, and / or parts. Thus, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present application.

[0078] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this application, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the examples of this application.

[0079] Some embodiments of the present application can be understood in conjunction with the drawings, and the drawings of the embodiments of the present application are also considered part of the description of the embodiments of the present application. It should be understood that the drawings of the embodiments of the present application are not drawn to the scale of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly illustrate the features of the embodiments of the present application. In addition, the structures and devices in the drawings are illustrated in a schematic manner to clearly illustrate the features of the embodiments of the present application.

[0080] In some embodiments of the present application, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as referring to the orientations depicted in the paragraph and related drawings. Such relative terms are only for the convenience of explanation and do not imply that the device described therein must be manufactured or operated in a specific orientation. Terms related to joining and connection, such as "connect", "interconnect", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with another structure being located between the two structures. Furthermore, such terms related to joining and connection may also include situations where both structures are movable or both structures are fixed.

[0081] Embodiments of the present invention disclose embodiments of semiconductor devices that may be included in integrated circuits (ICs) such as microprocessors, memory devices, and / or other devices. The ICs may also include various passive and active microelectronic components, such as thin-film resistors, other types of capacitors, such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors, or other types of transistors. A person skilled in the art will appreciate that the semiconductor device may also be used to include other types of semiconductor components in an IC.

[0082] Figure 1 A circuit diagram of a semiconductor device according to an embodiment of the present invention is shown. Figure 1 As shown, the semiconductor device 100 includes a junction field effect transistor 110, a P-type transistor 120, and a diode 130. According to one embodiment of the present invention, the semiconductor device 100 is used as a bootstrap diode and has the characteristics of low semiconductor substrate leakage and high reverse voltage resistance (i.e., when the voltage of the second node N2 is much greater than the voltage of the first node N1), while also having a high forward current, which will be described in detail below.

[0083] like Figure 1As shown, the semiconductor device 100 further includes a first node N1 and a second node N2. According to one embodiment of the present invention, when the voltage of the first node N1 exceeds the voltage of the second node N2, the semiconductor device 100 provides the voltage of the first node N1 to the second node N2. According to another embodiment of the present invention, when the voltage of the second node N2 exceeds the voltage of the first node N1, the semiconductor device 100 is configured to electrically isolate the first node N1 from the second node N2. According to one embodiment of the present invention, when the semiconductor device 100 functions as a bootstrap diode, the first node N1 serves as the anode terminal of the bootstrap diode, and the second node N2 serves as the cathode terminal of the bootstrap diode.

[0084] The junction field effect transistor 110 includes a first source / drain terminal S1 / D1, a second source / drain terminal S2 / D2, and a first gate terminal G1, wherein the first gate terminal G1 is coupled to the ground terminal, and the second source / drain terminal S2 / D2 is coupled to the second node N2. Figure 1 As shown, the junction field effect transistor 110 is an N-type junction field effect transistor.

[0085] The P-type transistor 120 includes a third source / drain terminal S3 / D3, a fourth source / drain terminal S4 / D4, and a second gate terminal G2. The third source / drain terminal S3 / D3 and the second gate terminal G2 are both coupled to ground, and the fourth source / drain terminal S4 / D4 is coupled to the first node N1. The diode 130 includes an anode terminal NA and a cathode terminal NC. The anode terminal NA is coupled to the first node N1 and the fourth source / drain terminal S4 / D4, and the cathode terminal NC is coupled to the first source / drain terminal S1 / D1.

[0086] According to one embodiment of the present invention, when the semiconductor device 100 functions as a bootstrap diode and the voltage at the first node N1 exceeds the voltage at the second node N2, both the junction field effect transistor 110 and the p-type transistor 120 are turned on, so that current flows from the first node N1 to the second node N2 through the channels of the p-type transistor 120 and the junction field effect transistor 110. According to another embodiment of the present invention, when the voltage at the second node N2 exceeds the voltage at the first node N1, both the junction field effect transistor 110 and the p-type transistor 120 are turned off, and the second source / drain terminals S2 / D2 are used to withstand the high reverse voltage received by the second node N2.

[0087] Figure 2 A block diagram of a power driving circuit according to an embodiment of the present invention is shown. Figure 2As shown, the power driver circuit 200 is used to alternately turn on the high-bridge transistor MHS and the low-bridge transistor MLS to generate the output signal SO, wherein the supply voltage VDD is less than the external voltage HV. The power driver circuit 200 includes a low-bridge driver 210, a semiconductor device 100, a bootstrap capacitor CBT, and a high-bridge driver 220.

[0088] According to one embodiment of the present invention, the low-bridge driver 210 outputs a low-bridge drive signal SLD, which turns on the low-bridge transistor MLS and turns off the high-bridge transistor MHS according to the low-bridge driver signal SLD, thereby pulling the output signal SO to ground. Simultaneously, the supply voltage VDD charges the bootstrap capacitor CBT through the semiconductor device 100, causing the bootstrap capacitor CBT to generate a bootstrap voltage VBT, wherein the bootstrap voltage VBT does not exceed the supply voltage VDD.

[0089] According to another embodiment of the present invention, when the lower bridge transistor MLS is turned off in response to the lower bridge drive signal SLD from the lower bridge driver 210 and the high bridge transistor MHS is turned on, the output signal SO is pulled up to the external voltage HV. The bootstrap capacitor CBT boosts the high bridge voltage VH to the sum of the bootstrap voltage VBT and the external voltage HV, allowing the high bridge driver 220 to fully turn on the high bridge transistor MHS. Furthermore, the semiconductor device 100 is turned off to electrically isolate the high bridge voltage VH from the supply voltage VDD.

[0090] Therefore, the semiconductor device 100 can operate independently without the need for a control circuit, which helps reduce circuit complexity and circuit area. In addition, the second source / drain terminals S2 / D2 of the junction field effect transistor 110 have a much higher voltage resistance than that of a general diode, allowing the semiconductor device 100 to withstand a higher reverse bias voltage than a general diode.

[0091] Figure 3 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. Figure 3 As shown, the semiconductor device 300 includes a substrate PSUB, a first N-type well NW1 , a first N-type buried layer NBL1 , a second N-type buried layer NBL2 , and a second N-type well NW2 .

[0092] The substrate PSUB is P-type, a first N-type well NW1 is formed in the substrate PSUB, and a first N-type buried layer NBL1 and a second N-type buried layer NBL2 are formed above the first N-type well NW1, with a spacing S between the first N-type buried layer NBL1 and the second N-type buried layer NBL2. The present invention is not limited to the method for forming the first N-type buried layer NBL1 and the second N-type buried layer NBL2. According to one embodiment of the present invention, the first N-type buried layer NBL1 and the second N-type buried layer NBL2 can be formed by ion implantation. For example, phosphorus ions or arsenic ions can be implanted into the regions where the first N-type buried layer NBL1 and the second N-type buried layer NBL2 are to be formed to form the N-type first N-type buried layer NBL1 and the second N-type buried layer NBL2.

[0093] The second N-type well NW2 is formed on the first N-type buried layer NBL1 and the second N-type buried layer NBL2. Figure 1 The junction field-effect transistor 110, the P-type transistor 120, and the diode 130 are formed in the second N-well NW2. According to one embodiment of the present invention, the impurity concentrations of the first N-type buried layer NBL1 and the second N-type buried layer NBL2 are higher than the impurity concentrations of the first N-well NW1 or the second N-well NW2. According to one embodiment of the present invention, the first N-well NW1 is a pre-drift region doped (Pre-HVNW). According to one embodiment of the present invention, the second N-well NW2 is a high-voltage well region or an epitaxial layer.

[0094] like Figure 3 As shown, the semiconductor device 300 further includes a first P-type well PW1, a second P-type well PW2, a first P-type doping region 311, a third N-type well NW3, a first N-type doping region 312, a third P-type well PW3, a second P-type doping region 313, a first P-type drift region 321, a second P-type drift region 322 and a gate structure 331.

[0095] The first P-type well PW1 is formed in the second N-type well NW2 and is located above the spacing S. The second P-type well PW2 is formed in the first P-type well PW1, and the first P-type doping region 311 is formed in the second P-type well PW2. According to one embodiment of the present invention, the first P-type well PW1 is a high-voltage well region. According to one embodiment of the present invention, the doping concentration of the second P-type well PW2 is higher than the doping concentration of the first P-type well PW1. According to one embodiment of the present invention, the first P-type doping region 311 is formed Figure 1 The first gate terminal G1 of the junction field effect transistor 110 and the third source / drain terminal S3 / D3 of the P-type transistor 120 are connected.

[0096] The third N-type well NW3 is formed in the second N-type well NW2 and is located on one side of the first P-type well PW1. The first N-type doping region 312 is formed in the third N-type well NW3. According to one embodiment of the present invention, the first N-type doping region 312 is used to form Figure 1 The second source / drain terminal S2 / D2 of the junction field effect transistor 110 and the second N-type well NW2 are formed. Figure 1 The first source / drain terminal S1 / D1 of the junction field effect transistor 110 is connected to the first source / drain terminal S1 / D1 of the junction field effect transistor 110.

[0097] The third P-type well PW3 is formed in the second N-type well NW2, wherein the third P-type well PW3 and the third N-type well NW3 are located on different sides of the first P-type well PW1. The second P-type doping region 313 is formed in the third P-type well PW3. According to one embodiment of the present invention, the second P-type doping region 313 is formed. Figure 1 The fourth source / drain terminal S4 / D4 of the P-type transistor 120.

[0098] According to one embodiment of the present invention, the second P-type doping region 313 is formed Figure 1 The anode terminal NA of the diode 130 and the second N-type well NW2 are formed Figure 1 In other words, the junction of the third P-type well PW3 and the second N-type well NW2 forms a cathode terminal NC of the diode 130. Figure 1 diode 130.

[0099] The first P-type drift region 321 is formed in the second N-type well NW2 and is located between the first P-type doped region 311 and the second P-type doped region 313. According to one embodiment of the present invention, the first P-type drift region 321 is interconnected with the second P-type doped region 313. According to another embodiment of the present invention, the first P-type drift region 321 may also be interconnected with the third P-type well PW3.

[0100] The second P-type drift region 322 is formed between the first P-type doping region 311 and the first N-type doping region 312. According to one embodiment of the present invention, the second P-type drift region 322 is interconnected with the first N-type doping region 312. According to another embodiment of the present invention, the second P-type drift region 322 is interconnected with the third N-type well NW3. According to another embodiment of the present invention, the second P-type drift region 322 is separated from the first N-type doping region 312 or the third N-type well NW3.

[0101] The gate structure 331 is formed on the first P-type drift region 321 and adjacent to the first P-type doping region 311. According to one embodiment of the present invention, the gate structure 331 is formed Figure 1 The second gate terminal G2 of the P-type transistor 120.

[0102] The semiconductor device 300 further includes a first isolation structure 341, a second isolation structure 342, a third isolation structure 343, and a fourth isolation structure 344. The first isolation structure 341 is adjacent to the second P-type doping region 313 and is used to isolate the second P-type doping region 313 from other components. Figure 3 As shown, the first isolation structure 341 directly contacts the second P-type doping region 313 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure 341 does not contact the second P-type doping region 313 .

[0103] The second isolation structure 342 is located in the first P-type doping region 311 and the second P-type doping region 313 and is located above the first P-type drift region 321. According to one embodiment of the present invention, the gate structure 331 covers the second isolation structure 342. Figure 3 As shown, the second isolation structure 342 directly contacts the second P-type doping region 313 and is away from the first P-type doping region 311 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure 342 does not contact the second P-type doping region 313 .

[0104] The third isolation structure 343 is located between the first P-type doping region 311 and the first N-type doping region 312 and above the second P-type drift region 322. Figure 3 As shown, the third isolation structure 343 directly contacts the first P-type doping region 311 and the first N-type doping region 312, but this is not intended to limit the present invention. According to other embodiments of the present invention, the third isolation structure 343 does not contact the first P-type doping region 311 and / or the first N-type doping region 312.

[0105] like Figure 3 As shown, the first P-type doping region 311 and the gate structure 331 are connected through the interconnect structure ( Figure 3 Not shown) is electrically connected to the ground terminal, and the first N-type doped region 312 is electrically connected to the ground terminal through the interconnection structure ( Figure 3 Not shown) is electrically connected to the second node N2, and the second P-type doping region 313 is connected to the second node N2 through the interconnection structure ( Figure 3 not shown) are electrically connected to Figure 1 According to one embodiment of the present invention, the semiconductor device 300 corresponds to Figure 1 semiconductor device 100.

[0106] In other words, the second N-type well NW2, the first P-type doping region 311 and the first N-type doping region 312 form Figure 1 The junction field effect transistor 110, the first P-type doping region 311, the gate structure 331 and the second P-type doping region 313 form Figure 1 The P-type transistor 120, the second P-type doping region 313 and the second N-type well NW2 form Figure 1 According to one embodiment of the present invention, the distance S between the first N-type buried layer NBL1 and the second N-type buried layer NBL2 is conducive to pinching off. Figure 1 The channel of the junction field effect transistor 110 is connected to the junction field effect transistor 110, so as to improve the performance of the semiconductor device 300 when the semiconductor device 300 is reverse biased.

[0107] According to one embodiment of the present invention, when the second P-type doped region 313 leaks to the substrate PSUB, the second P-type doped region 313, the N-type well (including the first N-type well NW1, the second N-type well NW2, and the parasitic PNP transistor of the substrate PSUB) must be turned on. Since the depth of the N-type well formed by the first N-type well NW1, the first N-type buried layer NBL1, the second N-type buried layer NBL2, and the second N-type well region NW2 is relatively deep, the current gain of the parasitic PNP transistor is reduced, thereby helping to reduce the magnitude of the leakage current from the second P-type doped region 313 to the substrate PSUB.

[0108] According to one embodiment of the present invention, when the voltage of the first node N1 exceeds the voltage of the second node N2, current flows from the first node N1 through the second P-type doping region 313 and the first P-type drift region 321, turning on the P-type transistor, and passes through the first P-type well PW1, the second P-type drift region 322, and the first N-type doping region 312 to the second node N2, thereby obtaining a considerable forward conduction current.

[0109] According to another embodiment of the present invention, when the voltage of the second node N2 exceeds the voltage of the first node N1, the depletion region generated by the first P-type well PW1 and the second N-type well NW2, the first N-type buried layer NBL1 and the second N-type buried layer NBL2 blocks the channel, so that current cannot flow from the second node N2 to the first node N1.

[0110] Figure 4 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown. Figure 3 The semiconductor device 300 and Figure 4 Compared with the semiconductor device 400, the semiconductor device 400 further includes a P-type buried layer PBL. Figure 4 As shown, the P-type buried layer PBL is located between the first N-type buried layer NBL1 and the second N-type buried layer NBL2 , that is, the P-type buried layer PBL fills the space of the interval S.

[0111] According to one embodiment of the present invention, the P-type buried layer PBL helps to adjust Figure 1According to another embodiment of the present invention, when the semiconductor device 400 is forward biased, that is, when the voltage at the first node N1 exceeds the voltage at the second node N2, the second P-type doped region 313, the second N-well NW2, the P-type buried layer PBL, the first N-well NW1, and the substrate PSUB form a PNPNP structure, which helps to further reduce the leakage current from the second P-type doped region 313 to the substrate PSUB.

[0112] Figure 5 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown. Figure 3 The semiconductor device 300 and Figure 5 Compared to the semiconductor device 500, the semiconductor device 500 further includes a fourth P-type well PW4. Figure 5 As shown, the fourth P-type well PW4 is located below and between the first N-type buried layer NBL1 and the second N-type buried layer NBL2 to fill the gap of the interval S.

[0113] According to one embodiment of the present invention, the fourth P-type well PW4 helps to adjust Figure 1 According to another embodiment of the present invention, when the semiconductor device 500 is forward biased, that is, when the voltage at the first node N1 exceeds the voltage at the second node N2, the second P-type doped region 313, the second N-well NW2, the fourth P-type well PW4, the first N-well NW1, and the substrate PSUB form a PNPNP structure, which helps further reduce the leakage current from the second P-type doped region 313 to the substrate PSUB.

[0114] The present invention proposes a semiconductor device that functions as a bootstrap diode. Because the semiconductor device of the present invention requires no additional circuit control, it helps reduce circuit complexity and area. Furthermore, the semiconductor device of the present invention can provide substantial forward current, withstand high reverse bias voltages, and significantly reduce current leakage to the substrate.

[0115] Although the embodiments of the present application and their advantages have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present application. In addition, the scope of protection of the present application is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present application. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present application. Therefore, the scope of protection of the present application includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present application also includes the combination of each claim and embodiment.

Claims

1. A bootstrap diode, characterized in that: The invention comprises a bootstrap cathode terminal and a bootstrap anode terminal, wherein the bootstrap diode comprises: a junction field effect transistor comprising a first gate terminal coupled to a ground terminal, a first source / drain terminal, and a second source / drain terminal coupled to the bootstrap cathode terminal; a P-type transistor comprising a second gate terminal coupled to the ground terminal, a third source / drain terminal coupled to the ground terminal, and a fourth source / drain terminal coupled to the bootstrap anode terminal; and A diode includes a cathode terminal coupled to the first source / drain terminal and an anode terminal coupled to the bootstrap anode terminal.

2. The bootstrap diode according to claim 1, wherein: Also includes: a substrate; a first N-type well formed in the substrate; a first N-type buried layer formed on the first N-type well; a second N-type buried layer formed on the first N-type well, wherein a distance exists between the first N-type buried layer and the second N-type buried layer; and A second N-type well is formed on the first N-type buried layer and the second N-type buried layer, wherein the junction field effect transistor, the P-type transistor and the diode are formed in the second N-type well.

3. The bootstrap diode according to claim 2, wherein: Also includes: a first P-type well formed in the second N-type well and located above the gap; a second P-type well formed in the first P-type well; a first P-type doped region formed in the second P-type well, wherein the first P-type doped region forms the first gate terminal; a third N-type well formed in the second N-type well and located on one side of the first P-type well; and A first N-type doped region is formed in the third N-type well, wherein the first N-type doped region forms the second source / drain terminal, and the second N-type well forms the first source / drain terminal.

4. The bootstrap diode according to claim 3, wherein: Also includes: a third P-type well formed in the second N-type well, wherein the third P-type well and the third N-type well are located on two opposite sides of the first P-type well; a second P-type doped region formed in the third P-type well, wherein the second P-type doped region forms the fourth source / drain terminal; a first P-type drift region formed in the second N-type well and located between the first P-type doped region and the second P-type doped region, wherein the first P-type drift region is connected to the second P-type doped region; a second P-type drift region formed between the first P-type doping region and the first N-type doping region; and A gate structure is formed on the first P-type drift region and adjacent to the first P-type doped region, wherein the gate structure forms the second gate terminal, and wherein the first P-type doped region also forms the third source / drain terminal.

5. The bootstrap diode according to claim 4, wherein: The second P-type doped region forms an anode terminal of the diode, and the second N-type well forms a cathode terminal of the diode.

6. The bootstrap diode according to claim 4, wherein: Also includes: A P-type buried layer is formed in the gap between the first N-type buried layer and the second N-type buried layer.

7. The bootstrap diode according to claim 4, wherein: Also includes: A fourth P-type well is formed in the first N-type well and is located below the gap.

8. A semiconductor device, characterized in that: include: a substrate; a first N-type well formed in the substrate; a first N-type buried layer formed on the first N-type well; a second N-type buried layer formed on the first N-type well, wherein a distance exists between the first N-type buried layer and the second N-type buried layer; a second N-type well formed on the first N-type buried layer and the second N-type buried layer, wherein a first source / drain terminal of a junction field effect transistor is formed in the second N-type well; a first P-type doped region formed in the second N-type well and located above the gap, wherein the first P-type doped region forms a first gate terminal of the junction field effect transistor and a third source / drain terminal of a P-type transistor, and wherein the first P-type doped region is coupled to a ground terminal; a first N-type doped region formed in the second N-type well, wherein the first N-type doped region forms a second source / drain terminal of the junction field effect transistor; a second P-type doped region formed in the second N-type well, wherein the first N-type doped region and the second P-type doped region are located on opposite sides of the first P-type doped region, and the second P-type doped region forms a fourth source / drain terminal of the P-type transistor; as well as A gate structure is formed on the second N-type well, located between the first P-type doping region and the second P-type doping region and adjacent to the first P-type doping region, wherein the gate structure forms a second gate terminal of the P-type transistor and is coupled to the ground terminal.

9. The semiconductor device according to claim 8, wherein The second P-type doped region forms an anode terminal of a diode, and the second N-type well forms a cathode terminal of the diode.

10. The semiconductor device according to claim 9, wherein The second P-type doped region is coupled to a first node, and the first N-type doped region is coupled to a second node, wherein when the voltage of the first node exceeds the voltage of the second node, the semiconductor device provides the voltage of the first node to the second node.

11. The semiconductor device according to claim 10, wherein When the voltage of the second node exceeds the voltage of the first node, the semiconductor device electrically isolates the first node from the second node.

12. The semiconductor device according to claim 8, wherein Also includes: a first P-type well formed in the second N-type well; a second P-type well formed in the first P-type well, wherein the first P-type doped region is formed in the second P-type well; a third N-type well formed in the second N-type well, wherein the first N-type doped region is formed in the third N-type well; a third P-type well formed in the second N-type well, wherein the second P-type doped region is formed in the third P-type well; a first P-type drift region formed in the second N-type well and located below the gate structure, wherein the first P-type drift region is connected to the second P-type doped region; and A second P-type drift region is formed between the first P-type doping region and the first N-type doping region.

13. The semiconductor device according to claim 12, wherein: Also includes: A P-type buried layer is formed in the gap between the first N-type buried layer and the second N-type buried layer.

14. The semiconductor device according to claim 12, wherein Also includes: A fourth P-type well is formed in the first N-type well and is located below the gap.

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