Nanoplate transistors with wraparound contacts

Abstract

Embodiments include a method of forming a semiconductor device and the resulting device. The method can include forming a source / drain on an exposed portion of a semiconductor layer of a layered nanosheet. The method can include forming a sacrificial material on the source / drain. The method can include forming a dielectric layer covering the sacrificial material. The method can include replacing the sacrificial material with a contact liner. The semiconductor device can include a first gate nanosheet stack and a second gate nanosheet stack. The semiconductor device can include a first source / drain in contact with the first nanosheet stack and a second source / drain in contact with the second nanosheet stack. The semiconductor device can include a source / drain dielectric between the first source / drain and the second source / drain. The semiconductor device can include a contact liner in contact with the first source / drain, the second source / drain, and the source / drain dielectric.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more specifically, to the formation of nanosheet transistors on bulk materials. Background Technology

[0002] FinFETs are an emerging technology that offers a solution to the scaling problem of field-effect transistors (FETs) at and below the 22-nanometer node. A FinFET structure may include at least a narrow semiconductor fin with a gate on at least two sides of each semiconductor fin, and source and drain regions adjacent to the fin on opposite sides of the gate. A FinFET structure with n-type source and drain regions can be referred to as an nFETFET, while a FinFET structure with p-type source and drain regions can be referred to as a pFETFET.

[0003] The degree of control over electron transport in the channel region of a field-effect transistor (FET) is a major factor determining the level of leakage current. Configurations such as the gate-all-around design in nanosheet FETs are ways to enhance control over electron transport in the channel region. However, using semiconductor-on-insulator (SOI) substrates in integrated solutions increases manufacturing costs because SOI substrates are more expensive than bulk substrates. Summary of the Invention

[0004] The embodiments include a method of forming a semiconductor device. The method may include forming source / drain electrodes on exposed portions of semiconductor layers of a layered nanosheet, wherein the layered nanosheet comprises multiple layers. The method may include forming a sacrificial material on the source / drain electrodes. The method may include forming a dielectric layer covering the sacrificial material. The method may include removing the sacrificial material to form contact voids. The method may include depositing contact pads into the contact voids.

[0005] The embodiments include a semiconductor device. The semiconductor device may include a first gate nanosheet stack. The semiconductor device may include a second gate nanosheet stack. The semiconductor device may include a first source / drain in contact with the first nanosheet stack. The semiconductor device may include a second source / drain in contact with the second nanosheet stack. The semiconductor device may include a source / drain dielectric located between the first source / drain and the second source / drain. The semiconductor device may include contact pads in contact with the first source / drain, the second source / drain, and the source / drain dielectric. Attached Figure Description

[0006] Figure 1 A gate through a nanosheet stack is shown according to an exemplary embodiment, wherein the x-axis and y-axis describe the cross-sections used in the following figures;

[0007] Figure 2A A cross-sectional view along the x-axis of a starting substrate is shown according to an exemplary embodiment, wherein the starting substrate has alternating layers of sacrificial material and semiconductor material;

[0008] Figure 2B A cross-sectional view along the y-axis of a starting structure is shown according to an exemplary embodiment, wherein the starting structure has alternating layers of sacrificial material and semiconductor material formed as fins on a substrate, wherein STI separates each fin;

[0009] Figure 3A A cross-sectional view showing the formation of a dummy gate and a gate spacer along the x-axis according to an exemplary embodiment is shown;

[0010] Figure 3B A cross-sectional view showing the formation of a dummy gate and a gate spacer along the y-axis according to an exemplary embodiment is shown;

[0011] Figure 4A A cross-sectional view of spacers formed in a nanosheet region along the x-axis according to an exemplary embodiment is shown;

[0012] Figure 4B A cross-sectional view showing the formation of spacers in a nanosheet region along the y-axis according to an exemplary embodiment is shown.

[0013] Figure 5A A cross-sectional view of source / drain and sacrificial source / drain materials formed along the x-axis according to an exemplary embodiment is shown;

[0014] Figure 5B A cross-sectional view of source / drain and sacrificial source / drain materials formed along the y-axis is shown according to an exemplary embodiment;

[0015] Figure 6A A cross-sectional view along the x-axis of the deposition of the dielectric layer is shown according to an exemplary embodiment;

[0016] Figure 6B A cross-sectional view along the y-axis of the deposition of the dielectric layer is shown according to an exemplary embodiment;

[0017] Figure 7A A cross-sectional view showing the formation of the source / drain dielectric along the x-axis according to an exemplary embodiment is shown;

[0018] Figure 7B A cross-sectional view of a source / drain dielectric formed along the y-axis according to an exemplary embodiment is shown;

[0019] Figure 8A A cross-sectional view of the interlayer dielectric deposited along the x-axis according to an exemplary embodiment is shown;

[0020] Figure 8BA cross-sectional view of an interlayer dielectric deposited along the y-axis according to an exemplary embodiment is shown;

[0021] Figure 9A A cross-sectional view showing an alternative metal gate formed along the x-axis according to an exemplary embodiment is shown;

[0022] Figure 9B A cross-sectional view showing an alternative metal gate formed along the y-axis according to an exemplary embodiment is shown;

[0023] Figure 10A A surface view of removing interlayer dielectric along the x-axis according to an exemplary embodiment is shown;

[0024] Figure 10B A cross-sectional view showing the removal of interlayer dielectric along the y-axis according to an exemplary embodiment is shown;

[0025] Figure 11A A cross-sectional view of the sacrificial source / drain layer removed along the x-axis is shown according to an exemplary embodiment;

[0026] Figure 11B A cross-sectional view of the sacrificial source / drain layer removed along the y-axis is shown according to an exemplary embodiment;

[0027] Figure 12A A cross-sectional view showing a contact pad formed along the x-axis according to an exemplary embodiment is shown;

[0028] Figure 12B A cross-sectional view showing a contact pad formed along the y-axis according to an exemplary embodiment is shown;

[0029] Figure 13A A cross-sectional view showing an electrical contact formed along the x-axis according to an exemplary embodiment is shown; and

[0030] Figure 13B A cross-sectional view showing an electrical contact formed along the y-axis according to an exemplary embodiment is shown.

[0031] The elements in the accompanying drawings are not necessarily drawn to scale and are not intended to depict specific parameters of the invention. For clarity and ease of illustration, the dimensions of elements may be exaggerated. Precise dimensions should be obtained by referring to the detailed description. The drawings are intended only to illustrate typical embodiments of the invention and should not be considered as limiting the scope of the invention. Similar reference numerals denote similar elements in the drawings. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of this disclosure to those skilled in the art. In the description, details of known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0033] For the purposes described below, terms such as “up,” “down,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall be used in relation to the disclosed structures and methods oriented as shown in the accompanying drawings. Terms such as “above,” “cover,” “on top,” “on top,” “located,” or “located on top” mean that a first element, such as a first structure, exists on a second element, such as a second structure, wherein an intermediate element, such as an interface structure, may exist between the first and second elements. The term “direct contact” means that the first element (such as the first structure) and the second element (such as the second structure) are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer. The terms substantially, substantially similar, or approximately mean that differences in length, height, or orientation convey no substantial difference between explicitly stated (e.g., phrases without substantially similar terms) and substantially similar variations. In one embodiment, substantial (and its derivative) represents a difference in engineering or manufacturing tolerances generally accepted for similar devices, up to, for example, a deviation of 10% in value or 10° in angle.

[0034] To avoid obscuring the presentation of embodiments of the present invention, some processing steps or operations known in the art may have been combined for presentation and illustrative purposes in the following detailed description, and in some instances may not have been described in detail. In other cases, some processing steps or operations known in the art may not have been described at all. It should be understood that the following description focuses more on the distinguishing features or elements of various embodiments of the present invention.

[0035] As CMOS dimensions continue to shrink, a persistent trade-off exists between reducing the contact resistance between the chip's source / drain and wiring (which can be achieved by increasing the contact surface area between elements) and reducing the gate-to-source / drain capacitance. This trade-off arises when more metal (or conductive material) is located in the source / drain region. While surround contacts have been used previously, this can result in higher gate-to-source / drain capacitance. Therefore, a method can be used to minimize excess conductive material in the source / drain region by limiting the contact thickness of the contact material using a sacrificial layer on the source / drain, and thus, a filling dielectric can be used to replace the excess contact material (which in turn reduces the gate-to-source / drain capacitance).

[0036] refer to Figure 2A In addition to B, the semiconductor structure can be formed from the starting structure 10 having a layered configuration, such as a substrate 100, a spacer layer 110, a semiconductor layer 120, and a sacrificial layer 130. Furthermore, additional embodiments are expected to have additional semiconductor layers and sacrificial layers.

[0037] In some embodiments, substrate 100 may be a bulk substrate. Substrate 100 may be made of any semiconductor material known in the art, including, for example, silicon, germanium, silicon-germanium alloys, silicon carbide, silicon-germanium carbide alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. Additionally, semiconductor layer 120 may be formed using the same type of material as substrate 100. In some embodiments, semiconductor layer 120 may be the same material as substrate 100.

[0038] The sacrificial layer 130 may contain a selected material that can be selectively removed without damaging the substrate 100 and the semiconductor layer 120. In an exemplary embodiment, the sacrificial layer 130 may be selected as silicon-germanium, while the substrate 100 and the semiconductor layer 120 contain silicon.

[0039] Figure 2A and Figure 2B The starting material shown can be achieved by epitaxially growing materials alternately between sacrificial and semiconductor materials on substrate 100. The sacrificial layer 130 can have a thickness ranging from 4 nanometers to about 10 nanometers. The semiconductor layer 120 can have a thickness ranging from 4 nanometers to about 10 nanometers.

[0040] The isolation layer 110 may be an oxide of the SOI starting material, a dielectric material after replacement with a sacrificial material (such as a high-Ge material that can be selectively removed relative to semiconductor layer 120 and sacrificial layer 130), or a dielectric material formed by any other suitable means. The isolation layer 110 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon-based carbon oxide, silicon-based low-k dielectric, flowable oxide, porous dielectric, or organic dielectric including porous organic dielectric, and may be formed using any suitable deposition technique, including ALD, CVD, plasma-enhanced CVD, spin-coating deposition, or PVD. However, in an alternative embodiment, the isolation layer 110 is absent, and the sacrificial layer 130 is formed directly on the substrate 100.

[0041] refer to Figure 3A and Figure 3B A dummy gate can be formed on the first structure 20 and the second structure 30. When forming the dummy gate, it is possible to... Figure 3A and Figure 3B A dummy gate layer is formed on the first structure 20 and the second structure 30 shown. In such an embodiment, the dummy gate layer can be made of any suitable sacrificial material, such as amorphous or polycrystalline silicon. The dummy gate layer can have any thickness ranging from about 30 nanometers to about 200 nanometers. The dummy gate layer can be deposited using any suitable deposition technique known in the art, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), or liquid source atomized chemical deposition (LSMCD).

[0042] After depositing the dummy gate layer, a dummy gate structure comprising a gate hard mask 140, a dummy gate 150, and spacers 160 can be formed. The dummy gate structure can be formed by photolithographically patterning the desired gate region using, for example, the gate hard mask 140, and subsequently etching away the dummy gate layer from the unpatterned areas. Suitable photolithography materials include, for example, a photoresist layer. Etching can be performed using any suitable technique, such as, for example, reactive ion etching (RIE) or wet stripping. Suitable materials for the dummy gate 150 include, but are not limited to, polycrystalline silicon (poly-Si) and / or amorphous silicon (a-Si). The sacrificial gate material can be deposited on the nanosheet device stack 105 using processes such as CVD, ALD, or PVD. Suitable materials for the gate hard mask 140 include, but are not limited to, nitride hard mask materials such as SiN, SiON, and / or SiCN, and / or oxide hard mask materials such as SiOx.

[0043] After the dummy gate 150 is formed, a spacer 160 may be formed around the gate hard mask 140 and the dummy gate 150. The spacer 160 may be made of any insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof, and may have a thickness between 2 nanometers and about 100 nanometers, preferably between about 2 nanometers and about 25 nanometers. The spacer may be made of an insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. The spacer 160 may be formed by any method known in the art, including depositing a conformal silicon nitride layer on the dummy gate 150 and removing unwanted material from the conformal silicon nitride layer using an anisotropic etching process (such as, for example, reactive ion etching (RIE) or plasma etching (not shown)). Methods for forming the spacer are known in the art, and other methods are explicitly contemplated. Additionally, in various embodiments, the spacer 160 may comprise one or more layers.

[0044] Still referencing Figure 3A and Figure 3B Anisotropic etching can be performed to remove material between each dummy gate structure. After anisotropic etching, the gate buffer layer 113, the first gate sacrificial layer 133, the second gate sacrificial layer 136, the first gate semiconductor layer 123, and the second gate semiconductor layer 126 remain only below the dummy gate structures. Anisotropic etching can be achieved by any suitable technique (such as, for example, reactive ion etching (RIE)).

[0045] refer to Figure 4A and Figure 4B An isotropic etching can be performed to pull back or selectively remove material from the first gate sacrificial layer 133 and the second gate sacrificial layer 136 while retaining the first gate semiconductor layer 123 and the second gate semiconductor layer 126, forming a pulled-back first gate sacrificial layer 134 and a pulled-back second gate sacrificial layer 137. The pull-back interleaves the vertical interfaces generated during the anisotropic etching, such that the vertical interfaces of the pulled-back gate buffer layer 114, the pulled-back first gate sacrificial layer 134, and the pulled-back second gate sacrificial layer 137 differ from the vertical interfaces of the first gate semiconductor layer 123 and the second gate semiconductor layer 126. The isotropic etching can be achieved by any suitable technique capable of selectively removing the gate buffer layer 113, the first gate sacrificial layer 133, and the second gate sacrificial layer 136 (such as, for example, wet and dry etching techniques).

[0046] Still referencing Figure 4A and Figure 4B Conformal deposition of insulating layer 170 can be performed. Insulating layer 170 can be deposited by... Figure 6A and Figure 6BThe insulating layer 170 is formed by conformally depositing an insulating material on the exposed surface of the structure described herein. Furthermore, in various embodiments, the insulating layer 170 may include one or more layers. The insulating layer 170 may be any suitable oxide, nitride, or oxynitride material, such as silicon nitride.

[0047] The removal of the insulating layer covering the first gate semiconductor layer 123 and the second gate semiconductor layer 126 can be achieved by any combination of known techniques (such as, for example, RIE, wet stripping, and plasma etching). Due to the anisotropic nature of etching, the insulating layer 170 is retained along the pulled-back first gate sacrificial layer 134 and the pulled-back second gate sacrificial layer 137.

[0048] refer to Figure 5A and Figure 5B Sources / drains 190 can be formed on the exposed surfaces of the first gate semiconductor layer 123 and the second gate semiconductor layer 126 using epitaxial growth, and sacrificial source / drain layers 180 can be formed on the sources / drains 190. The sources / drains 190 can be formed such that the surface of the source / drain 190 contacting the seed layer (i.e., the first gate semiconductor layer 123 and the second gate semiconductor layer 126) is slightly larger than the seed layer. Additionally, when using epitaxial growth, {111} surfaces can be generated, and growth can be stopped so that the source / drain 190 formed from the first gate semiconductor layer 123 does not contact the source / drain 190 formed from the second gate semiconductor layer 126, or continuous semiconductor layers of nanosheets can be merged to produce… Figure 5A and Figure 5B The triangular cross-section depicted in the figure. However, in some embodiments, the source / drain 190 may be grown together, but not to the point of completely filling the space between the first gate and the second gate, or to merge the source / drain of each semiconductor layer of the nanosheet, such that there are no gaps between the structures of the source / drain 190. In some embodiments, the source / drain 190 may be silicon-germanium. In such embodiments, the semiconductor material may contain, for example, about 20% to about 100% germanium, about 0% to about 80% silicon, and may be doped with a concentration of about 1 × 10⁻⁶. 20 atoms / cm 3 Up to approximately 2×10 21 atoms / cm 3 The range includes p-type dopants such as boron. In another example embodiment, the semiconductor material may be carbon-doped silicon. In this embodiment, the semiconductor material may contain, for example, about 0.5% to about 2.5% carbon, about 97.5% to about 99.5% silicon, and may be doped with a concentration of about 1 × 10⁻⁶. 20 atoms / cm 3 Up to approximately 2×10 21 atoms / cm 3The range of n-type dopants, such as arsenic or phosphorus, is considered. Removal of portions of mask layer 180 and the second region mask layer 183 can occur after epitaxial growth. The sacrificial source / drain layer 180 can be epitaxially grown on the surface of the source / drain layer 190. The material of the sacrificial source / drain layer 180 can be selected such that it can be selectively removed relative to the source / drain layer 190 in subsequent steps. The sacrificial source / drain layer 180 can have a thickness of about 1 to about 10 nanometers.

[0049] The terms "epitaxygian growth and / or deposition" and "epitaxygian formation and / or growth" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material can have the same crystal properties as the semiconductor material on the deposition surface. During epitaxial deposition, chemical reactants supplied by a source gas are controlled, and system parameters are set such that the deposition atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves toward the crystal arrangement of atoms on the deposition surface. Therefore, the epitaxial semiconductor material can have the same crystal properties as the deposition surface on which it can be formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface can adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process can be selectively formed on a semiconductor surface and may not deposit material on a dielectric surface (such as a silicon dioxide or silicon nitride surface).

[0050] refer to Figure 6A and Figure 6B A conformal deposition of the source / drain dielectric layer 200 can be performed. The source / drain dielectric layer 200 can be made of any insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. In an example embodiment, SiBCN can be selected as the source / drain dielectric layer 200. The source / drain dielectric layer 200 can be formed by any method known in the art, including conformal deposition. The source / drain dielectric layer 200 can contact the insulating layer 170 to attach between the gate structures and stabilize the source / drain dielectric layer 200.

[0051] refer to Figure 7A and Figure 7B The source / drain dielectric layer 200 can be reduced below the sacrificial source / drain 180 to form the source / drain dielectric layer 205. Isotropic etching suitable for the material can be used to remove material from the previous conformal process.

[0052] refer to Figure 8A and Figure 8BAn interlayer dielectric (ILD) 210 can be formed around the gate. Suitable ILD materials include, but are not limited to, low-κ oxide materials such as silicon oxide (SiOx), and / or, for example, ultra-low-κ oxide interlayer dielectric (ULK-ILD) materials having a dielectric constant κ of less than 2.7. In contrast, silicon dioxide (SiO2) has a dielectric constant κ value of 3.9. Suitable ultra-low-κ dielectric materials include (but are not limited to) porous organosilicon glass (pSiCOH). Processes such as CVD, ALD, or PVD can be used to deposit the ILD 210. After deposition, the ILD 210 can be planarized using processes such as chemical mechanical polishing (CMP).

[0053] refer to Figure 9A and Figure 9B The sacrificial gate 150, the pulled-back first gate sacrificial layer 134, and the pulled-back second gate sacrificial layer 137 can be removed and replaced using a replacement metal gate (RMG) 220. The dummy gate 150 can be removed by any suitable etching process known in the art capable of selectively removing the dummy gate 150 without substantially removing material from the surrounding structure. In an exemplary embodiment, for example, the dummy gate 150 can be removed by a reactive ion etching (RIE) process capable of selectively removing silicon.

[0054] Still referencing Figure 9A and Figure 9B Selective removal of the pulled-back first gate sacrificial layer 134 and the pulled-back second gate sacrificial layer 137 is possible. Any suitable etching process known in the art capable of selectively removing material from the pulled-back first gate sacrificial layer 134 and the pulled-back second gate sacrificial layer 137 while retaining material from the first gate semiconductor layer 123 and the second gate semiconductor layer 126 can be used, and the choice of etching process can depend on the specific material considered.

[0055] Still referencing Figure 9A and Figure 9B The RMG 220 can be formed within the voids. Forming the RMG 220 may include depositing a dielectric, a work function metal, and a gate electrode. In one embodiment, the dielectric layer may include silicon oxide (SiO2). x O y or high-k oxides, such as, for example, hafnium oxide (Hf) x O y Zirconium oxide (Zr) x O y ), aluminum oxide (Al) x O y ), titanium dioxide (Ti x O y ), Lanthanum oxide (La) x Oy ), Strontium titanium oxide (Sr) x Ti y O z ), Lanthanum aluminum oxide (La) x Al y O z ) and mixtures thereof. Any suitable deposition technique known in the art can be used to deposit the dielectric layer, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), or liquid source atomized chemical deposition (LSMCD).

[0056] In some embodiments, a work function metal layer may be deposited after the dielectric layer. The work function metal layer may include, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, TiN, or TaN. The work function metal layer may be formed using any suitable metal deposition technique, including, for example, CVD, PVD, ALD, sputtering, and electroplating. In some embodiments, high-temperature annealing may be performed before depositing the gate electrode.

[0057] The gate electrode can be deposited on a dielectric layer or a work function layer. The gate electrode can be made of a gate conductor material, including but not limited to zirconium, tungsten, tantalum, hafnium, titanium, aluminum, ruthenium, metal carbides, metal nitrides, transition metal aluminum compounds, tantalum carbide, titanium carbide, magnesium tantalum carbide, or combinations thereof. Any suitable metal deposition technique can be used to form the gate electrode, including, for example, CVD, PVD, and ALD, sputtering, and electroplating. Additionally, the sacrificial cap 230 can fill the remainder of the gate opening. The sacrificial cap 230 can be formed using any suitable deposition technique, including ALD, CVD, plasma-enhanced CVD, spin-coating, or PVD. The sacrificial cap 230 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. After the RMG 220 is formed, any suitable dielectric can be used to form the sacrificial cap 230.

[0058] refer to Figure 10A and Figure 10B The ILD 210 can be removed to expose the sacrificial source / drain layer 180. The removal of the ILD 210 can be performed using any suitable etching technique, such as reactive ion etching (RIE) for example.

[0059] refer to Figure 11A and Figure 11BThe sacrificial source / drain layer 180 can be selectively removed, leaving a gap between the source / drain layer 190 and the source / drain dielectric 205. Based on the chemical properties of the sacrificial source / drain layer 180 and the source / drain layer 190, any suitable etching technique can be used to selectively remove the sacrificial source / drain layer 180.

[0060] refer to Figure 12A and Figure 12B Contact pads 240 can be formed in the gaps created during the removal of the sacrificial source / drain layer 180. Metal pads can be conformally deposited, followed by silicided metal using the source / drain to form contact pads 240. Metal pads can include metals such as Co, Ti, Ni, W, Mo, and Ta.

[0061] Reference Figure 13A and Figure 13B Electrical contacts 250 can be deposited. Electrical contacts 250 can be deposited in the source / drain regions. Electrical contacts 250 can include, for example, copper, aluminum, titanium nitride, tantalum nitride, or tungsten. Electrical contacts 250 can be formed using filling techniques such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, or a combination of these methods.

[0062] Following the steps described above, a device with reduced contact resistance (by increasing contact surface area) and reduced gate-to-source / drain capacitance can be formed. The formed structure includes source / drain electrodes 190 that are not fully merged with other portions of the source / drain electrodes 190 on consecutive semiconductor layers (e.g., first gate semiconductor layer 123) or on opposing semiconductor layers (e.g., first gate semiconductor layer 123 and second gate semiconductor layer 126). A layer of contact pad 240 lies on the surface of the source / drain electrodes 190, which can maintain a high contact area indicating the surrounding contact. The contact pad 240 can have a uniform or substantially uniform thickness around each source / drain electrode 190, and the remaining area in the source / drain region is filled with a source / drain dielectric 205. The source / drain dielectric 205 reduces the total volume that can be filled by the contact pad 240, while still achieving a similar contact surface area when the region is fully filled using the contact pad 240. This can reduce the total gate-to-source / drain capacitance around the contact by reducing unnecessary conductive material in the source / drain region, and thus reduce the capacitance generated by the region.

[0063] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. Therefore, the invention is not limited to the precise forms and details described and illustrated, but falls within the scope of the appended claims.

Claims

1. A semiconductor structure, comprising: A first gate nanosheet stack, wherein a first gate portion and a first spacer are formed between two adjacent nanosheets; Second gate nanosheet stack; The first source / drain electrode that is in contact with the stacked first gate nanosheet; The second source / drain electrode is in contact with the stacked second gate nanosheet; A source / drain dielectric is disposed between the first source / drain and the second source / drain, wherein the source / drain dielectric is in contact with the first spacer of the first gate nanosheet stack; as well as A contact pad that is in contact with the first source / drain, the second source / drain, and the source / drain dielectric.

2. The structure according to claim 1, wherein the contact pad has a thickness of 1 nanometer to 10 nanometers.

3. The structure according to claim 1, wherein, The first source / drain includes a first portion on a first nanosheet of the first gate nanosheet stack and a second portion on a second nanosheet adjacent to the first nanosheet, wherein the first portion of the first source / drain is separated from the second portion of the first source / drain.

4. The structure according to claim 1, wherein the first source / drain is in contact with the second source / drain.

5. The structure according to claim 1, wherein the first source / drain is not in contact with the second source / drain.

6. The structure of claim 5, wherein the contact pad is an adjacent layer in contact with the first source / drain and the second source / drain.

7. The structure of claim 1, wherein the second gate nanosheet stack has a second gate portion and a second spacer formed between two adjacent nanosheets, and the source / drain dielectric is also in contact with the second spacer of the second gate nanosheet stack.

8. A method of forming a semiconductor device, the method comprising: Sources / drains are formed on the exposed portion of the semiconductor layer of the first layered nanosheet, wherein a first gate sacrificial layer and a first spacer are formed between two adjacent semiconductor layers; Sacrificial material is formed on the source / drain electrodes; Form a dielectric layer covering the sacrificial material; The sacrificial material is removed to form a contact void, wherein the dielectric layer is in contact with the first spacer of the first layered nanosheet; as well as The contact pad is deposited in the contact gap.

9. The method of claim 8, wherein the material of the contact pad comprises a silicide.

10. The method of claim 8 or 9, wherein the contact pad has a thickness of 1 nanometer to 10 nanometers.

11. The method according to claim 8, wherein, The source / drain includes a first portion on a first semiconductor layer of the first layered nanosheet and a second portion on a second semiconductor layer of the first layered nanosheet adjacent to the first semiconductor layer, wherein the first portion of the source / drain is separated from the second portion of the source / drain.

12. The method of claim 8, comprising: A structure is prepared in which a first layer of nanosheets and a second layer of nanosheets are formed, wherein the second layer of nanosheets has a second gate sacrificial layer and a second spacer formed between two adjacent semiconductor layers, and the dielectric layer is also in contact with the second spacer of the second layer of nanosheets.

13. A method of forming a semiconductor device, the method comprising: A first gate stack and a second gate stack are formed on a substrate, wherein each of the first gate stack and the second gate stack includes a plurality of semiconductor nanosheets, spacers formed between two adjacent semiconductor nanosheets, and a gate portion, wherein a first surface of the first semiconductor nanosheet of the first gate stack and a second surface of the second semiconductor nanosheet of the second gate stack face each other. A first source / drain is formed on the first surface, and a second source / drain is formed on the second surface. Sacrificial material is formed above the first source / drain and the second source / drain. A dielectric layer is formed covering the sacrificial material, wherein the dielectric layer is in contact with the spacer of the first gate stack. Remove the sacrificial material to form a contact gap, and The contact pad is deposited into the contact void.

14. The method of claim 13, wherein the material of the contact pad comprises a silicide.

15. The method of claim 13 or 14, wherein the contact pad has a thickness of 1 nanometer to 10 nanometers.

16. The method according to claim 13, wherein, The first source / drain includes a first portion on the first semiconductor nanosheet of the first gate stack and a second portion on a third semiconductor nanosheet adjacent to the first semiconductor nanosheet, wherein the first portion of the first source / drain is separated from the second portion of the first source / drain.

17. The method of claim 13, wherein the dielectric layer is in contact with the spacer of the second gate stack.

18. The method according to claim 13, wherein, The first source / drain does not contact the second source / drain.

19. The method according to claim 18, wherein, The contact pad is an adjacent layer that contacts the first source / drain and the second source / drain.

20. The method according to claim 13, wherein, The first source / drain is in contact with the second source / drain.

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