Pixel array substrate with reduced crosstalk and manufacturing method

Abstract

A pixel array substrate for reducing crosstalk and a method for manufacturing the pixel array substrate are provided. A pixel array substrate comprises a semiconductor substrate, a buffer layer and a metal ring. The semiconductor substrate comprises a first photodiode region. The rear surface of the semiconductor substrate forms a groove surrounding the first photodiode region in a cross-sectional plane parallel to a first rear surface region of the rear surface above the first photodiode region. The buffer layer is located on the rear surface and has (i) a thin buffer layer region located above the first photodiode region and (ii) a thick buffer layer region forming a ring above the groove in a plane parallel to the cross-sectional plane. The metal ring is located on the buffer layer and covers the thick buffer layer region.

Description

Technical Field

[0001] The present invention relates to a pixel array substrate for reducing crosstalk and a method for manufacturing the pixel array substrate. Background Art

[0002] Camera modules in commercial products such as stand-alone digital cameras, mobile devices, automotive components, and medical devices include image sensors. The image sensor includes a plurality of pixels forming a pixel array and often also includes a plurality of microlenses forming a microlens array and at least one of a plurality of color filters forming a color filter array located between the pixel array and the microlens array. Each color filter of the color filter array is aligned with a corresponding pixel of the pixel array. Similarly, each microlens of the microlens array is aligned with a corresponding pixel of the pixel array. Images produced by image sensors often include artifacts produced by power or light sources. Optical crosstalk is one such artifact and refers to light detected by a first pixel of a pixel array after propagating through a microlens and / or color filter that is aligned with a second pixel of the pixel array. One source of optical crosstalk occurs when incident light propagates through a microlens at a sufficiently high angle of incidence relative to a surface normal of the pixel array. Summary of the invention

[0003] Embodiments disclosed herein reduce optical crosstalk by preventing the above-mentioned sources of crosstalk.

[0004] The present invention provides a pixel array substrate for reducing crosstalk and a method for manufacturing the pixel array substrate.

[0005] In a first aspect, a pixel array substrate includes a semiconductor substrate, a buffer layer, and a metal ring. The semiconductor substrate includes a first photodiode region. The rear surface of the semiconductor substrate forms a groove surrounding the first photodiode region in a cross-sectional plane parallel to a first rear surface region of the rear surface above the first photodiode region. The buffer layer is located on the rear surface and has (i) a thin buffer layer region located above the first photodiode region and (ii) a thick buffer layer region forming a ring above the groove in a plane parallel to the cross-sectional plane. The metal ring is located on the buffer layer and covers the thick buffer layer region.

[0006] In some embodiments, the metal ring includes: a middle segment on the thick buffer layer area; an inner segment surrounded by the middle segment and bonded to both the inner side wall of the middle segment and the inner side wall of the thick buffer layer area; and an outer segment bonded to both the outer side wall of the middle segment and the outer side wall of the thick buffer layer area.

[0007] In some embodiments, the thickness of each of the inner segment and the outer segment is between twenty nanometers and forty nanometers.

[0008] In some embodiments, the pixel array substrate further includes a dielectric annular layer on a top surface of the middle section.

[0009] In some embodiments, the inner segment includes an inner top region bonded to an inner surface of the dielectric annular layer; and the outer segment includes an outer top region bonded to an outer surface of the dielectric annular layer.

[0010] In some embodiments, the pixel array substrate further includes an attenuation layer located on the thin buffer layer region, an inner sidewall of the metal ring, a top surface of the metal ring, and a top surface of the dielectric annular layer.

[0011] In some embodiments, the thick buffer layer region has a thickness between 0.10 microns and 0.16 microns.

[0012] In some embodiments, the width of the thick buffer layer region is between 0.10 microns and 0.25 microns.

[0013] In some embodiments, the thin buffer layer region has a thickness between twenty nanometers and forty nanometers.

[0014] In some embodiments, the pixel array substrate further includes an adhesive layer between the metal ring and the thick buffer layer region.

[0015] In some embodiments, the pixel array substrate further includes an attenuation layer on the thin buffer layer region and an inner sidewall of the metal ring.

[0016] In some embodiments, the attenuation layer is formed of one of titanium and titanium nitride.

[0017] In some embodiments, the metal ring is formed of tungsten.

[0018] In some embodiments, the metal ring has a thickness between 0.1 and 0.3 microns.

[0019] In some embodiments, the pixel array substrate further includes a color filter on the thin buffer layer region and having a thickness exceeding a thickness of the metal ring.

[0020] In some embodiments, the semiconductor substrate further includes four second photodiode regions forming a two-by-two array; and in the cross-sectional plane, the first photodiode region is located within a quadrilateral region defined by respective centers of the four second photodiode regions.

[0021] In some embodiments, the semiconductor substrate also includes a second photodiode region adjacent to a first side edge of the first photodiode region, a third photodiode region adjacent to a second side edge of the first photodiode region, and a fourth photodiode region adjacent to a corner of the first photodiode region and adjacent to each side edge of the second photodiode region and the third photodiode region.

[0022] In a second aspect, a method for manufacturing a pixel array substrate includes (i) forming a metal ring on a buffer layer disposed on a semiconductor substrate; (ii) reducing the thickness of a buffer layer region that is not located below the metal ring to produce a thinned buffer layer; and (iii) depositing a conformal metal layer on the thinned buffer layer and the metal ring.

[0023] In some embodiments, the method further includes: removing at least a portion of the conformal metal layer over a top surface of the metal ring; and removing a portion of the conformal metal layer over a photodiode region of the semiconductor substrate.

[0024] In some embodiments, the method further includes depositing an attenuation layer on (i) a portion of the thinned buffer layer over a photodiode region of the semiconductor substrate and (ii) an inner sidewall of the metal ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Depicts a camera imaging a scene.

[0026] Figure 2 is a cross-sectional schematic diagram of a pixel array substrate. Figure 1 An embodiment of a pixel array substrate for a camera.

[0027] Figure 3 is a cross-sectional schematic diagram of a second pixel array substrate. The second pixel array substrate is Figure 1 An embodiment of a pixel array substrate for a camera.

[0028] Figure 4 is a cross-sectional schematic diagram of a pixel array substrate. Figure 3 An embodiment of a pixel array substrate.

[0029] Figure 5 is a schematic cross-sectional view of a metal ring. Figure 3 An example of a metal ring of a pixel array substrate.

[0030] Figure 6 is a cross-sectional schematic diagram of a pixel array substrate. Figure 3 An embodiment of a pixel array substrate.

[0031] Figure 7 -10 is a corresponding cross-sectional schematic diagram of an intermediate substrate formed in the process of manufacturing a pixel array substrate in an embodiment.

[0032] Fig.11 It is shown in the embodiment for manufacturing Figure 3 A flowchart of a method for a pixel array substrate.

[0033] Fig.12 is a cross-sectional schematic diagram of a pixel array substrate. Figure 3 An embodiment of a pixel array substrate.

[0034] Fig.13 is a cross-sectional schematic diagram of a pixel array substrate. Figure 3 An embodiment of a pixel array substrate. DETAILED DESCRIPTION

[0035] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with that example is included in at least one example of the present invention. Thus, the phrases "in one example" or "in one embodiment" appearing in various places throughout this specification are not necessarily all referring to the same example. Furthermore, in one or more examples, particular features, structures, or characteristics may be combined in any suitable manner.

[0036] For ease of description, spatially relative terms such as "under...", "below...", "below...", "below...", "above...", "on...", etc. may be used herein to describe the relationship of one element or feature to another (multiple) element or feature, as shown in the figure. It will be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as being "under" or "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the terms "under..." and "below..." can cover both the above and below orientations. The device can be oriented in other ways (rotated ninety degrees or in other orientations), and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers.

[0037] The term semiconductor substrate may refer to a substrate formed using semiconductors such as silicon, silicon germanium, germanium, gallium arsenide, and combinations thereof. The term semiconductor substrate may also refer to a substrate formed from one or more semiconductors that has undergone prior process steps to form regions and / or junctions in the substrate. A semiconductor substrate may also include various features such as doped and undoped semiconductors, epitaxial layers of silicon, and other semiconductor structures formed on the substrate.

[0038] Throughout the specification, several technical terms are used. These terms should have their ordinary meaning in the art, unless specifically defined herein or the context of their use clearly implies otherwise. It should be noted that in this document, element names and symbols can be used interchangeably (e.g., Si with silicon); however, both have exactly the same meaning.

[0039] Figure 1 A camera 190 is depicted that images a scene. The camera 190 includes an image sensor 192 that includes a pixel array substrate 100. The constituent elements of the pixel array substrate 100 may include at least one of silicon and germanium. The pixel array substrate 100 includes a pixel array 112A. The image sensor 192 may be part of a chip scale package or a chip on board package.

[0040] Figure 2 2 is a schematic cross-sectional view of a pixel array substrate 200 , which is an example of the pixel array substrate 100 . Figure 2 The cross section shown in is parallel to the plane formed by orthogonal axes A1 and A3, hereinafter referred to as the xz plane, wherein the orthogonal axes A1 and A3 are each orthogonal to the axis A2. In this article, the xy plane is formed by the orthogonal axes A1 and A2, and the plane parallel to the xy plane is referred to as the transverse plane. Unless otherwise specified, the height of an object in this article refers to the extent of the object along the axis A3. In this article, references to axes x, y or z refer to axes A1, A2 and A3, respectively. Moreover, in this article, the horizontal plane is parallel to the xy plane, the width refers to the extent of the object along the y axis, and the vertical direction is along the z axis.

[0041] The pixel array substrate 200 includes a semiconductor substrate 210, a passivation layer 230, a buffer layer 250, a metal ring 270, and a color filter array 280. The metal ring 270 and the color filter array 280 are on the buffer layer 250. The pixel array substrate 200 also includes a microlens array 290, which includes a plurality of microlenses 292 and 293. Each microlens 292 is aligned with a corresponding photodiode region 212 to guide light thereto. Each microlens 293 is aligned with a corresponding photodiode region 213 to guide light thereto.

[0042] The semiconductor substrate 210 includes one or more photodiode regions 212. The rear surface 220 of the semiconductor substrate 210 forms a groove 221 surrounding each photodiode region 212 in a cross-sectional plane of a rear surface region 228 of the rear surface 220 above the photodiode region 212. The groove 221 isolates the small photodiode region 212 from the adjacent large photodiode region 213. The rear surface region 228 may be parallel to the xy plane. The buffer layer 250 is on the rear surface 220 and has a uniform thickness 252.

[0043] The constituent elements of the semiconductor substrate 210 may include at least one of silicon and germanium. The semiconductor substrate 210 includes a front surface 211 opposite to a rear surface 220. The rear surface 220 includes an inner sidewall surface region 222, an outer sidewall surface region 226, and a bottom surface region 224, and the inner sidewall surface region 222, the outer sidewall surface region 226, and the bottom surface region 224 form a groove 221.

[0044] The semiconductor substrate 210 has a thickness 216 between the front surface 211 and the rear surface region 228. The trench 221 has a width 223 and a depth 225 in the horizontal direction and the vertical direction, respectively. The width 223 can be between 0.10 microns and 0.25 microns. The depth 225 is relative to the rear surface region 228 and can be between 0.5 microns and 2.0 microns. In an embodiment, the thickness 216 exceeds the depth 225 by between 0.5 microns and 2.0 microns to ensure sufficient electrical isolation.

[0045] In an embodiment, the passivation layer 230 covers the rear surface region 228 and is located between the metal ring 270 and the semiconductor substrate 210. In an embodiment, the passivation layer 230 is adjacent to the rear surface 220. In an embodiment, an additional material layer is located between the passivation layer 230 and the rear surface 220. The additional layer can be thinner than the passivation layer 230 and can be formed of an oxide. In an embodiment, the passivation layer 230 conformally covers the surface regions 222, 224, and 226 of each trench 221. The passivation layer 230 can be formed of a high-κ material, such as a material having a dielectric constant κ greater than or equal to the dielectric constant of silicon nitride (κ≥7). The passivation layer 230 can have a fixed negative charge, thereby generating a hole accumulation layer at its surface interface with the semiconductor substrate 210. Aluminum oxide (Al2O3) and hafnium oxide (HfO2) are examples of such high-κ materials.

[0046] In an embodiment, each trench 221 is filled with a trench filling material 241. The trench 221, the portion of the passivation layer 230 therein, and the trench filling material 241 form a deep trench isolation (DTI) structure 240. The trench filling material 241 may be an oxide, a metal, or a combination thereof.

[0047] In an embodiment, semiconductor substrate 210 includes a two-dimensional array of photodiode regions 212, wherein respective directions of rows and columns of the two-dimensional array define respective directions of axes A2 and A1. Adjacent photodiode regions 212 are separated in each of the x and y directions by a pixel pitch 214. In an embodiment, each photodiode region 212 is part of a respective pixel of a pixel array formed in semiconductor substrate 210.

[0048] In an embodiment, semiconductor substrate 210 further includes a two-dimensional array of photodiode regions 213. Adjacent photodiode regions 213 are separated by a pixel pitch 214. Each photodiode region 213 is located between a corresponding pair of adjacent photodiode regions 212. Photodiode regions 213 are part of a pixel array that is interleaved with a pixel array that includes a two-dimensional photodiode array of photodiode regions 212.

[0049] The color filter array 280 includes a plurality of color filters 282 and 283 for spectrally filtering light transmitted through the microlens 292 or 293 aligned therewith. Each color filter 282 is aligned with a corresponding photodiode region 212. Each color filter 283 is aligned with a corresponding photodiode region 213. Herein, a color filter or a microlens is aligned with a photodiode region when a portion of the color filter or the microlens is located directly above the center of the photodiode region.

[0050] Photodiode regions 212 and 213 have respective widths 217 and 218. In an embodiment, width 218 exceeds width 217. In an embodiment, width 217 is between 0.7 microns and 1.0 microns. In an embodiment, at least one of width 218 and pixel pitch 214 is between 0.7 microns and 3.0 microns.

[0051] Buffer layer 250 has a thickness 252 and may be formed of an oxide material. In an embodiment, buffer layer 250 is thinned to thickness 252 via chemical mechanical polishing (CMP). CMP induces mechanical stresses on passivation layer 230, the high-κ layer below it, and top surface 228. As CMP thins buffer layer 250, the magnitude of the induced mechanical stress increases, which can cause dark current and white pixel image artifacts in images captured by camera 190. In an embodiment, thickness 252 exceeds 0.1 microns to provide sufficient thickness for stress relief and prevent such artifacts.

[0052] The cost of requiring thickness 252 to exceed 0.1 microns increases vulnerability to increased optical crosstalk from large photodiode region 213 to adjacent small photodiode region 212. For example, Figure 2Light ray 202 is shown refracted by microlens 293 such that it impinges on the buffer layer at angle of incidence 203. If properly detected, light ray 202 will reach photodiode region 213 beneath microlens 293. However, after being refracted by microlens 293, light ray 202 propagates through color filter 280(1) and reaches photodiode region 212 at position 212L thereof, which results in optical crosstalk.

[0053] Figure 3 2 is a cross-sectional schematic diagram of a pixel array substrate 300 that reduces crosstalk, which is hereinafter referred to as pixel array substrate 300 . Pixel array substrate 300 compensates for optical crosstalk caused by light 202 , etc. Pixel array substrate 300 is an example of pixel array substrate 100 .

[0054] The pixel array substrate 300 includes a semiconductor substrate 210, a buffer layer 350, and a metal ring 370. In a horizontal plane, the metal ring 370 has a hole, and its shape may be a polygon (such as a square, rectangle, or hexagon) or a circle.

[0055] In an embodiment, at least one of the following: (a) buffer layer 350 is formed of an oxide material and (b) metal ring 370 is formed of a metal such as tungsten or aluminum. In an embodiment, pixel array substrate 300 includes an adhesive layer 360 between thick buffer layer region 355 and metal ring 370. Adhesive layer 360 may be formed of titanium nitride. Adhesive layer 360 has a thickness 362, which may be in a vertical direction and / or in a horizontal direction. In an embodiment, thickness 362 is between twenty nanometers and forty nanometers.

[0056] In an embodiment, the bonding layer 360 is formed of at least one of titanium and titanium nitride. The bonding layer 360 may include a titanium layer and a titanium nitride layer so that it functions as both an adhesive and a metal barrier layer. For example, the titanium layer bonds the metal ring 370 to the thick buffer layer region 355. The titanium nitride layer functions as a diffusion barrier layer to prevent metal ions from diffusing from the metal ring 370 into the semiconductor substrate 210.

[0057] The buffer layer 350 is on the back surface 220 and has (i) a thin buffer layer region 351 located above the photodiode regions 212 and 213 and (ii) a thick buffer layer region 355 between adjacent thin buffer layer regions 351 and above the trench 240. The thick buffer layer region 355 forms a ring above the trench 221 in a plane parallel to the cross-sectional plane 4A. The metal ring 370 is on the buffer layer 350 and covers the thick buffer layer region 355. Figure 3 A portion of the metal ring 370(1) and an adjacent metal ring 370(2) are shown. The DTI structure 240 below the metal ring 370(1) is shown as DTI structure 240(1).

[0058] The thin buffer layer region 351 has a thickness 352 that is less than Figure 2 The thickness 352 of the buffer layer 250 of the pixel array substrate 200 is 252. The thickness 352 is thin enough to prevent light from propagating between the metal ring 370 (1) and the DTI structure 240 (1). In an embodiment, the thickness 352 is between twenty nanometers and forty nanometers.

[0059] For example, Figure 3 The illustration shows light ray 302 incident on buffer layer 350 at incident angle 203, which is the same incident angle as light ray 202. In an embodiment, light ray 302 propagates at incident angle 203 after being refracted by a microlens (not shown) directed over large photodiode region 213. Light ray 202 causes Figure 2 The optical crosstalk in the pixel array substrate 200 is reduced. The light 302 has a trajectory that intersects the position 212L of the photodiode region 212 like the light 202. However, since the thickness 352 of the thin buffer layer region 351 is sufficiently small, for example, smaller than the thickness 252 of the buffer layer 250, the metal ring 370 (1) blocks the light 302 and thus prevents the light 302 from reaching the position 212L of the small photodiode region 212 and causing optical crosstalk. In the second example, Figure 3 Light rays 304 and 305 are illustrated. Light ray 305 propagates between metal ring 370(1) and DTI structure 240(1) so that it reaches photodiode region 212. Without metal ring 370(2), light ray 305 is a continuation of light ray 304. However, for light ray 305 to traverse such a path, thickness 352 requires that its propagation angle 306 must be large enough to place metal ring 370(2) between photodiode region 212 and light ray 304 so that light ray 304 is blocked before it can propagate (as light ray 305) to photodiode region 212.

[0060] Thick buffer layer region 355 has a thickness 356 and a width 357. In an embodiment, thickness 356 is between 0.10 microns and 0.16 microns. The lower limit is used to prevent the surface stress mentioned above that causes image artifacts. The upper limit is used to maintain a sufficiently wide angular response, for example as a function of the chief ray angle of a pixel including photodiode region 212. In an embodiment, width 357 is between 0.10 microns and 0.20 microns. The upper limit of width 357 is important to allow buffer layer 350 to be etched to thickness 352 above photodiode region 212.

[0061] Metal ring 370 has a height 372 and a width 374. In an embodiment, height 372 is between 0.1 microns and 0.3 microns, which balances the tradeoff between crosstalk reduction and angular response of a pixel including photodiode region 212. In an embodiment, width 374 is between 0.16 microns and 0.26 microns. The upper limit of width 374 is important to allow etching of buffer layer 350 to a thickness 352 between metal rings above photodiode regions 212, 213.

[0062] The metal ring 370 has an inner sidewall 375, a top surface 376, and an outer sidewall 377. In an embodiment, the pixel array substrate 300 also includes (i) a portion of the thin buffer layer region 351 above the photodiode region 212 and (ii) an attenuation layer 365 on the inner sidewall 375 for attenuating incident light propagating toward the photodiode region 212. The attenuation layer 365 may also cover at least a portion of the top surface 376 and may be formed of one of titanium, titanium nitride, and a combination thereof. In an embodiment, the thickness of the attenuation layer 365 is between twenty nanometers and fifty nanometers. In an embodiment, the attenuation layer 365 is conformal to at least one of the surfaces 375, 376, and the top surface of the thin buffer layer region 351 above the photodiode region 212. In an embodiment, the attenuation layer 365 reduces the photosensitivity of the photodiode region 212, thereby reducing the quantum efficiency of the photodiode region 212.

[0063] Figure 4 4 is a schematic cross-sectional view of a pixel array substrate 400 , which is an example of the pixel array substrate 300 . Figure 4 The cross section of Figure 3 The cross-sectional plane 4A is shown in FIG. Figure 4 represents a cross-sectional plane 3A, which is Figure 3 Pixel array substrate 400 includes a plurality of photodiode regions 412 and a plurality of photodiode regions 413, which are respective examples of photodiode region 212 and a plurality of photodiode regions 213. Although cross-sectional plane 4A does not intersect photodiode regions 412 and 413, Figure 4 Photodiode regions 412 and 413 are illustrated to show their positions relative to metal ring 370 and thick buffer layer region 355. Since pixel array substrate 400 is an example of pixel array substrate 300, pixel array substrate 400 may include attenuation layer 365, Figure 4 Not shown.

[0064] In an embodiment, each photodiode region 412 is located within a quadrilateral region defined by corresponding photodiode regions 413 forming a two-by-two array of photodiode regions 413. In an embodiment, the shape of the quadrilateral region is one of a square, a rectangle, and a parallelogram. For example, photodiode region 412(1) is located within a rectangular region 419(1) defined by corresponding centers of photodiode regions 413(1–4), and photodiode region 412(2) is located within a rectangular region 419(2) defined by corresponding centers of photodiode regions 413(3–6). In an embodiment, photodiode regions 412(1), 412(2) are located at corresponding centers of rectangular regions 419(1) and 419(2).

[0065] In an embodiment, a device transistor region (not shown for simplicity) is defined in a region between adjacent photodiode regions 212 or a region between adjacent photodiode regions 213 on the front surface 211. The device transistor region includes pixel transistors (e.g., source follower, reset transistor, row select) formed on the front surface 211 to control the operation of the corresponding pixel including the photodiode region 212 or 213.

[0066] In an embodiment, each photodiode region 412 is part of a corresponding pixel of a pixel array 416A formed in semiconductor substrate 210, and each photodiode region 413 is part of a corresponding pixel of a pixel array 417A formed in semiconductor substrate 210. Pixel array substrate 400 is an example of pixel array substrate 100, so that in an embodiment, pixel array 112A includes both pixel array 416A and pixel array 417A. Semiconductor substrate 210 is an example of semiconductor substrate 210.

[0067] Figure 5 5 is a schematic cross-sectional view of a metal ring 570 on a buffer layer 350. The metal ring 570 is an example of a metal ring 370 and includes an intermediate segment 576, an inner segment 574, and an outer segment 578. The intermediate segment 576 has an inner sidewall 575, a top surface 571, and an outer sidewall 577. The intermediate segment 576 is on the thick buffer layer region 355 and surrounds the inner segment 574. The inner segment 574 is bonded to both the inner sidewall 575 and the inner sidewall 554 of the thick buffer layer region 355. The outer segment 578 is bonded to both the outer sidewall 577 and the outer sidewall 556 of the thick buffer layer region 355. The inner segment 574 and the outer segment 578 have a thickness 573. In an embodiment, the thickness 573 is between twenty nanometers and forty nanometers.

[0068] In an embodiment, metal ring 570 further includes bonding layer 560, which is an example of bonding layer 360. Bonding layer 560 (i) bonds middle segment 576 to thick buffer region 355, (ii) bonds inner segment 574 to both inner sidewall 575 and inner sidewall 554, and bonds outer segment 578 to at least one of outer sidewall 577 and outer sidewall 556.

[0069] In an embodiment, the metal ring 570 further includes a dielectric annular layer 564 on the top surface 571. The annular layer 564 has an inner surface 563 and an outer surface 566. The inner surface 563 may be covered by a portion of the inner segment 574 bonded thereto. The outer surface 566 may be covered by a portion of the outer segment 578 bonded thereto.

[0070] The buffer layer 350 and the metal ring 570 are part of an embodiment of the pixel array substrate 300. This embodiment may also include an attenuation layer 565 that covers the thin buffer layer region 351 of the buffer layer 350 above the photodiode region 212. In an embodiment, the attenuation layer 565 also covers the inner section 574, as well as portions of the adhesive layer 560 and the annular layer 564. The attenuation layer 565 is Figure 3 Example of attenuation layer 365.

[0071] Figure 6 6 is a cross-sectional schematic diagram of a pixel array substrate 600, which is a pixel array substrate 300 with a color filter array 680 added to a buffer layer 350. The color filter array 680 is similar to the color filter array 280 and includes color filters 682 and 683 that are similar to the color filters 282 and 283, respectively. Each color filter 682 is aligned with a corresponding photodiode region 212. Each color filter 683 is aligned with a corresponding photodiode region 213.

[0072] The top surface 376 of the metal ring 370 is located at a height 672 relative to the top surface 652 of the thin buffer layer region 351. The color filter array 680 has a top surface 689, which is located at a height 686 relative to the top surface 652. The optimal range of height 686 is determined by balancing the tradeoff between filtering undesirable wavelengths and attenuating the desired wavelengths of illumination incident on the photodiode regions 212 and 213. The height 686 exceeds the height 672 by a distance 687, which in an embodiment is between five nanometers and forty nanometers. Each metal ring 370 is embedded in the color filter array 680.

[0073] In an embodiment, the pixel array substrate 600 further includes a microlens array 290, which includes a plurality of microlenses 292 and 293. Each microlens 292 is aligned with a corresponding photodiode region 212 for guiding incident light thereon to the photodiode region 212. Each microlens 293 is aligned with a corresponding photodiode region 213 for guiding incident light thereon to the photodiode region 213.

[0074] Figure 7 – 10 is a corresponding cross-sectional schematic diagram of an intermediate substrate formed in the process of manufacturing the pixel array substrate 300 . Figure 7 is a schematic cross-sectional view of an intermediate substrate 700, which includes a semiconductor substrate 210 on which a passivation layer 230, a buffer layer 750, an adhesive layer 760, a metal layer 770, a hard mask layer 780, and a photoresist layer 790 are disposed. Each trench 221 of the semiconductor substrate 210 is filled with a trench filling material 241. In an embodiment, the thickness of the buffer layer 750 is between 0.10 micrometers and 0.16 micrometers.

[0075] Figure 8 8 is a schematic cross-sectional view of intermediate substrate 800, which is intermediate substrate 700 after removing sections of layers 770, 780, and 790 above photodiode regions 212 and 213, for example, via dry etching. Intermediate substrate 800 includes adhesion layer 860, metal ring 870, mask layer 880, and photoresist layer 890, which are respectively the remaining sections of adhesion layer 760, metal layer 770, mask layer 780, and photoresist layer 790 after a layer removal process such as etching.

[0076] Fig. 9 900 is a schematic cross-sectional view of intermediate substrate 900. Intermediate substrate 900 is intermediate substrate 800 after removing a section of layer 750 above photodiode regions 212 and 213, for example, by etching to thin the section of layer 750 above photodiode regions 212 and 213 to produce buffer layer 950. Buffer layer 950 is Figure 3 The intermediate substrate 800 further includes an adhesive layer 860 , a metal ring 870 , a ring-shaped mask layer 880 , and a photoresist layer 890 .

[0077] Fig.10 1 is a schematic cross-sectional view of an intermediate substrate 1000, which is the intermediate substrate 900 after removing the photoresist layer 890 and then depositing the adhesion layer 1060 and the metal layer 1070 thereon. The metal layer 1070 has a width 1073, which in an embodiment is between Figure 5The thickness 573 of the inner section 574 and the outer section 578 of the metal ring 570 are within the same range.

[0078] Mask layer 880 has a top surface 888 in plane 889 . Fig.10 An inner section 1074 and an outer section 1078 of the metal layer 1070 between the bonding layer 1060 and the plane 889 are shown, as well as a horizontal section 1071 of the metal layer 1070 on the bonding layer 1060 . Fig.10 Also shown are cap segment 1079 of metal layer 1070 and cap segment 1069 of adhesion layer 1060 , each of which is above plane 889 .

[0079] Removal of horizontal segment 1071, the area of ​​cap segment 1079 above ring 870, and the portion of adhesive layer 1060 above plane 889 produces Figure 5 The metal ring 570 of the metal layer 1070 corresponds to the middle section 576; the annular mask layer 880 corresponds to the dielectric annular layer 564. The inner section 1074 and the outer section 1078 of the metal layer 1070 correspond to the inner section 574 and the outer section 578, respectively.

[0080] Fig.11 1 is a flow chart illustrating a method 1100 for manufacturing a pixel array substrate. The method 1100 includes steps 1110, 1120, and 1130. In an embodiment, the method 1100 further includes at least one of steps 1140, 1150, and 1160.

[0081] Step 1110 includes forming a metal ring on a buffer layer disposed on a semiconductor substrate. In an example of step 1110, Figure 8 The metal ring 870 of the intermediate substrate 800 is for example formed by a photolithography process. Figure 7 The intermediate substrate 700 is formed.

[0082] In an embodiment, step 1110 includes at least one of steps 1112, 1114, and 1116. Step 1112 includes depositing a metal layer on the buffer layer. In an example of step 1112, metal layer 770 is deposited on buffer layer 750 or on adhesion layer 760. Figure 7. Step 1114 includes depositing a dielectric layer on the metal layer. In an example of step 1114, at least one of a hard mask layer 780 and a photoresist layer 790 is deposited on the metal layer 770. Step 1116 includes removing sections of the dielectric layer and the metal layer above the first photodiode region formed in the semiconductor substrate to produce a metal ring. In an example of step 1116, sections of layers 760, 770, 780, and 790 above the photodiode region 212 are removed to produce a metal ring 870. In an embodiment, step 1116 also includes removing sections of the dielectric layer and the metal layer above a second photodiode region adjacent to the first photodiode region formed in the semiconductor substrate to produce a metal ring. In another example of step 1116, sections of layers 760, 770, 780, and 790 above the photodiode region 213 are also removed to produce a metal ring aligned with the photodiode region 213.

[0083] Step 1120 includes reducing the thickness of the buffer layer in the region of the buffer layer that is not located under the metal ring to produce a thinned buffer layer located above the first photodiode. In the example of step 1120, the region of the buffer layer 750 that is not located under the metal ring 870 is thinned, for example, via dry etching, to produce Fig. 9 Buffer layer 950.

[0084] Step 1130 includes depositing a conformal metal layer on the thinned buffer layer and metal ring. In the example of step 1130, metal layer 1070 is deposited on metal ring 870 and a portion of buffer layer 950, such as Fig.10 In an embodiment, before depositing the metal layer 1070 , the adhesion layer 1060 is conformally deposited on the metal ring 870 , the mask layer 880 , and the buffer layer 950 to enhance the adhesion of the conformal metal layer to the metal ring 870 .

[0085] Step 1140 includes removing at least a portion of the conformal metal layer over the top surface of the metal ring. In the example of step 1140, cap segment 1069 and cap segment 1079 are removed via etching.

[0086] Step 1150 includes removing a portion of the conformal metal layer located above the photodiode region of the semiconductor substrate. In the example of step 1150, horizontal sections 1071 of the metal layer 1070 (eg, sections 1071 and 1079) located above the photodiode regions 212, 213 are removed to produce Figure 5 The metal ring 570 is formed by removing the metal ring 570. In an embodiment, step 1150 also includes removing a portion of the adhesion layer located above the photodiode region of the semiconductor substrate. Steps 1140 and 1150 can be performed in a single step, such as a single blanket etching step.

[0087] Step 1160 includes depositing an attenuation layer on (i) a portion of the thinned buffer layer located above the photodiode region of the semiconductor substrate and (ii) an inner sidewall of the metal ring. In an example of step 1160, layer 365 is deposited on thin buffer layer region 351 located above the photodiode region 212 and inner sidewall 375 of metal ring 370. In another example of step 1160, attenuation layer 565 is deposited on thin buffer layer region 351 of buffer layer 350 located above the photodiode region 212, inner segment 574, and portions of adhesion layer 560 and portions of annular layer 564.

[0088] Fig.12 is a schematic cross-sectional view of a pixel array substrate 1200 , which is an example of the pixel array substrate 300 . Fig.12 The cross section of Figure 3 12A. The pixel array substrate 1200 includes a metal grid 1270A formed by a plurality of metal rings 1270 and a plurality of interconnection segments 1273 connecting adjacent rings 1270. Examples of metal rings 1270 include metal rings 370 and metal rings 570. In an embodiment, the metal rings 1270 and the interconnection segments 1273 are integrally formed so that the metal grid 1270A is monolithic. In an embodiment, each interconnection segment 1273 extends into a corresponding groove surrounding the large photodiode region 413. For clarity, not all interconnection segments 1273 are in the Fig.12 In the embodiment, the pixel array substrate 1200 includes an attenuation layer 1265, which is an example of the attenuation layer 365, 565. Although the photodiode regions 412 and 413 are not in the cross section 12A, Fig.12 They are shown to illustrate the alignment of metal grid 1270A with photodiode regions 412 and 413 .

[0089] Although in Fig.12 The shapes of the photodiode regions 412 and 413 are illustrated as squares, however, in other embodiments, the shapes of the photodiode regions 412 and 413 can be conformal to the shapes defined by the surrounding deep trench isolation structures and / or the surrounding metal rings 1270 and interconnect segments 1273 (e.g., diamond or polygonal shapes).

[0090] Fig.13 is a schematic cross-sectional view of a pixel array substrate 1300 , which is an example of the pixel array substrate 300 . Fig.13 The cross section of Figure 3The pixel array substrate 1300 includes a plurality of photodiode regions 1312, a plurality of photodiode regions 1313, and a plurality of metal rings 1370. The photodiode regions 1312, the photodiode regions 1313, and the metal rings 1370 are respective examples of the photodiode regions 212, the photodiode regions 213, and the metal rings 370 or 570. In an embodiment, the pixel array substrate 1300 includes additional metal rings 1372, each of the additional metal rings 1372 being aligned above a respective photodiode region 1313 such that the metal rings 1370 and 1372 are interconnected to form a metal grid 1370A. In an embodiment, the pixel array substrate 1300 includes an attenuation layer 1365, which is an example of the attenuation layer 365, which is coated on the metal rings 1370 and covers the exposed areas of the respective photodiode regions 1312. Although the photodiode regions 1312 and 1313 are not in the cross-sectional plane 12A, Fig.13 They are shown to illustrate the alignment of each metal ring 1370 with a corresponding photodiode region 1312 .

[0091] Photodiode region 1312 includes photodiode region 1312 ( k ), where index k is a positive integer. Fig.13 Photodiode regions 1312(1–8) are illustrated. Each photodiode region 1312(k) has three photodiode regions 1313(k) adjacent to it. Two of the three photodiode regions 1313(k) are adjacent to the sides of the photodiode region 1312(k). The remaining photodiode region 1313(k) is adjacent to the corner of the photodiode region 1312(k) and is adjacent to the sides of the other two photodiode regions 1313(k). For each index k, the photodiode region 1312(k) and the three photodiode regions 1313(k) form a two-by-two subarray.

[0092] In an embodiment, each photodiode region 1312(k) and three adjacent photodiode regions 1313(k) are located under a single color filter of the color filter array. For example, when the color filter array is a Bayer array, a green color filter is located above the photodiode regions 1312 and 1313, where the index k is equal to 2, 4, 6, or 8; a red color filter is located above the photodiode regions 1312 and 1313, where the index k is equal to 1, 3, and 7; and a blue color filter is located above the photodiode regions 1312 and 1313, where the index k is equal to 5.

[0093] Combination of features

[0094] The features described above and those claimed below may be combined in various ways without departing from the scope of the present invention. The examples listed below illustrate some possible, non-limiting combinations.

[0095] (A1) A pixel array substrate comprises a semiconductor substrate, a buffer layer and a metal ring. The semiconductor substrate comprises a first photodiode region. A rear surface of the semiconductor substrate forms a groove surrounding the first photodiode region in a cross-sectional plane parallel to a first rear surface region of the rear surface above the first photodiode region. The buffer layer is located on the rear surface and has (i) a thin buffer layer region located above the first photodiode region and (ii) a thick buffer layer region forming a ring above the groove in a plane parallel to the cross-sectional plane. The metal ring is located on the buffer layer and covers the thick buffer layer region.

[0096] (A2) In an embodiment of the pixel array substrate (A1), the metal ring includes (i) a middle segment on the thick buffer layer area, (ii) an inner segment surrounded by the middle segment and bonded to both the inner side wall of the middle segment and the inner side wall of the thick buffer layer area; and (iii) an outer segment bonded to both the outer side wall of the middle segment and the outer side wall of the thick buffer layer area.

[0097] (A3) In an embodiment of the pixel array substrate (A2), a thickness of each of the inner segment and the outer segment is between twenty nanometers and forty nanometers.

[0098] (A4) An embodiment of one of the pixel array substrates (A2) and (A3), further comprising a dielectric annular layer on the top surface of the middle section.

[0099] (A5) In an embodiment of the pixel array substrate (A4), (i) the inner segment includes an inner top region bonded to an inner surface of the dielectric annular layer and (ii) the outer segment includes an outer top region bonded to an outer surface of the dielectric annular layer.

[0100] (A6) In an embodiment of any one of the pixel array substrates (A1)-(A5), a thickness of the thick buffer layer region is between 0.10 micrometers and 0.16 micrometers.

[0101] (A7) In an embodiment of any one of the pixel array substrates (A1)-(A6), a width of the thick buffer layer region is between 0.10 micrometers and 0.25 micrometers.

[0102] (A8) In an embodiment of any one of the pixel array substrates (A1)-(A7), the thickness of the thin buffer layer region is between twenty nanometers and forty nanometers.

[0103] (A9) In any one of the embodiments of the pixel array substrates (A1)-(A8), the buffer layer is formed of an oxide material.

[0104] (A10) An embodiment of any one of the pixel array substrates (A1)-(A9), further comprising an adhesive layer between the metal ring and the thick buffer layer region.

[0105] (A11) In an embodiment of the pixel array substrate (A10), the adhesive layer is formed of titanium nitride.

[0106] (A12) An embodiment of any one of the pixel array substrates (A1)-(A11), further comprising an attenuation layer on at least one of (i) the thin buffer layer region, the inner sidewall of the metal ring, and the top surface of the metal ring. In an embodiment of the pixel array substrate (A12) comprising a dielectric annular layer of the pixel array substrate (A4), the attenuation layer may also be located on the top surface of the dielectric annular layer.

[0107] (A13) In an embodiment of the pixel array substrate (A12), the attenuation layer is formed of one of titanium and titanium nitride.

[0108] (A14) In an embodiment of any one of the pixel array substrates (A1)-(A13), the metal ring is formed of tungsten.

[0109] (A15) In an embodiment of any one of the pixel array substrates (A1)-(A14), the metal ring has a thickness between 0.1 and 0.3 microns.

[0110] (A16) An embodiment of any one of the pixel array substrates (A1)-(A15), further comprising a color filter on the thin buffer layer region. The thickness of the color filter exceeds the thickness of the metal ring. In an embodiment, the color filter thickness exceeds the metal ring thickness by between five nanometers and forty nanometers.

[0111] (A17) In an embodiment of any one of the pixel array substrates (A1)-(A16), the semiconductor substrate further comprises four second photodiode regions forming a two-by-two array. In a cross-sectional plane, the first photodiode region is located within a quadrilateral region defined by respective centers of the four second photodiode regions.

[0112] (A18) In an embodiment of the pixel array substrate (A17), (i) the four second photodiode regions include first, second, third and fourth second photodiode regions, and the semiconductor substrate also includes an additional first photodiode region; (ii) the semiconductor substrate also includes a fifth second photodiode region and a sixth second photodiode region, which form an additional two-by-two array with the third and fourth second photodiode regions; and (iii) in a cross-sectional plane, the additional first photodiode region is located within a quadrilateral region defined by corresponding centers of the third, fourth, fifth and sixth second photodiode regions.

[0113] (A19) In an embodiment of any one of the pixel array substrates (A17) and (A18), a pixel pitch of the two-by-two array is between 0.7 microns and 3.0 microns, a first width of each first photodiode region is between 0.7 microns and 1.0 microns, and a width of each second photodiode region exceeds the first width.

[0114] (A20) In an embodiment of any one of the pixel array substrates (A1)-(A19), the semiconductor substrate further comprises second, third and fourth photodiode regions. The second photodiode region is adjacent to a first side edge of the first photodiode region. The third photodiode region is adjacent to a second side edge of the first photodiode region. The fourth photodiode region is adjacent to a corner of the first photodiode region and adjacent to each side edge of the second and third photodiode regions.

[0115] (B1) A method for manufacturing a pixel array substrate, comprising (i) forming a metal ring on a buffer layer disposed on a semiconductor substrate; (ii) reducing the thickness of a buffer layer region that is not located below the metal ring to produce a thinned buffer layer; and (iii) depositing a conformal metal layer on the thinned buffer layer and the metal ring.

[0116] (B2) An embodiment of method (B1) further comprising the steps of: (i) removing at least a portion of the conformal metal layer located above the top surface of the metal ring, and (ii) removing a portion of the conformal metal layer located above the photodiode region of the semiconductor substrate.

[0117] (B3) An embodiment of one of methods (B1) and (B2), further comprising depositing an attenuation layer on (i) a portion of the thinned buffer layer above the photodiode region of the semiconductor substrate and (ii) an inner sidewall of the metal ring.

[0118] Changes may be made in the above methods and systems without departing from the scope of the present embodiments. It should therefore be noted that the content contained in the above description or shown in the accompanying drawings should be interpreted as illustrative, not restrictive. In this document, and unless otherwise indicated, the phrase "in an embodiment" is equivalent to the phrase "in certain embodiments" and does not refer to all embodiments. The following claims are intended to cover all general and specific features described herein, as well as all statements of the scope of the present methods and systems, which, as far as language is concerned, can be considered to be between the two.

Claims

1. A pixel array substrate for reducing crosstalk, comprising: a semiconductor substrate including a first photodiode region, a rear surface of the semiconductor substrate forming a groove surrounding the first photodiode region in a cross-sectional plane parallel to a first rear surface region of the rear surface above the first photodiode region; a buffer layer on the rear surface and having (i) a thin buffer layer region over the first photodiode region and (ii) a thick buffer layer region that (a) is thicker than the thin buffer layer region and (b) forms a ring over the trench in a plane parallel to the cross-sectional plane; a metal ring, the metal ring being on the buffer layer and covering the thick buffer layer region; as well as A damping layer is provided on the thin buffer layer region and the inner side wall of the metal ring.

2. The pixel array substrate according to claim 1, wherein the metal ring comprises: an intermediate section above the thick buffer layer region; an inner section surrounded by the middle section and bonded to both the inner sidewall of the middle section and the inner sidewall of the thick buffer layer region; as well as An outer section bonded to both the outer sidewall of the intermediate section and the outer sidewall of the thick buffer region. 3 . The pixel array substrate of claim 2 , wherein a thickness of each of the inner segment and the outer segment in a direction parallel to the first rear surface area is between twenty nanometers and forty nanometers. 4 . The pixel array substrate of claim 2 , further comprising a dielectric annular layer on a top surface of the middle section.

5. The pixel array substrate according to claim 4, wherein The inner section includes an inner top region bonded to an inner surface of the dielectric annular layer; and The outer segment includes an outer top region bonded to an outer surface of the dielectric annular layer. 6 . The pixel array substrate of claim 4 , wherein the attenuation layer is further located on the thin buffer layer region, the inner sidewall of the metal ring, the top surface of the metal ring, and the top surface of the dielectric annular layer. 7 . The pixel array substrate of claim 1 , wherein the thickness of the thick buffer layer region is between 0.10 micrometers and 0.16 micrometers. 8 . The pixel array substrate of claim 1 , wherein a width of the thick buffer layer region is between 0.10 micrometers and 0.25 micrometers. 9 . The pixel array substrate of claim 1 , wherein the thickness of the thin buffer layer region is between twenty nanometers and forty nanometers. 10 . The pixel array substrate of claim 1 , further comprising an adhesive layer between the metal ring and the thick buffer layer region. 11 . The pixel array substrate of claim 1 , wherein the attenuation layer is formed of one of titanium and titanium nitride. 12 . The pixel array substrate of claim 1 , wherein the metal ring has a thickness between 0.1 and 0.3 microns.

13. The pixel array substrate of claim 1 , further comprising a color filter on the thin buffer layer region and having a thickness exceeding a thickness of the metal ring, the metal ring being located between the buffer layer and a portion of the color filter in a direction perpendicular to the first rear surface region.

14. The pixel array substrate according to claim 13, further comprising: a microlens on the color filter, The metal ring is between the buffer layer and a portion of the microlens along a direction perpendicular to the first rear surface area.

15. The pixel array substrate according to claim 1, wherein The semiconductor substrate further includes four second photodiode regions forming a two-by-two array; and In the cross-sectional plane, the first photodiode region is located within a quadrilateral region defined by respective centers of the four second photodiode regions.

16. The pixel array substrate according to claim 1, wherein The semiconductor substrate also includes a second photodiode region adjacent to a first side edge of the first photodiode region, a third photodiode region adjacent to a second side edge of the first photodiode region, and a fourth photodiode region adjacent to a corner of the first photodiode region and adjacent to each side edge of the second photodiode region and the third photodiode region.

17. A method for manufacturing a pixel array substrate, comprising: forming a metal ring on a buffer layer disposed on a semiconductor substrate; reducing the thickness of the buffer layer in regions of the buffer layer that are not located below the metal ring to produce a thinned buffer layer; depositing a conformal metal layer on the thinned buffer layer and the metal ring; as well as An attenuation layer is formed on (i) a portion of the thinned buffer layer over a photodiode region of the semiconductor substrate and (ii) a portion of the metal ring.

18. The method of claim 17, further comprising: removing at least a portion of the conformal metal layer above a top surface of the metal ring; as well as A portion of the conformal metal layer located above a photodiode region of the semiconductor substrate is removed.

19. The method of claim 17, wherein the step of forming an attenuation layer further comprises depositing the attenuation layer on (i) a portion of the thinned buffer layer above the photodiode region of the semiconductor substrate and (ii) an inner sidewall of the metal ring.

Images