Semiconductor device and method of manufacturing semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device and a preparation method thereof, and relate to the technical field of microelectronics, the semiconductor device comprising a substrate, a semiconductor epitaxial layer, a metal electrode, a source field plate and a metal interconnection layer, the semiconductor epitaxial layer being located on one side of the substrate, the metal electrode comprising a source electrode, a gate electrode and a drain electrode, and the source electrode, the gate electrode and the drain electrode all being located on a side of the semiconductor epitaxial layer away from the substrate, the source field plate being located on a side of the gate electrode away from the substrate and being arranged in a spaced manner with the gate electrode, wherein a dielectric space is formed between the gate electrode and the source field plate, and the source field plate and the metal interconnection layer are integrally arranged. The present application enables the metal interconnection layer and the source field plate to be integrally formed, compared with the existing split structure, so that the device structure is simpler, the process steps are simplified, the production cost is saved, and the production efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and more specifically, to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0002] Gallium nitride (GaN), a semiconductor material, has become a research hotspot due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In electronic devices, GaN is more suitable than silicon and gallium arsenide for manufacturing high-temperature, high-frequency, high-voltage, and high-power devices, thus GaN-based electronic devices have excellent application prospects.

[0003] HEMT (High Electron Mobility Transistor) devices operating at high drain-source voltages experience a high electric field spike near the drain side of the gate. This localized high electric field can induce very large gate leakage currents, even leading to material breakdown and device failure. This, in turn, affects device reliability, reduces device lifespan, and prevents HEMT devices from fully utilizing their advantages of high temperature, high voltage, and high frequency. Therefore, in the structural design and process development of practical devices, various methods are always employed to reduce the strong electric field near the device gate in order to improve the device's breakdown voltage and achieve excellent reliability.

[0004] The currently widely used method employs a field plate structure, where a field plate is placed on the gate side near the drain. This field plate is typically connected to the source or gate, generating an additional potential in the gate-drain region. This increases the area of ​​the depletion region, improves its breakdown voltage, and modulates the dense electric field lines near the drain edge of the gate, resulting in a more uniform electric field distribution, reducing the electric field near the drain edge, decreasing gate leakage current, and improving the device breakdown voltage. Existing field plate structures are usually separate, with the field plate structure and the interconnect metal on the source placed sequentially and made of different materials. This design affects the efficiency of the field plate fabrication process, and the process steps and structure are complex, leading to high production costs. Summary of the Invention

[0005] The objectives of this invention include, for example, providing a semiconductor device and a method for fabricating a semiconductor device, which simplifies the structure, streamlines the process steps, saves production costs, and improves production efficiency.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] In a first aspect, the present invention provides a semiconductor device, comprising:

[0008] Substrate;

[0009] A semiconductor epitaxial layer located on one side of the substrate;

[0010] The source, gate, and drain electrodes are located on the side of the semiconductor epitaxial layer away from the substrate;

[0011] A source field plate located on the side of the gate away from the substrate and spaced apart from the gate;

[0012] And a metal interconnect layer located on the side of the source electrode away from the substrate and connected to the source electrode;

[0013] A dielectric space is formed between the gate and the source field plate, and the source field plate and the metal interconnect layer are integrally disposed.

[0014] In an optional embodiment, the semiconductor device further includes a dielectric layer, which is at least partially located in the dielectric space.

[0015] In an optional embodiment, the dielectric layer is located on the side of the semiconductor epitaxial layer away from the substrate and covers the gate and the drain, with the source field plate located on the dielectric layer.

[0016] In an optional embodiment, an isolation structure is provided on the metal interconnect layer, the isolation structure dividing the metal interconnect layer into at least two metal conductive blocks, at least one of the metal conductive blocks being integrally disposed with the source field plate.

[0017] In an optional embodiment, the isolation structure includes at least two separating lines that intersect and divide the metal interconnect layer into at least two metal conductive blocks, and at least one of the separating lines is connected to the dielectric layer.

[0018] In an optional implementation, each of the dividing lines extends to the edge of the metal interconnect layer.

[0019] In an optional embodiment, a plurality of connecting metal bridges are integrally disposed between the source field plate and the metal interconnect layer, and at least one of the separating lines is disposed between adjacent connecting metal bridges.

[0020] In an optional embodiment, the isolation structure is hollow or filled with a medium material.

[0021] In an optional implementation, the distance between any two adjacent metal conductive blocks is greater than or equal to 2 micrometers.

[0022] In an optional embodiment, the projected area S1 of the metal interconnect layer on the substrate is 0.4-1.6 times the projected area S2 of the source electrode on the substrate.

[0023] In a second aspect, the present invention provides a method for fabricating a semiconductor device, comprising:

[0024] A semiconductor epitaxial layer is prepared on one side of the substrate;

[0025] A source, gate, and drain are fabricated on the side of the semiconductor epitaxial layer away from the substrate;

[0026] A metal interconnect layer is fabricated on the side of the source electrode that is away from the substrate, and a source field plate is fabricated on the side of the gate electrode that is away from the substrate.

[0027] The source field plate and the gate are spaced apart to form a dielectric space, and the source field plate and the metal interconnect layer are integrally formed.

[0028] In an optional embodiment, prior to the steps of fabricating a metal interconnect layer on the side of the source electrode away from the substrate and fabricating a source field plate on the side of the gate electrode away from the substrate, the method further includes:

[0029] A dielectric layer is formed on the side of the semiconductor epitaxial layer away from the substrate, and the dielectric layer covers the gate and the drain.

[0030] In an optional embodiment, the steps of fabricating a metal interconnect layer on the side of the source electrode away from the substrate and fabricating a source field plate on the side of the gate electrode away from the substrate include:

[0031] A photoresist layer is coated on the side of the source electrode away from the substrate and the side of the dielectric layer away from the substrate, and the shapes of the source field plate and the metal interconnect layer are developed.

[0032] Metal deposition is performed on the side of the photoresist layer away from the substrate;

[0033] Excess metal deposits are stripped off, and the source field plate and the metal interconnect layer are formed.

[0034] The beneficial effects of the embodiments of the present invention include:

[0035] The semiconductor device and its fabrication method provided in this invention form a semiconductor epitaxial layer on a substrate, and a metal electrode on the semiconductor epitaxial layer. A metal interconnect layer and a source field plate are formed above the metal electrode. The metal interconnect layer and the source field plate are integrally disposed, so that the metal interconnect layer and the source field plate can be formed simultaneously. Compared with the existing separate structure, the device structure is simpler, the process steps are simplified, production costs are saved, and production efficiency is improved. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the semiconductor device provided in the first embodiment of the present invention from a first perspective;

[0038] Figure 2 This is a schematic diagram of the semiconductor device provided in the first embodiment of the present invention from a second perspective;

[0039] Figure 3 A schematic diagram of the parallel structure of a semiconductor device provided in the second embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in the third embodiment of the present invention;

[0041] Figure 5 This is a flowchart illustrating the steps of a method for fabricating a semiconductor device according to the fourth embodiment of the present invention.

[0042] Icons: 100 - Semiconductor device; 110 - Substrate; 130 - Semiconductor epitaxial layer; 131 - Nucleation layer; 133 - Buffer layer; 135 - Channel layer; 137 - Barrier layer; 150a - Source; 150b - Gate; 150c - Drain; 170 - Source field plate; 180 - Metal interconnect layer; 181 - Isolation structure; 183 - Metal conductive block; 185 - Separator line; 187 - Connecting metal bridge; 190 - Dielectric layer. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0045] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0046] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0047] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0048] As disclosed in the background section, existing technologies typically use field plate structures to regulate the electric field, resulting in a more uniform distribution of electric field lines, reducing the electric field near the drain edge of the gate, decreasing gate leakage current, and improving device breakdown voltage. However, conventional field plate structures usually require interconnect metal to achieve electrical connection with the source. This interconnect metal refers to a conductive metal layer deposited above the source, which is typically separate from the source field plate. That is, the interconnect metal layer above the source and the source field plate are formed sequentially, and to achieve better adhesion, the interconnect metal layer and the source field plate generally use different materials. This design and process undoubtedly leads to low field plate manufacturing efficiency, complex process steps and structures, increased manufacturing difficulty, and higher production costs.

[0049] Furthermore, conventional interconnect metal layers are deposited as a whole, and a stripping process is required after the interconnect metal layer and source field plate are formed. Excess metal connecting the interconnect metal layer and the source field plate, as well as the surrounding area of ​​the interconnect metal layer and the external passive region, needs to be stripped after forming. The stripping process is very troublesome and can easily damage the structure of the source field plate and the interconnect metal layer, which greatly increases the difficulty of device fabrication and further reduces the fabrication efficiency.

[0050] To address the aforementioned problems, embodiments of the present invention provide a method for the machine fabrication of a semiconductor device 100. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0051] First Embodiment

[0052] See Figure 1 and Figure 2This embodiment provides a semiconductor device 100, which has a simple structure, simplifies the process steps, reduces the process difficulty, saves production costs, improves production efficiency, and makes the metal stripping process simpler, safer and more reliable.

[0053] The semiconductor device 100 provided in this embodiment includes a substrate 110, a semiconductor epitaxial layer 130, a metal electrode, a source field plate 170, and a metal interconnect layer 180. The semiconductor epitaxial layer 130 is located on one side of the substrate 110. The metal electrode includes a source 150a, a gate 150b, and a drain 150c. The source 150a, gate 150b, and drain 150c are all located on the side of the semiconductor epitaxial layer 130 away from the substrate 110. The source field plate 170 is located on the side of the gate 150b away from the substrate 110 and is spaced apart from the gate 150b. A dielectric space is formed between the gate 150b and the source field plate 170. The source field plate 170 and the metal interconnect layer 180 are integrally disposed.

[0054] In this embodiment, the metal interconnect layer 180 and the source field plate 170 are integrally formed during fabrication. Specifically, the metal interconnect layer 180 and the source field plate 170 are deposited and formed simultaneously, thereby enabling the metal interconnect layer 180 and the source field plate 170 to be integrated, simplifying the structure. Furthermore, the metal interconnect layer 180 and the source field plate 170 use the same conductive material, ensuring stable and reliable electrical connection performance. Simultaneously, the simultaneous fabrication of the metal interconnect layer 180 and the source field plate 170 simplifies the process steps. Compared to conventional separate fabrication methods using different materials, this reduces process difficulty, saves production costs, and improves production efficiency.

[0055] In this embodiment, an isolation structure 181 is also provided on the metal interconnect layer 180. The isolation structure 181 divides the metal interconnect layer 180 into at least two metal conductive blocks 183, and at least one metal conductive block 183 is integrally disposed with the source field plate 170. Specifically, for parallel devices, multiple metal conductive blocks 183 are connected to the source field plate 170 on adjacent devices, so that each metal conductive block 183 can be connected to the source field plate 170. This embodiment uses one device as an example for explanation.

[0056] It should be noted that in this embodiment, the isolation structure 181 is used to divide the metal interconnect layer 180 into at least two metal conductive blocks 183. The metal interconnect layer 180 is connected to the source field plate 170 and integrally formed. By setting the isolation structure 181, during the deposition and formation of the metal interconnect layer 180 and the source field plate 170, excess metal between the metal interconnect layer 180 and the source field plate 170 and connected to the external passive area, as well as excess metal around the metal interconnect layer 180, can all be connected to the metal deposits corresponding to the isolation structure 181. This results in a larger area of ​​the metal deposits to be peeled off, making the peeling off of excess metal easier and safer, without damaging the structure of the source field plate 170 and the metal interconnect layer 180. This further reduces the manufacturing difficulty of the metal interconnect layer 180 and the source field plate 170 and improves manufacturing efficiency.

[0057] In this embodiment, the substrate 110 serves to support the semiconductor epitaxial layer 130. The deposition method of the substrate 110 is not specifically limited and can be CVD (Chemical Vapor Deposition), VPE (Vapour Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, etc. Simultaneously, the substrate 110 can be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, or any other material known to those skilled in the art capable of growing group III nitrides. In this embodiment, the substrate 110 is made of sapphire.

[0058] In this embodiment, a semiconductor layer is formed on the upper surface of the substrate 110. The semiconductor layer includes a nucleation layer 131 on the upper surface of the substrate 110, a buffer layer 133 on the side of the nucleation layer 131 away from the substrate 110, a channel layer 135 on the side of the buffer layer 133 away from the substrate 110, and a barrier layer 137 on the side of the channel layer 135 away from the substrate 110. The barrier layer 137 and the channel layer 135 form a heterojunction. The buffer layer 133 serves to bond the other semiconductor epitaxial layers 130 that will be grown subsequently, specifically bonding the substrate 110 and the channel layer 135, and also protecting the substrate 110 from the intrusion of some metal ions. The buffer layer 133 is AlGaN with controllable aluminum content. The channel layer 135 is deposited and grown on the buffer layer 133, and the channel layer 135 is used to provide a channel for the movement of two-dimensional electron gas (2DEG). The channel layer 135 can be one or more of GaN, AlGaN, InAlN, or AlN, whether undoped, n-type doped, or partially n-type doped. A barrier layer 137 is deposited on the buffer layer 133, and its deposition material can be any semiconductor material capable of forming a heterojunction structure with the channel layer 135, including gallium-based compound semiconductor materials or group III nitride semiconductor materials, such as InAlGaN. Specifically, in this embodiment, AlGaN is used, with a controllable Al content of 0 < Al% < 1. The AlGaN barrier layer 137 and the underlying channel layer 135 together form a heterojunction structure, and a two-dimensional electron gas (2DEG) is formed near the channel layer 135 at the heterojunction interface.

[0059] It should be noted that the semiconductor device 100 mentioned in this embodiment includes, but is not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current environments, silicon-on-insulator (SOI) transistors on insulating substrates 110, gallium arsenide (GaAs) based transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), and metal-semiconductor field-effect transistors (MFETs). Transistor (MESFET), Metal-Semiconductor Heterojunction Field-Effect Transistor (MISHFET), or other field-effect transistors.

[0060] In this embodiment, both the source 150a and drain 150c are located on the barrier layer 137 and are electrically connected to the two-dimensional electron gas (2DEG) formed at the interface between the channel layer 135 and the barrier layer 137. The gate 150b is located between the source 150a and drain 150c and is located on the barrier layer 137. When fabricating the gate 150b, a passivation layer can also be formed on the barrier layer 137, and a T-shaped gate is formed by depositing metal through a gate trench on the passivation layer. The gate 150b is spaced apart from and corresponds to the source field plate 170. There is a dielectric space between the gate 150b and the source field plate 170. This dielectric space can be filled with dielectric material or air, thereby enabling the source field plate 170 to regulate the electric field. Specifically, the isolation structure 181 in this embodiment extends into this dielectric space, thereby enabling the dielectric space between the gate 150b and the source field plate 170 to be connected to the external passive region through the isolation structure 181.

[0061] In this embodiment, the metal interconnect layer 180 is deposited on the surface of the source 150a away from the substrate 110, and the shape of the isolation structure 181 is formed by depositing metal after developing a mask, such that the isolation structure 181 penetrates the metal interconnect layer 180 in the deposition thickness direction, and in the horizontal direction, the isolation structure 181 extends to the edge of the metal interconnect layer 180.

[0062] Specifically, the isolation structure 181 includes at least two dividing line portions 185, which intersect and divide the metal interconnect layer 180 into at least two metal conductive blocks 183. At least one dividing line portion 185 extends into the dielectric space. Specifically, the intersection of multiple dividing line portions 185 allows the isolation structure 181 to present a T-shape, a cross shape, or a star shape. When there are two dividing line portions 185, and one dividing line portion 185 intersects the middle of another dividing line portion 185, the two dividing line portions 185 form a T-shaped structure. When there are two or more dividing line portions 185, and the multiple dividing line portions 185 are compared to their midpoints, a cross-shaped structure or a star-shaped structure is formed. Preferably, in this embodiment, two dividing line portions 185 intersect to form a cross-shaped structure, dividing the metal interconnect layer 180 into four metal conductive blocks 183. The four metal conductive blocks 183 are respectively connected to two source field plates 170. Of course, the multiple dividing lines 185 here can also divide the metal interconnect layer 180 into a cross-shaped structure, a star-shaped structure or a T-shaped structure. For example, when the metal interconnect layer 180 is long enough, the multiple dividing lines 185 can divide it into several cross-shaped structures and form multiple metal conductive blocks 183.

[0063] In this embodiment, each separator line portion 185 extends to the edge of the metal interconnect layer 180. Specifically, at least one end of each separator line portion 185 extends to the boundary of the metal interconnect layer 180, thereby enabling each separator line portion 185 to penetrate the metal interconnect layer 180 on at least one side, thus separating the metal interconnect layer 180. Simultaneously, at least one separator line portion 185 extends into the dielectric space, allowing the dielectric space to be connected to an external passive region through the plurality of separator line portions 185.

[0064] In this embodiment, a plurality of connecting metal bridges 187 are integrally formed between the source field plate 170 and the metal interconnect layer 180, and at least one separating line portion 185 is provided between adjacent connecting metal bridges 187. Specifically, at least one connecting metal bridge 187 is provided between each metal conductive block 183 and the corresponding source field plate 170, so that each connecting metal bridge 187 can be connected to each independent metal conductive block 183, and the number of connecting metal bridges 187 is less than or equal to the number of metal conductive blocks 183. The plurality of connecting metal bridges 187, the metal interconnect layer 180 and the source field plate 170 are integrally formed to achieve a good electrical connection effect.

[0065] In this embodiment, the isolation structure 181 is either hollow or filled with a dielectric material. When the multiple separator lines 185 are filled with air, that is, when the multiple separator lines 185 are all hollow. Preferably, each separator line 185 is filled with a dielectric material, wherein the dielectric material refers to a dielectric material, such as SiN or resin. By filling with a dielectric material, the structure of the metal interconnect layer 180 can be made more stable, and the device performance can be more reliable.

[0066] It should be noted that in this embodiment, the metal interconnect layer 180, the source field plate 170, and the connecting metal bridge 187 are formed by metal deposition. The metal interconnect layer 180 is formed on the source electrode 150a, and the source field plate 170 is formed above the gate electrode 150b. Specifically, after coating the surface of the source electrode 150a with a photoresist layer, the shape of the metal interconnect layer 180 is developed using the isolation structure 181 as a mask, and then metal deposition is performed. Finally, the excess metal is peeled off. During the peeling process, due to the presence of the isolation structure 181, the surrounding excess metal deposits can connect with the metal deposits corresponding to the isolation structure 181, and the metal deposits corresponding to the isolation structure 181 are in a raised state, making the peeling of excess metal easier and safer, without damaging the metal interconnect layer 180. The source field plate 170 can also be formed simultaneously here. The source field plate 170 and the metal interconnect layer 180 are integrally formed, and the isolation structure 181 makes the peeling process of the source field plate 170 easier and safer. In order to form the source field plate 170, a support layer can be provided on the side of the gate 150b away from the substrate 110, and metal can be deposited on the support layer to form the source field plate 170. Finally, the support layer can be partially or completely removed. When the support layer is made of dielectric material, it can also be retained to form the dielectric layer 190.

[0067] In this embodiment, the distance between any two adjacent metal conductive blocks 183 is greater than or equal to 2 micrometers. Specifically, the width of each separator line portion 185 is greater than or equal to 2 micrometers, and the width of the separator line portion 185 is less than the width of the metal interconnect layer 180. Preferably, the width of each separator line portion 185 is the same, that is, the distance between any two adjacent metal conductive blocks 183 is equal everywhere, thereby improving the stability of the device.

[0068] In this embodiment, the projected area S1 of the metal interconnect layer 180 on the substrate 110 is 0.4-1.6 times the projected area S2 of the source electrode 150a on the substrate 110. Specifically, in this embodiment, the metal interconnect layer 180 covers the source electrode 150a. In this embodiment, the surface of the substrate 110 is used as the projection surface. Of course, the surface of the semiconductor epitaxial layer 130 can also be used as the projection screen, as long as the projection direction is in the deposition thickness direction. The projected area S1 of the metal interconnect layer 180 is not much different from the projected area S2 of the source electrode 150a, which makes the fabrication process simpler and the structure more stable. The area difference between S1 and S2 is less than or equal to 3 / 5 of S2. Of course, the projected area of ​​the metal interconnect layer 180 here includes the projected area of ​​the metal conductive block 183 and the projected area of ​​the isolation structure 181. When the projected area of ​​the metal interconnect layer 180 above the source 150a is greater than the projected area of ​​the source 150a, after the metal interconnect layer 180 above the source 150a strips off the excess metal and forms the isolation structure 181, the projected area of ​​the remaining multiple metal conductive blocks 183 may be greater than or less than the projected area of ​​the source 150a, and no specific limitation is made here.

[0069] In summary, this embodiment provides a semiconductor device 100, which forms a metal interconnect layer 180 and a source field plate 170 above a metal electrode. The metal interconnect layer 180 and the source field plate 170 are integrally formed, allowing for a simpler device structure compared to existing separate structures. This simplifies the manufacturing process, reduces production costs, and improves production efficiency. Furthermore, by providing an isolation structure 181 on the metal interconnect layer 180, which divides the metal interconnect layer 180 into multiple conductive metal blocks 183, excess metal can connect with the corresponding metal deposits at the isolation structure 181 during the deposition of the metal interconnect layer 180 and the source field plate 170. This results in a larger area of ​​the metal deposits to be removed, making the removal of excess metal easier and safer, without damaging the source field plate 170 and the metal interconnect layer 180. This reduces the fabrication difficulty of the metal interconnect layer 180 and the source field plate 170 and improves manufacturing efficiency.

[0070] Second Embodiment

[0071] See Figure 3 This embodiment provides a semiconductor device 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0072] In this embodiment, the semiconductor devices 100 are arranged in parallel, and two semiconductor devices 100 are used as an example for illustration. Specifically, each semiconductor device 100 includes a substrate 110, a semiconductor epitaxial layer 130, a metal electrode, a source field plate 170, and a metal interconnect layer 180. The semiconductor epitaxial layer 130 is located on one side of the substrate 110. The metal electrode includes a source 150a, a gate 150b, and a drain 150c, and the source 150a, gate 150b, and drain 150c are all located on the side of the semiconductor epitaxial layer 130 away from the substrate 110. The source field plate 170 is located on the side of the gate 150b away from the substrate 110 and is spaced apart from the gate 150b. A dielectric space is formed between the gate 150b and the source field plate 170. The source field plate 170 and the metal interconnect layer 180 are integrally formed.

[0073] In this embodiment, multiple metal conductive blocks 183 are respectively connected to source field plates 170 on adjacent devices, so that each metal conductive block 183 can be connected to the source field plate 170. Specifically, each metal conductive block 183 is provided with a connecting metal bridge 187, which enables the connection between the metal conductive block 183 and the corresponding source field plate 170.

[0074] Third Embodiment

[0075] See Figure 4 This embodiment provides another semiconductor device 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0076] The semiconductor device 100 provided in this embodiment includes a substrate 110, a semiconductor epitaxial layer 130, metal electrodes, a source field plate 170, a metal interconnect layer 180, and a dielectric layer 190. The semiconductor epitaxial layer 130 is located on one side of the substrate 110. The metal electrodes include a source 150a, a gate 150b, and a drain 150c, and the source 150a, gate 150b, and drain 150c are all located on the side of the semiconductor epitaxial layer 130 away from the substrate 110. The source field plate 170 is located on the side of the gate 150b away from the substrate 110 and is spaced apart from the gate 150b. A dielectric space is formed between the gate 150b and the source field plate 170. The source field plate 170 and the metal interconnect layer 180 are integrally disposed. The dielectric layer 190 is located on the side of the semiconductor epitaxial layer 130 away from the substrate 110 and is at least partially located in the dielectric space.

[0077] In this embodiment, the gate 150b is located between the source 150a and the drain 150c. A dielectric layer 190 is grown on the semiconductor epitaxial layer 130 and covers the gate 150b and drain 150c. A source field plate 170 is located on the dielectric layer 190. Specifically, the dielectric layer 190 fills the dielectric space between the gate 150b and the source field plate 170. A trench is also formed on the dielectric layer 190 to accommodate the source field plate 170. The source field plate 170 is located on the side of the dielectric layer 190 away from the substrate 110 and extends into the trench. By providing the dielectric layer 190, the source field plate 170 can be better supported and the dielectric space can be filled, enabling the source field plate 170 to regulate the electric field. The dielectric layer 190 can be a crystalline material deposited during growth or processing, such as GaN or AlN, or an amorphous material deposited during growth or processing, such as SiN.

[0078] In other preferred embodiments of the present invention, the dielectric layer 190 may only cover the gate 150b and be self-aligned with the gate 150b, with the remaining dielectric space being air, which can also ensure the electric field regulation effect of the source field plate 170.

[0079] In this embodiment, an isolation structure 181 is provided on the metal interconnect layer 180. The isolation structure 181 divides the metal interconnect layer 180 into at least two metal conductive blocks 183, and at least one metal conductive block 183 is integrally disposed with the source field plate 170. The isolation structure 181 includes at least two dividing line portions 185, which intersect and divide the metal interconnect layer 180 into at least three metal conductive blocks 183. At least one dividing line portion 185 is connected to the dielectric layer 190, thereby connecting the isolation structure 181 to the dielectric layer 190 and to the external passive region. This allows the dielectric layer 190 between the gate 150b and the source 150a to be connected to the passive region through the isolation structure 181.

[0080] It should be noted that in this embodiment, the metal interconnect layer 180, the source field plate 170, and the connecting metal bridge 187 are formed by metal deposition. The metal interconnect layer 180 is formed on the source 150a, and the source field plate 170 is formed on the dielectric layer 190 and located above the gate 150b. Specifically, after forming the dielectric layer 190 (the dielectric layer 190 covers the gate 150b and drain 150c, and the dielectric layer 190 above the source 150a needs to be removed), a photoresist layer is coated on the surface of the source 150a and the surface of the dielectric layer 190. The shape of the metal interconnect layer 180 is developed on the photoresist layer above the source 150a using the isolation structure 181 as a mask. At the same time, the shape of the source field plate 170 is developed on the photoresist layer on the dielectric layer 190. Then, metal deposition is performed, and finally, the excess metal is stripped off. During the stripping process, due to the presence of the isolation structure 181, the excess metal deposits can be connected with the metal deposits corresponding to the isolation structure 181, making the stripping of excess metal easier and safer, without damaging the metal interconnect layer 180.

[0081] The semiconductor device 100 provided in this embodiment can better support and form the source field plate 170 by additionally setting a dielectric layer 190, and can fill the dielectric space, so that the source field plate 170 can achieve the function of regulating the electric field.

[0082] Fourth embodiment

[0083] See Figure 5 This embodiment provides a method for fabricating a semiconductor device 100, used to fabricate the semiconductor device 100 as provided in the first or second embodiment. The method for fabricating the semiconductor device 100 includes the following steps:

[0084] S1: A semiconductor epitaxial layer 130 is prepared on one side of the substrate 110.

[0085] Specifically, a substrate 110 is first provided, and a semiconductor epitaxial layer 130 is deposited on the substrate 110. The semiconductor epitaxial layer 130 includes a nucleation layer 131, a buffer layer 133, a channel layer 135, and a barrier layer 137 sequentially formed on the surface of the substrate 110. The substrate 110 serves to support the semiconductor layer, and its deposition method can include CVD (Chemical Vapor Deposition), VPE (Vapour Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, etc. A semiconductor epitaxial layer 130 is deposited on the surface of the substrate 110, and its preparation method can be MOCVD, MBE, atomic layer epitaxy, etc.

[0086] In this embodiment, the substrate 110 can be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, or any other material capable of growing group III nitrides. The nucleation layer 131 varies depending on the substrate 110 material. Specifically, the nucleation layer 131 is grown on the substrate 110 and is used to influence parameters such as crystal quality, surface morphology, and electrical properties of the heterojunction structure, thereby matching the substrate 110 material with the semiconductor material layer in the heterojunction structure. The material used to prepare the nucleation layer 131 can include at least one of GaN, AlN, AlGaN, or other semiconductor materials. The buffer layer 133 serves to bond the subsequent semiconductor layers, specifically the nucleation layer 131 and the channel layer 135, and also protects the substrate 110 and the nucleation layer 131 from the intrusion of metal ions. The buffer layer 133 can be at least one of AlN, InAlN, AlGaN, InAlGaN, or other semiconductor materials. Preferably, the buffer layer 133 is AlGaN with controllable aluminum content. The channel layer 135 is deposited on the buffer layer 133 and provides a channel for the movement of two-dimensional electron gas (2DEG). The channel layer 135 can be one or more of GaN, AlGaN, InAlN, or AlN, whether undoped, n-type doped, or partially n-type doped. The barrier layer 137 is deposited on the buffer layer 133, and its deposition material can be any semiconductor material capable of forming a heterojunction with the channel layer 135, including gallium compound semiconductor materials or group III nitride semiconductor materials, such as InAlGaN. Specifically, in this embodiment, AlGaN is used, and the Al content is controllable, with 0 < Al% < 1. The AlGaN barrier layer 137 and the underlying channel layer 135 together form a heterojunction structure, and a two-dimensional electron gas (2DEG) is formed near the channel layer 135 at the heterojunction interface.

[0087] S2: A source 150a, a gate 150b, and a drain 150c are fabricated on the side of the semiconductor epitaxial layer 130 away from the substrate 110;

[0088] Specifically, the source 150a and drain 150c are both located on the barrier layer 137 and are electrically connected to the two-dimensional electron gas (2DEG) formed at the interface between the channel layer 135 and the barrier layer 137. The methods for forming the electrical connection include, but are not limited to, high-temperature annealing, ion implantation, and heavy doping. The gate 150b is located between the source 150a and drain 150c and is located on the barrier layer 137. When fabricating the gate 150b, a passivation layer can also be formed on the barrier layer 137, and a T-shaped gate can be formed by depositing metal through a gate trench on the passivation layer.

[0089] S3: A metal interconnect layer 180 is fabricated on the side of the source 150a away from the substrate 110, and a source field plate 170 is fabricated on the side of the gate 150b away from the substrate 110.

[0090] Specifically, the source field plate 170 and the gate 150b are spaced apart to form a dielectric space, and the source field plate 170 and the metal interconnect layer 180 are integrally formed. A dielectric layer 190 is prepared on the side of the semiconductor epitaxial layer 130 away from the substrate 110, and the dielectric layer 190 covers the gate 150b and the drain 150c. In the process of preparing the dielectric layer 190, the dielectric layer 190 is first deposited on the side of the semiconductor layer away from the substrate 110, and then the dielectric layer 190 above the source 150a is removed by an etching process. After the dielectric layer 190 is formed (the dielectric layer 190 covers the gate 150b and the drain 150c, and the dielectric layer 190 above the source 150a needs to be removed), a photoresist layer is coated on the surface of the source 150a and the surface of the dielectric layer 190. The photoresist layer above the source 150a is displayed using the isolation structure 181 as a mask. The shape of the metal interconnect layer 180 is developed, and the shape of the source field plate 170 is developed on the photoresist layer on the dielectric layer 190. Then, metal deposition is performed, and finally, the excess metal is peeled off. During the peeling process, due to the presence of the isolation structure 181, the excess metal deposits can be connected with the metal deposits corresponding to the isolation structure 181, and the metal deposits corresponding to the isolation structure 181 are in a raised state, which makes the peeling off of excess metal easier and safer, and will not damage the metal interconnect layer 180.

[0091] It should be noted that, when fabricating the semiconductor device 100 as provided in the second embodiment, after forming the source field plate 170 and the metal interconnect layer 180, it is not necessary to remove the dielectric layer 190. The dielectric layer 190 is located between the gate 150b and the source field plate 170, thereby enabling the source field plate 170 to regulate the electric field. In the fabrication of the semiconductor device 100 as provided in the first embodiment, the dielectric layer 190 serves as a support layer, and after the source field plate 170 is formed, part or all of the dielectric layer 190 is removed, thereby creating an air dielectric between the source field plate 170 and the gate 150b.

[0092] Specifically, during the deposition of dielectric layer 190, a crystalline material (such as GaN or AlN) or an amorphous material (such as SiN) is deposited on the semiconductor epitaxial layer 130 to form dielectric layer 190 covering the source 150a, drain 150c, and gate 150b. Then, photoresist is coated on the upper surface of dielectric layer 190, the source 150a region is exposed, and the shape of source 150a is developed. Finally, the dielectric layer 190 above source 150a is removed by etching, facilitating the subsequent fabrication of metal interconnect layer 180 above source 150a. Here, the dielectric layer 190 above source 150a can be completely removed, or it can be partially removed; for example, removing 65% of the area of ​​dielectric layer 190 on source 150a. Here, it is only necessary to expose source 150a to allow the subsequent formation of metal interconnect layer 180.

[0093] This embodiment provides a method for fabricating a semiconductor device 100, which involves forming a metal interconnect layer 180 and a source field plate 170 above a metal electrode. The metal interconnect layer 180 and the source field plate 170 are integrally formed, allowing them to be integrally molded and made of the same material. Compared with existing separate structures, this method simplifies the device structure, reduces process steps, saves production costs, and improves production efficiency. Furthermore, by providing an isolation structure 181 on the metal interconnect layer 180, the isolation structure 181 divides the metal interconnect layer 180 into at least two metal conductive blocks 183. This allows the excess metal to be stripped to connect with the corresponding metal deposit at the isolation structure 181 during the deposition and formation of the metal interconnect layer 180 and the source field plate 170. It also makes the area of ​​the metal deposit to be stripped larger, making the stripping of excess metal easier and safer, without damaging the source field plate 170 and the metal interconnect layer 180. This reduces the manufacturing difficulty of the metal interconnect layer 180 and the source field plate 170 and improves the manufacturing efficiency.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The method comprises the following steps: a substrate; a semiconductor epitaxial layer on one side of the substrate; a source electrode, a gate electrode and a drain electrode on the side of the semiconductor epitaxial layer away from the substrate; a source field plate on the side of the gate electrode away from the substrate and spaced apart from the gate electrode; and a metal interconnection layer on the side of the source electrode away from the substrate and connected to the source electrode; wherein a dielectric space is formed between the gate electrode and the source field plate, and the source field plate and the metal interconnection layer are integrally arranged; an isolation structure is arranged on the metal interconnection layer, the isolation structure separates the metal interconnection layer into at least two metal conductive blocks, and at least one of the metal conductive blocks is integrally arranged with the source field plate; the projection area of the metal interconnection layer on the substrate is greater than the projection area of the source electrode on the substrate.

2. The semiconductor device according to claim 1, wherein The isolation structure comprises at least two separation line portions, and the at least two separation line portions intersect and separate the metal interconnection layer into at least two metal conductive blocks.

3. The semiconductor device of claim 2, wherein, Each of the separation line portions extends to the edge of the metal interconnection layer.

4. The semiconductor device of claim 2, wherein The source field plate and the metal interconnection layer are further integrally arranged with a plurality of connecting metal bridges, and at least one separation line portion is arranged between adjacent connecting metal bridges.

5. The semiconductor device of claim 2, wherein The isolation structure is in a hollow shape or filled with a dielectric material.

6. The semiconductor device of claim 2, wherein The distance between each adjacent two metal conductive blocks is greater than or equal to 2 microns.

7. The semiconductor device according to any one of claims 1 to 6, wherein The projection area S1 of the metal interconnection layer on the substrate is 0.4-1.6 times the projection area S2 of the source electrode on the substrate.

8. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: preparing a semiconductor epitaxial layer on one side of a substrate; preparing a source electrode, a gate electrode and a drain electrode on the side of the semiconductor epitaxial layer away from the substrate; preparing a metal interconnection layer on the side of the source electrode away from the substrate and a source field plate on the side of the gate electrode away from the substrate; wherein the source field plate is spaced apart from the gate electrode and forms a dielectric space, and the source field plate and the metal interconnection layer are integrally formed; an isolation structure is arranged on the metal interconnection layer, the isolation structure separates the metal interconnection layer into at least two metal conductive blocks, and at least one of the metal conductive blocks is integrally arranged with the source field plate; the isolation structure is in a hollow shape or filled with a dielectric material, and the projection area of the metal interconnection layer on the substrate is greater than the projection area of the source electrode on the substrate.

9. The method of producing a semiconductor device according to Claim 8, wherein Before the steps of preparing a metal interconnection layer on the side of the source electrode away from the substrate and a source field plate on the side of the gate electrode away from the substrate, the method further comprises: preparing a dielectric layer on the side of the semiconductor epitaxial layer away from the substrate, the dielectric layer covering the gate electrode and the drain electrode.

10. The method of producing a semiconductor device according to Claim 9, wherein The steps of preparing a metal interconnection layer on the side of the source electrode away from the substrate and a source field plate on the side of the gate electrode away from the substrate comprise: coating a photoresist layer on the side of the source electrode away from the substrate and the side of the dielectric layer away from the substrate, and developing the shape of the source field plate and the metal interconnection layer; performing metal deposition on the side of the photoresist layer away from the substrate; excess metal deposit is removed and the source field plate and the metal interconnect layer are formed.

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