A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes an active region and further comprises: a substrate; an electrode structure located on one side of the substrate and within the active region, the electrode structure including multiple drain electrodes; a dielectric layer located on the side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure; and multiple drain bonding pads, wherein the vertical projection of the drain bonding pads onto the plane of the substrate overlaps with the vertical projection of the drain electrodes onto the plane of the substrate, and each drain bonding pad further includes at least a portion located on the side of the dielectric layer away from the substrate, the drain bonding pads being electrically connected to drain electrodes. The solution provided by this invention, by placing at least a portion of the drain bonding pads in the active region, can significantly reduce the area of ​​the passive region, thereby reducing the overall area of ​​the semiconductor device, improving the integration density of the semiconductor device, and thus significantly reducing the cost of the chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a semiconductor material, is more suitable for manufacturing high-frequency, high-voltage, and high-temperature-resistant high-power electronic devices than first-generation and second-generation semiconductor materials due to its large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity. It also has strong spontaneous and piezoelectric polarization effects. In particular, it has obvious advantages in the fields of radio frequency and power supply.

[0003] GaN can be used to fabricate high electron mobility transistors (HEMTs). In GaN HEMT RF or power devices, the drain bonding pads are located outside the active area, occupying a large portion of the chip area, while the actual active region only occupies about 50% or less of the total chip area. For RF devices using SiC as a substrate, the chip cost accounts for a very high proportion of the final product cost. Therefore, how to reduce the chip area and thus lower the chip cost is a pressing problem that needs to be solved. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method, by placing at least a portion of the drain bonding disk in the active region, which can greatly reduce the area of ​​the passive region, thereby reducing the overall area of ​​the semiconductor device, improving the integration density of the semiconductor device, and thus greatly reducing the cost of the chip.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device including an active region;

[0006] The semiconductor device further includes:

[0007] Substrate;

[0008] An electrode structure is located on one side of the substrate and in the active region, and the electrode structure includes multiple drain electrodes;

[0009] A dielectric layer is located on the side of the electrode structure away from the substrate, and the dielectric layer covers the electrode structure;

[0010] Multiple drain bonding pads, wherein the vertical projection of the drain bonding pads onto the plane of the substrate overlaps with the vertical projection of the drain onto the plane of the substrate, and each drain bonding pad further includes at least a portion located on the side of the dielectric layer away from the substrate, and the drain bonding pads are electrically connected to the drain.

[0011] Optionally, the drain includes a first drain portion and a second drain portion that are interconnected;

[0012] The vertical projection of the drain bonding disk onto the plane of the substrate overlaps with the vertical projection of the first drain distribution onto the plane of the substrate.

[0013] Optionally, the first drain portion is provided with multiple grooves;

[0014] In a direction perpendicular to the substrate, the groove extends through the first drain portion or the bottom of the groove is located in the first drain portion;

[0015] The dielectric layer fills the groove.

[0016] Optionally, the groove may be strip-shaped, dot-matrix-shaped, or cross-shaped.

[0017] Optionally, the drain bonding disk is located on the side of the dielectric layer away from the substrate.

[0018] Optionally, in a direction perpendicular to the substrate, the drain bonding disk includes a first portion and a second portion that are interconnected.

[0019] The second portion is embedded in the dielectric layer, and the first portion is located on the side of the dielectric layer away from the substrate.

[0020] Optionally, the second portion is directly connected to the drain electrode.

[0021] Optionally, the second drain portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are respectively located on both sides of the first drain portion;

[0022] Along the first direction, the extension length of the first sub-part is L1, and the extension length of the second sub-part is L2, wherein -5% ≤ (L1-L2) / L1 ≤ 100%; the first direction is parallel to the direction from the first sub-part to the second sub-part.

[0023] Optionally, multiple drain bonding disks are located on the same side of the active region.

[0024] Optionally, the electrode structure includes multiple gate electrodes and multiple source electrodes;

[0025] The semiconductor device further includes a plurality of gate bonding disks, each gate bonding disk being at least partially located in the active region and coinciding with the source or a portion of its vertical projection on the plane of the substrate, and each gate bonding disk further including at least a portion located on the side of the dielectric layer away from the substrate, the gate bonding disk being electrically connected to the gate.

[0026] Secondly, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the aforementioned semiconductor device, wherein the semiconductor device includes an active region, and the method for fabricating the semiconductor device includes:

[0027] Provide substrate;

[0028] An electrode structure is fabricated on one side of the substrate and in the active region, the electrode structure including a plurality of drain electrodes;

[0029] A dielectric layer is prepared on the side of the electrode structure away from the substrate, and the dielectric layer covers the electrode structure;

[0030] At least one drain bonding pad is prepared on the side of the dielectric layer away from the substrate. The vertical projection of the drain bonding pad onto the plane of the substrate overlaps with the vertical projection of the drain onto the plane of the substrate, and the drain bonding pad is electrically connected to the drain.

[0031] The semiconductor device and its fabrication method provided in this invention, by setting multiple drain bonding pads electrically connected to the drain, and setting the vertical projection of the drain bonding pads on the plane of the substrate to overlap with the vertical projection of the drain on the plane of the substrate, with each drain bonding pad including at least a portion located on the side of the dielectric layer away from the substrate, can realize the setting of at least a portion of the drain bonding pads in the active region, greatly reducing the area of ​​the passive region, thereby reducing the overall area of ​​the semiconductor device, improving the integration of the semiconductor device, reducing the cost of the chip, and also facilitating the miniaturization design of the semiconductor device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art;

[0033] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0034] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line A-A';

[0035] Figure 4 yes Figure 2 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B';

[0036] Figure 5 yes Figure 2 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B';

[0037] Figure 6 yes Figure 2A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line A-A';

[0038] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0039] Figure 8 yes Figure 2 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line C-C';

[0040] Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0042] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art, such as... Figure 1 As shown, an active region a and a passive region b are provided on the substrate 11. The active region a contains a source, a gate, and a drain (not shown in the figure). The passive region b contains a gate bonding disk 12 and a drain bonding disk 13. The gate bonding disk 12 and the drain bonding disk 13 occupy a large area, which relatively increases the area of ​​the entire chip. This is not conducive to the miniaturization design of semiconductor devices, nor is it conducive to reducing the manufacturing cost of the chip.

[0043] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device comprising: a substrate, the substrate including an active region; an electrode structure located on one side of the substrate and within the active region, the electrode structure including a plurality of drains; a dielectric layer located on the side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure; and a plurality of drain bonding pads, each drain bonding pad being at least partially located within the active region, and each drain bonding pad further including at least a portion located on the side of the dielectric layer away from the substrate, the drain bonding pads being electrically connected to drains. By employing the above technical solution, at least a portion of the drain bonding pads can be disposed within the active region, significantly reducing the area of ​​the passive region, thereby reducing the overall area of ​​the semiconductor device, improving the integration density of the semiconductor device, reducing chip costs, and facilitating the miniaturization design of the semiconductor device.

[0044] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0045] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 3 yes Figure 2 A schematic cross-sectional view of the provided semiconductor device along section line A-A'. (Reference) Figure 2 and Figure 3 As shown, the semiconductor device 20 includes an active region aa;

[0046] The semiconductor device 20 also includes:

[0047] Substrate 21;

[0048] Electrode structure 22 is located on one side of substrate 21 and in active region aa. Electrode structure 22 includes multiple drain electrodes 223.

[0049] The dielectric layer 23 is located on the side of the electrode structure 22 away from the substrate 21, and the dielectric layer 23 covers the electrode structure 22.

[0050] Multiple drain bonding pads 27 are provided. The vertical projection of the drain bonding pads 27 onto the plane of the substrate 21 overlaps with the vertical projection of the drain 223 onto the plane of the substrate 21. Each drain bonding pad 27 also includes at least a portion located on the side of the dielectric layer 23 away from the substrate 21. The drain bonding pads 27 are electrically connected to the drain 223.

[0051] Specifically, the substrate 21 can be formed from one or more of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, etc., or other materials suitable for growing gallium nitride. The dielectric layer 23 can be made of dielectric materials such as silicon nitride (SiN) or silicon oxide (SiO), serving as an insulating isolation electrode structure 22 and a drain bonding disk 27.

[0052] like Figure 2 and Figure 3 As shown, the semiconductor device 20 can be divided into an active region aa and a passive region bb surrounding the active region aa. The active region aa can be understood as the region beneath which a two-dimensional electron gas, electrons, or holes exist. Its operating state and characteristics are affected by external circuits, and it is the active operating region of the semiconductor device. The passive region bb can be understood as the region that participates in the operation of the device, but its operating state is not affected by external circuits. An electrode structure 22, including multiple drains 223, is located on one side of the substrate 21 and within the active region aa, and a dielectric layer 23 covers the side of the electrode structure 22 away from the substrate 21. Figure 1 and Figure 2 As can be seen, compared with the prior art where the entire drain bonding disk 13 is set on the periphery of the active region a, the semiconductor device 20 provided in this embodiment of the invention adopts the inventive concept of "divide and conquer". The entire large-area drain bonding disk 13 in the prior art is divided into multiple small-area drain bonding disks 27 in this embodiment of the invention. The multiple small-area drain bonding disks 27 are used to electrically connect with multiple drains 223. The arrangement of the drain bonding disks 27 is flexible and can reduce the overall area of ​​the drain bonding disks 27. Furthermore, by setting the vertical projection of the drain bonding disks 27 on the plane where the substrate 21 is located to overlap with the vertical projection of the drains 223 on the plane where the substrate 21 is located, and each drain bonding disk 27 is at least partially set on the side of the dielectric layer 23 away from the substrate 21, the area of ​​the drain bonding disks 27 in the passive region bb can be greatly reduced, thereby reducing the overall area of ​​the semiconductor device, improving the integration of the semiconductor device, reducing the cost of the chip and facilitating the miniaturization design of the semiconductor device.

[0053] In this embodiment of the invention, the large drain bonding pad 27 occupying a significant chip area is divided into multiple smaller drain bonding pads 27, which are then positioned within the active region aa. This arrangement becomes more flexible and convenient, and the total chip area can be reduced by more than 30%. With almost no increase in wafer manufacturing costs, each wafer can produce more than 1.5 times the number of chips. Simultaneously, due to the significantly shortened leads of the drain 223, the associated stray inductance, capacitance, and wire delay are greatly reduced, thus improving the high-frequency characteristics and performance of the device. The technical solution provided by this embodiment of the invention can be used in both radio frequency devices and power devices.

[0054] Optionally, the semiconductor device 20 provided in the embodiments of the present invention may further include an insulating layer (not shown in the figure) located on the side of the drain bonding pad 27 away from the substrate 21, with an opening formed in the insulating layer, through which the drain bonding wire is electrically connected to the drain bonding pad 27.

[0055] Optional, continue to refer to Figure 3 As shown, the drain 223 may include a first drain portion 2231 and a second drain portion 2232 that are connected to each other; the vertical projection of the drain bonding disk 27 onto the plane where the substrate 21 is located overlaps with the vertical projection of the first drain portion 2231 onto the plane where the substrate 21 is located.

[0056] This invention creatively positions the drain bonding pad 27 above the drain 223, for example, above the first drain portion 2231, providing a way to position the drain bonding pad 27 within the active region aa. This ensures that the scheme of placing the drain bonding pad 27 at least partially within the active region aa is feasible, and that the area of ​​the drain bonding pad 27 in the passive region bb can be reduced, thereby reducing the overall area of ​​the semiconductor device, increasing the integration density of the semiconductor device, reducing the cost of the chip, and facilitating the miniaturization design of the semiconductor device.

[0057] Figure 4 yes Figure 2 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B'. Optional, refer to... Figure 4 As shown, the first drain portion 2231 can be a continuous structure.

[0058] Figure 5 yes Figure 2 Another cross-sectional view of the provided semiconductor device along section line B-B' is shown. Optional, refer to... Figure 5 As shown, multiple grooves can be provided in the first drain portion 2231. Figure 5 Four grooves (P1, P2, P3, P4, P5) are exemplarily shown in the diagram. In the direction perpendicular to the substrate 21, the grooves penetrate the first drain portion 2231, or the bottom of the grooves is located within the first drain portion 2231. The dielectric layer 23 fills the grooves (P1, P2, P3, P4, P5). By providing multiple grooves (P1, P2, P3, P4, P5) in the first drain portion 2231 and filling the grooves (P1, P2, P3, P4, P5) with the dielectric layer 23, the rigidity of the material stack below the drain bonding pad 27 can be improved. This avoids the problem of dielectric material breakage caused by deformation of the underlying metal under the mechanical stress applied during the wire bonding process.

[0059] Optionally, the shape of the grooves (P1, P2, P3, P4, P5) may include stripes, dot matrix, or cross shapes. This embodiment of the invention does not limit the shape of the grooves, as long as the shape of the grooves does not affect the normal current flow in the drain 223. For example, the shape of the grooves (P1, P2, P3, P4, P5) can be set to be consistent with the current direction in the drain 223, which improves the rigidity of the material stack and is more conducive to the transmission of drain signals in the drain 223.

[0060] Based on the above embodiments, each drain bonding disk includes at least a portion located on the side of the dielectric layer away from the substrate. This can be understood as each drain bonding disk being entirely located on the side of the dielectric layer away from the substrate, or as the drain bonding disk including a portion located on the side of the dielectric layer away from the substrate and a portion located within the dielectric layer. The above two cases will be described in detail below.

[0061] First, let's take an example where all the drain bonding disks are located on the side of the dielectric layer away from the substrate.

[0062] Optional, see reference Figure 3 As shown, the drain bonding disk 27 can be located on the side of the dielectric layer 23 away from the substrate 21. Figure 3 As shown, the drain bonding disk 27 can be located entirely on the side of the dielectric layer 23 away from the substrate 21, that is, the entire structure of the drain bonding disk 27 is located above the dielectric layer 23. Thus, the drain bonding disk 27 located above the dielectric layer 23 and the electrode structure 22 located below the dielectric layer 23 are separated by the dielectric layer 23, making the arrangement of the drain bonding disk 27 simple.

[0063] The following section will describe in detail the case where the drain bonding pad includes a portion located on the side of the dielectric layer away from the substrate, and also includes a portion located within the dielectric layer.

[0064] Figure 6 yes Figure 2 Another cross-sectional view of the provided semiconductor device along section line A-A' is shown. Optional, refer to... Figure 6 As shown, in the direction perpendicular to the substrate 21, the drain bonding pad 27 may include a first portion 271 and a second portion 272 that are interconnected; the second portion 272 is embedded in the dielectric layer 23, and the first portion 271 is located on the side of the dielectric layer 23 away from the substrate 21. Embedding the second portion 272 of the drain bonding pad 27 into the dielectric layer 23 can increase the adhesion between the drain bonding pad 27 and the dielectric layer 23, improve the mechanical stability of the drain bonding pad 27, and thus make the structure of the semiconductor device 20 more stable. It should be noted that although the drain bonding pad 27 can be divided into a first portion 271 and a second portion 272, the first portion 271 and the second portion 272 are interconnected and are formed in one step in the fabrication process.

[0065] Optional, continue to refer to Figure 6 As shown, the second portion 272 is directly connected to the drain 223. A dielectric layer 23 can be filled between the second portion 272 of the drain bonding pad 27 and the drain 223. Alternatively, the second portion 272 of the drain bonding pad 27 can be directly connected to the drain 223. Preferably, directly connecting the second portion 272 of the drain bonding pad 27 to the drain 223 reduces the drain resistance and significantly shortens the output current path length, thus reducing the corresponding parasitic inductance.

[0066] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Optional, refer to... Figure 7As shown, the second drain portion 2232 may include a first sub-portion 22321 and a second sub-portion 22322, the first sub-portion 22321 and the second sub-portion 22322 being located on both sides of the first drain portion 2231 respectively; along a first direction, the extension length of the first sub-portion 22321 is L1 and the extension length of the second sub-portion 22322 is L2, wherein -5% ≤ (L1-L2) / L1 ≤ 100%; the first direction is parallel to the direction from the first sub-portion 22321 to the second sub-portion 22322.

[0067] like Figure 7 As shown, in this embodiment of the invention, the drain bonding disk 27 can also be positioned at the middle position above the drain 223. Thus, the first drain portion 2231 of the drain 223 is distributed at the middle position of the drain 223. The second drain portion 2232 is divided into a first portion 22321 and a second portion 22322. Specifically, the extension length of the first sub-part 22321 can be defined as L1, and the extension length of the second sub-part 22322 can be defined as L2, wherein -5% ≤ (L1-L2) / L1 ≤ 100%. In this way, the gates 221 on both sides of the drain 223 can be cooled down by the drain bonding disk 27, which is beneficial to reducing the junction temperature peak in the middle of the gate 221. For example, the extension length L2 of the second portion 22322 can be set to 0, i.e. (L1-L2) / L1 = 100%, so that the drain bonding disk 27 extends to the passive region bb. Alternatively, the extension length L1 of the first portion 22321 can be set to be equal to the extension length L2 of the second portion 22322, and equal to the length of the first drain portion 2231, i.e. (L1-L2) / L1 = 0. In this way, the first drain portion 2231 is basically located in the middle of the drain 223, which is more conducive to reducing the junction temperature peak in the middle of the gate 221.

[0068] Optional, continue to refer to Figure 2 As shown, multiple drain bonding pads 27 can be located on the same side of the active region aa. Multiple drain bonding pads 27 can be located on the same side of the active region aa, or on both sides of the active region aa. Preferably, in this embodiment of the invention, multiple drain bonding pads 27 are arranged on the same side of the active region aa, thus making the arrangement of the drain bonding pads 27 beneficial for application circuit layout.

[0069] Optional, continue to refer to Figure 2As shown, the semiconductor device 20 may further include a drain bonding pad connection portion 273, which is electrically connected to a plurality of drains 223 and a plurality of drain bonding pads 27. The drain bonding pad connection portion 273 may be located within the passive region bb, and is used to realize the electrical connection between the plurality of drain bonding pads 27 and the plurality of drains 223. The technical solution provided by the embodiments of the present invention, by disposing at least a portion of the drain bonding pads 27 in the active region aa, and realizing the electrical connection between the plurality of drain bonding pads 27 and the plurality of drains 223 through the drain bonding pad connection portion 273 located in the passive region bb, can greatly reduce the area of ​​the passive region bb, thereby reducing the overall area of ​​the semiconductor device, improving the integration of the semiconductor device, reducing the cost of the chip, and also facilitating the miniaturization design of the semiconductor device.

[0070] Figure 8 yes Figure 2 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line C-C'. Optional, refer to... Figure 2 and Figure 8 As shown, the electrode structure 22 may include a plurality of gates 221 and a plurality of sources 222; the semiconductor device 20 may also include a plurality of gate bonding disks 24, each gate bonding disk 24 being at least partially located in the active region aa and coinciding with the vertical projection portion of the source 222 or drain 223 on the plane of the substrate 21, and each gate bonding disk 24 also includes at least a portion located on the side of the dielectric layer 23 away from the substrate 21, and the gate bonding disk 24 and the gate 221 are electrically connected through the gate bonding disk connection portion 243.

[0071] contrast Figure 1 and Figure 2 As can be seen, compared with the prior art where the entire gate bonding disk 12 is disposed on the periphery of the active region a, the semiconductor device 20 provided in this embodiment of the invention adopts the inventive concept of "divide and conquer". The entire large-area gate bonding disk 12 in the prior art is divided into multiple small-area gate bonding disks 24 as in this embodiment of the invention. The multiple small-area gate bonding disks 24 are used to electrically connect with multiple gates 221. The arrangement of the gate bonding disks 24 is flexible and can reduce the overall area of ​​the gate bonding disks 24. Furthermore, by disposing at least a portion of the structure of each gate bonding disk 24 within the active region aa and coinciding with the vertical projection portion of the source 222 or drain 223 on the plane where the substrate 21 is located, and by disposing at least a portion of the structure of each gate bonding disk 24 on the side of the dielectric layer 23 away from the substrate 21, the area of ​​the gate bonding disk 24 in the passive region bb can be greatly reduced, thereby reducing the overall area of ​​the semiconductor device, improving the integration of the semiconductor device, reducing the cost of the chip and facilitating the miniaturization design of the semiconductor device.

[0072] In summary, the semiconductor device provided by the embodiments of the present invention, by disposing an electrode structure including multiple drains and multiple gates on one side of a substrate, disposing a dielectric layer covering the electrode structure on the side of the electrode structure away from the substrate, disposing multiple drain bonding pads electrically connected to the drains, and disposing the vertical projection of the drain bonding pads on the plane of the substrate to overlap with the vertical projection of the drain on the plane of the substrate, with each drain bonding pad including at least a portion located on the side of the dielectric layer away from the substrate, and also disposing multiple gate bonding pads electrically connected to the gates, with at least a portion of each gate bonding pad located in the active region and coinciding with the vertical projection portion of the source or drain on the plane of the substrate, with each gate bonding pad including at least a portion located on the side of the dielectric layer away from the substrate, can realize the placement of at least a portion of the gate bonding pads and at least a portion of the drain bonding pads in the active region, greatly reducing the area of ​​the passive region, thereby reducing Smaller overall semiconductor device area increases integration density, reducing chip cost and facilitating miniaturization. Simultaneously, multiple grooves are created in the first portion of the drain directly below the drain bonding pad, and the dielectric layer is filled into these grooves. This increases the rigidity of the material stack beneath the drain bonding pad, preventing dielectric material damage caused by deformation of the underlying metal under the mechanical stress applied during wire bonding. Furthermore, embedding the second portion of the drain bonding pad into the dielectric layer increases adhesion between the pad and the dielectric layer, improving the mechanical stability of the pad and resulting in a more robust semiconductor device structure. Moreover, positioning the drain bonding pad approximately at the center above the drain allows the gates on both sides to dissipate heat through the pad, reducing the peak junction temperature at the center of the gate.

[0073] Based on the same concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device described in any of the above embodiments, the semiconductor device including an active region. Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 9 As shown, the method for fabricating this semiconductor device includes:

[0074] S110 provides a substrate.

[0075] For example, the substrate material can be Si, SiC, gallium nitride, or sapphire, or other materials suitable for growing gallium nitride.

[0076] S120. An electrode structure is fabricated on one side of the substrate and in the active region. The electrode structure includes multiple drain electrodes.

[0077] S130. A dielectric layer is prepared on the side of the electrode structure away from the substrate, and the dielectric layer covers the electrode structure.

[0078] S140. At least on the side of the dielectric layer away from the substrate, a plurality of drain bonding disks are prepared, the vertical projection of the drain bonding disks onto the plane of the substrate overlaps with the vertical projection of the drain onto the plane of the substrate, and the drain bonding disks are electrically connected to the drain.

[0079] The semiconductor device fabrication method provided in this invention involves fabricating an electrode structure containing multiple drains on one side of a substrate, then fabricating a dielectric layer covering the electrode structure on the side away from the substrate, and fabricating multiple drain bonding pads with small areas that are electrically connected to the drains on at least the side of the dielectric layer away from the substrate. The vertical projection of the drain bonding pads onto the plane of the substrate overlaps with the vertical projection of the drains onto the plane of the substrate, making the arrangement of the drain bonding pads flexible and convenient, and greatly reducing the area of ​​the passive region, thereby reducing the overall area of ​​the semiconductor device, improving the integration density of the semiconductor device, reducing the cost of the chip, and facilitating the miniaturization design of the semiconductor device.

[0080] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, Including the active region; The semiconductor device further includes: a substrate; An electrode structure is located on one side of the substrate and in the active region, and the electrode structure includes multiple drain electrodes; A dielectric layer is located on the side of the electrode structure away from the substrate, and the dielectric layer covers the electrode structure; Multiple drain bonding pads, wherein the vertical projection of the drain bonding pads onto the plane of the substrate overlaps with the vertical projection of the drain onto the plane of the substrate, and each drain bonding pad further includes at least a portion located on the side of the dielectric layer away from the substrate, and the drain bonding pads are electrically connected to the drain. The drain includes a first drain portion and a second drain portion that are connected to each other; The second drain portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are respectively located on both sides of the first drain portion; Along the first direction, the extension length of the first sub-part is L1, and the extension length of the second sub-part is L2, wherein -5% ≤ (L1-L2) / L1 ≤ 100%; the first direction is parallel to the direction from the first sub-part to the second sub-part.

2. The semiconductor device according to claim 1, characterized in that, The vertical projection of the drain bonding disk onto the plane of the substrate overlaps with the vertical projection of the first drain distribution onto the plane of the substrate.

3. The semiconductor device according to claim 2, characterized in that, The first drain portion is provided with multiple grooves; In a direction perpendicular to the substrate, the groove extends through the first drain portion or the bottom of the groove is located in the first drain portion; The dielectric layer fills the groove.

4. The semiconductor device according to claim 3, characterized in that, The groove can be strip-shaped, dot-matrix-shaped, or cross-shaped.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The drain bonding pad is located on the side of the dielectric layer away from the substrate.

6. The semiconductor device according to any one of claims 1-4, characterized in that, In a direction perpendicular to the substrate, the drain bonding disk includes a first portion and a second portion that are interconnected. The second portion is embedded in the dielectric layer, and the first portion is located on the side of the dielectric layer away from the substrate.

7. The semiconductor device according to claim 6, characterized in that, The second part is in direct contact with the drain electrode and electrically connected.

8. The semiconductor device according to claim 1, characterized in that, Multiple drain bonding pads are located on the same side of the active region.

9. The semiconductor device according to claim 1, characterized in that, The electrode structure also includes multiple gate electrodes and multiple source electrodes; The semiconductor device further includes a plurality of gate bonding disks, each gate bonding disk being at least partially located in the active region and coinciding with the vertical projection portion of the source or drain on the plane of the substrate, and each gate bonding disk further including at least a portion located on the side of the dielectric layer away from the substrate, the gate bonding disk being electrically connected to the gate.

10. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-9, wherein the semiconductor device includes an active region, characterized in that, The method for fabricating the semiconductor device includes: Provide substrate; An electrode structure is fabricated on one side of the substrate and in the active region, the electrode structure including a plurality of drain electrodes; A dielectric layer is prepared on the side of the electrode structure away from the substrate, and the dielectric layer covers the electrode structure; At least one drain bonding pad is prepared on the side of the dielectric layer away from the substrate. The vertical projection of the drain bonding pad onto the plane of the substrate overlaps with the vertical projection of the drain onto the plane of the substrate, and the drain bonding pad is electrically connected to the drain.

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