A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises an active region; the semiconductor device further comprises a substrate; an electrode structure located on one side of the substrate and the active region, the electrode structure comprising a plurality of gates and a plurality of adjacent electrodes arranged adjacent to the gates; a dielectric layer located on a side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure; a plurality of gate bonding pads, each gate bonding pad at least partially located in the active region and partially coinciding with a vertical projection of the adjacent electrode on a plane of the substrate, and each gate bonding pad further comprising a part located on a side of the dielectric layer away from the substrate, the gate bonding pad being electrically connected with the gate. The semiconductor device provided by the application sets at least part of the gate bonding pad in the active region, which can greatly reduce the area of the passive region, thereby reducing the overall area of the semiconductor device, improving the integration of the semiconductor device, and further greatly reducing the cost of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) has a large band gap, high electron mobility, high breakdown field, good heat conduction, and strong spontaneous and piezoelectric polarization effects, and is more suitable for manufacturing high-frequency, high-voltage and high-temperature-resistant power electronic devices than the first and second generation semiconductor materials, especially in the fields of radio frequency and power.

[0003] GaN can be used to manufacture high electron mobility transistors (HEMTs). The gate bonding pad of a GaN HEMT radio frequency or power device is placed outside the working area, occupying a large chip area, and the active area that actually works only accounts for about 50% or less of the total chip area. For radio frequency devices with SiC substrates, the cost of the chip accounts for a very high proportion of the final product. Therefore, how to reduce the area of the chip and thus reduce the cost of the chip is a problem to be solved at present. SUMMARY

[0004] The embodiments of the present application provide a semiconductor device and a preparation method thereof, at least part of the gate bonding pad is arranged in the active area, which can greatly reduce the area of the passive area, thereby reducing the overall area of the semiconductor device, improving the integration of the semiconductor device, and greatly reducing the cost of the chip.

[0005] In a first aspect, the embodiments of the present application provide a semiconductor device, comprising an active area;

[0006] The semiconductor device further comprises:

[0007] a substrate;

[0008] an electrode structure located on one side of the substrate and in the active area, the electrode structure comprising a plurality of gates and a plurality of adjacent electrodes arranged adjacent to the gates;

[0009] a dielectric layer located on the side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure;

[0010] a plurality of gate bonding pads, each of the gate bonding pads being at least partially located in the active area and at least partially overlapping the vertical projection of the adjacent electrode on the plane of the substrate, and each of the gate bonding pads further comprising a portion located on the side of the dielectric layer away from the substrate, the gate bonding pad being electrically connected to the gate.

[0011] Optionally, the electrode structure further comprises a source electrode and a drain electrode, and the gate electrode is located between the source electrode and the drain electrode.

[0012] The source electrode comprises a first source electrode subpart and a second source electrode subpart connected to each other.

[0013] A vertical projection of the gate electrode bonding pad on a plane where the substrate is located overlaps a vertical projection of the first source electrode subpart on the plane where the substrate is located.

[0014] Optionally, a plurality of grooves are arranged in the first source electrode subpart.

[0015] In a direction perpendicular to the substrate, the grooves penetrate the first source electrode subpart or the bottoms of the grooves are located in the first source electrode subpart.

[0016] The dielectric layer fills the grooves.

[0017] Optionally, the shape of the grooves comprises a strip, a dot matrix, a cross or an arc.

[0018] Optionally, the electrode structure further comprises a source electrode and a drain electrode, and the gate electrode is located between the source electrode and the drain electrode.

[0019] The source electrode comprises a source electrode hollow part, and a vertical projection of the gate electrode bonding pad on a plane where the substrate is located overlaps a vertical projection of the source electrode hollow part on the plane where the substrate is located.

[0020] Optionally, the electrode structure further comprises a plurality of virtual electrodes.

[0021] The plurality of virtual electrodes are arranged in the source electrode hollow part, and a vertical projection of the gate electrode bonding pad on a plane where the substrate is located overlaps vertical projections of the plurality of virtual electrodes on the plane where the substrate is located.

[0022] Optionally, the semiconductor device further comprises a heterojunction structure, and the heterojunction structure is arranged with a two-dimensional electron gas.

[0023] A vertical projection of the source electrode hollow part on a plane where the substrate is located does not overlap a vertical projection of the two-dimensional electron gas on the plane where the substrate is located.

[0024] Optionally, in a direction perpendicular to the substrate, the gate electrode bonding pad comprises a first subpart and a second subpart connected to each other.

[0025] The second subpart is embedded in the dielectric layer, and the first subpart is located on a side of the dielectric layer away from the substrate.

[0026] Optionally, the electrode structure further comprises a source electrode and a drain electrode, and the gate electrode is located between the source electrode and the drain electrode.

[0027] The vertical projection of the second part on the plane where the substrate is located is within the vertical projection coverage of the source hollow part on the plane where the substrate is located.

[0028] Optionally, the electrode structure further comprises a plurality of dummy electrodes.

[0029] The plurality of dummy electrodes are arranged in the source hollow part, and the vertical projection of the second part on the plane where the substrate is located overlaps with the vertical projection of the plurality of dummy electrodes on the plane where the substrate is located.

[0030] Optionally, the semiconductor device further comprises a source back electrode on the side of the substrate away from the electrode structure, and the source and the source back electrode are electrically connected through a via hole.

[0031] The via hole penetrates the substrate.

[0032] The vertical projection of the gate bonding pad on the plane where the substrate is located does not overlap with the vertical projection of the via hole on the plane where the substrate is located.

[0033] Optionally, the plurality of gate bonding pads are located on the same side of the active region.

[0034] Optionally, the semiconductor device further comprises a gate bonding pad connecting part, and the gate bonding pad connecting part is electrically connected with the plurality of gates and the plurality of gate bonding pads respectively.

[0035] Optionally, the electrode structure comprises a plurality of drains.

[0036] The semiconductor device further comprises a plurality of drain bonding pads, the vertical projection of the gate bonding pad on the plane where the substrate is located overlaps with the vertical projection of the drain on the plane where the substrate is located, and each of the drain bonding pads further comprises at least a part located on the side of the dielectric layer away from the substrate, and the drain bonding pad is electrically connected with the drain.

[0037] In a second aspect, an embodiment of the present application provides a preparation method of a semiconductor device, which is used for preparing the semiconductor device described in any one of the above embodiments, and the semiconductor device comprises an active region.

[0038] The preparation method of the semiconductor device comprises:

[0039] A substrate is provided.

[0040] An electrode structure is prepared on one side of the substrate and in the active region, and the electrode structure comprises a plurality of gates and a plurality of adjacent electrodes arranged adjacent to the gates.

[0041] A dielectric layer is prepared on a side of the electrode structure away from the substrate, and the dielectric layer covers the electrode structure;

[0042] A plurality of gate bonding pads are prepared at least on the active region and coinciding with a vertical projection of the adjacent electrode of the gate on a plane of the substrate, and at least on a side of the dielectric layer away from the substrate, and the gate bonding pads are electrically connected with the gate.

[0043] The semiconductor device and the preparation method thereof provided by the embodiments of the present application can realize the arrangement of at least part of the gate bonding pads in the active region, greatly reduce the area of the passive region, and thus reduce the overall area of the semiconductor device and improve the integration of the semiconductor device, which is conducive to the miniaturization design of the semiconductor device and the reduction of the cost of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a structure diagram of a semiconductor device in the prior art;

[0045] Figure 2 is a structure diagram of a semiconductor device provided by the embodiments of the present application;

[0046] Figure 3 is Figure 2 is a cross-sectional structure diagram of the semiconductor device provided by the embodiments of the present application along the cross-sectional line A-A';

[0047] Figure 4 is Figure 2 is a cross-sectional structure diagram of the semiconductor device provided by the embodiments of the present application along the cross-sectional line B-B';

[0048] Figure 5 is a top view of the recess provided by the embodiments of the present application;

[0049] Figure 6 is Figure 2 is another cross-sectional structure diagram of the semiconductor device provided by the embodiments of the present application along the cross-sectional line B-B';

[0050] Figure 7 is Figure 2 is still another cross-sectional structure diagram of the semiconductor device provided by the embodiments of the present application along the cross-sectional line B-B';

[0051] Figure 8 is Figure 2 is another cross-sectional structure diagram of the semiconductor device provided by the embodiments of the present application along the cross-sectional line A-A';

[0052] Figure 9 yes Figure 2 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B';

[0053] Figure 10 yes Figure 2 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line C-C';

[0054] Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0055] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0056] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art, such as... Figure 1 As shown, an active region a and a passive region b are disposed on the substrate 11. The active region a contains a gate and a drain (not shown in the figure), and the passive region b contains a gate bonding disk 12 and a drain bonding disk 13. The gate bonding disk 12 and the drain bonding disk 13 occupy a large area, which relatively increases the area of ​​the entire chip. This is not conducive to the miniaturization design of semiconductor devices, nor is it conducive to reducing the manufacturing cost of the chip.

[0057] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device comprising: a substrate, the substrate including an active region; an electrode structure located on one side of the substrate and within the active region, the electrode structure including a plurality of gates; a dielectric layer located on the side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure; and a plurality of gate bonding pads, each gate bonding pad being at least partially located within the active region, and each gate bonding pad further including at least a portion located on the side of the dielectric layer away from the substrate, the gate bonding pads being electrically connected to gates. By employing the above technical solution, by placing at least a portion of each gate bonding pad within the active region, and each gate bonding pad including at least a portion located on the side of the dielectric layer away from the substrate, at least a portion of the gate bonding pads can be disposed within the active region, significantly reducing the area of ​​the passive region, thereby reducing the overall area of ​​the semiconductor device, improving the integration density of the semiconductor device, reducing chip costs, and facilitating the miniaturization design of the semiconductor device.

[0058] The above is the core idea of the application, and the technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0059] Figure 2 is a structural schematic diagram of a semiconductor device provided by an embodiment of the application, Figure 3 is Figure 2 The sectional structure schematic diagram of the semiconductor device provided by the application along the section line A-A'. Referring to Figure 2 and Figure 3 , the semiconductor device 20 includes an active region aa;

[0060] The semiconductor device further includes:

[0061] a substrate 21;

[0062] an electrode structure 22 located on one side of the substrate 21 and in the active region aa, the electrode structure 22 including a plurality of gates 221 and a plurality of adjacent electrodes arranged adjacent to the gates 221;

[0063] a dielectric layer 23 located on a side of the electrode structure 22 away from the substrate 21, the dielectric layer 23 covering the electrode structure 22;

[0064] a plurality of gate bonding pads 24, each gate bonding pad 24 at least partially located in the active region aa and coinciding with a vertical projection of the adjacent electrode on a plane where the substrate 21 is located, and each gate bonding pad 24 further including a portion located on a side of the dielectric layer 23 away from the substrate 21, the gate bonding pad 24 being electrically connected with the gate 221.

[0065] Specifically, the material of the substrate 21 can be formed by one or more of silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, and the like, and can also be other materials suitable for growing gallium nitride. The material of the dielectric layer 23 can be a dielectric material such as silicon nitride SiN and silicon oxide SiO, which serves to insulate and isolate the electrode structure 22 and the gate bonding pad 24.

[0066] As Figure 2 and Figure 3As shown, the semiconductor device 20 can be divided into an active area aa and a passive area bb surrounding the active area aa, the active area aa can be understood as a region in which a two-dimensional electron gas, an electron or a hole exists below, its working state and characteristics are affected by external circuits, and it is an active working area of the semiconductor device; the passive area bb can be understood as a region participating in the working of the device, but the working state is not affected by external circuits. The electrode structure 22 including a plurality of gates 221 is located in the active area aa on one side of the substrate 21, and a dielectric layer 23 is used to cover the side of the electrode structure 22 away from the substrate 21. Compared with Figure 1 and Figure 2 It can be seen that, compared with the prior art in which the entire gate bonding pad 12 is arranged in the periphery of the active area a, the semiconductor device 20 provided by the embodiment of the present application adopts the inventive concept of “divide the whole into parts”, divides the entire large-area gate bonding pad 12 in the prior art into a plurality of small-area gate bonding pads 24 in the embodiment of the present application, the plurality of small-area gate bonding pads 24 are used to be electrically connected with the plurality of gates 221, the gate bonding pad 24 is arranged in a flexible manner and can reduce the overall area of the gate bonding pad; further, at least part of the structure of each gate bonding pad 24 is arranged in the active area aa and overlaps with the adjacent electrode of the gate 221, i.e., the source 222 or the drain 223, in the vertical projection part of the plane where the substrate 21 is located, preferably, the gate bonding pad 24 is arranged on the source 222 in the embodiment of the present application, and at least part of the structure of each gate bonding pad 24 is arranged on the side of the dielectric layer 23 away from the substrate 21, which can greatly reduce the area of the gate bonding pad 24 in the passive area bb, thereby reducing the overall area of the semiconductor device and improving the integration of the semiconductor device, while reducing the cost of the chip, which is also conducive to the miniaturization design of the semiconductor device.

[0067] In the embodiment of the present application, the gate bonding pad occupying a large chip area in the prior art is divided into a plurality of small-area gate bonding pads 24, and the plurality of gate bonding pads 24 are arranged in the active area aa, the arrangement of the gate bonding pad becomes flexible and convenient, and the total area of the chip can be reduced by more than 30%, and more than 1.5 times of chips can be produced from each wafer without increasing the cost of wafer manufacturing; at the same time, since the lead of the gate is greatly shortened, the parasitic inductance, capacitance and lead delay are greatly reduced, and thus the high-frequency characteristics and performance of the device are also improved. The technical solution provided by the embodiment of the present application can be used not only for radio frequency devices but also for power devices.

[0068] Optionally, the semiconductor device 20 provided by the embodiment of the present application can further include an insulating layer (not shown in the figure) on the side of the gate bonding pad 24 away from the substrate 21, the insulating layer has an opening, and the gate bonding wire is electrically connected with the gate bonding pad 24 through the opening.

[0069] On the basis of the above-mentioned embodiments, each gate bonding pad at least includes a part located on the side of the dielectric layer away from the substrate. It can be understood that each gate bonding pad is entirely located on the side of the dielectric layer away from the substrate, or that the gate bonding pad includes a part located on the side of the dielectric layer away from the substrate and a part located in the dielectric layer. The following will describe the two cases in detail.

[0070] First, the case that each bonding pad is entirely located on the side of the dielectric layer away from the substrate will be described.

[0071] Optionally, continuing to refer to Figure 3 It is shown that the gate bonding pad 24 can be located on the side of the dielectric layer 23 away from the substrate 21. As Figure 3 It is shown that the gate bonding pad 24 can be entirely located on the side of the dielectric layer 23 away from the substrate 21, that is, the structure of the gate bonding pad 24 is entirely located above the dielectric layer 23. In this way, the gate bonding pad 24 located above the dielectric layer 23 is spaced apart from the electrode structure 22 located below the dielectric layer 23 by the dielectric layer 23, and the gate bonding pad 24 has less influence on the electrode structure 22.

[0072] Optionally, continuing to refer to 2 and Figure 3 It is shown that the electrode structure 22 can further include a source electrode 222 and a drain electrode 223, and the gate electrode 221 is located between the source electrode 222 and the drain electrode 223. The source electrode 222 can include a first source electrode part 2221 and a second source electrode part 2222 connected to each other. The vertical projection of the gate bonding pad 24 on the plane of the substrate 21 overlaps the vertical projection of the first source electrode part 2221 on the plane of the substrate 21.

[0073] The embodiment of the present application creatively provides that the gate bonding pad 24 is located above the source electrode 222, for example, above the first source electrode part 2221, and provides a setting mode of the gate bonding pad 24 in the active area aa, which ensures that the scheme of setting the gate bonding pad 24 at least partially in the active area aa is feasible, and ensures that the area of the gate bonding pad 24 in the passive area bb can be reduced, thereby reducing the overall area of the semiconductor device and improving the integration of the semiconductor device. While reducing the cost of the chip, it is also conducive to the miniaturization design of the semiconductor device. Further, since the gate bonding pad 24 is only located above part of the source electrode 222, the parasitic capacitance between the gate bonding pad 24 and the source electrode 222 is small, and the gate bonding pad 24 has little influence on the potential of the source electrode 222 and the potential of the gate bonding pad 24, and has little influence on the performance of the semiconductor device.

[0074] Figure 4 It is Figure 2 The cross-sectional structure of the semiconductor device provided by the present application along the cross-sectional line B-B' is shown. Optionally, referring to Figure 4 It is shown that a plurality of grooves 2222 can be provided in the first source electrode part 2221. Figure 4The four recesses P1, P2, P3, P4, P5 are shown in the figure as an example; in the direction of the vertical substrate 21, the recesses penetrate the first source electrode part or the bottom of the recess is located in the first source electrode part 2221; the dielectric layer 23 fills the recesses (P1, P2, P3, P4, P5). By arranging multiple recesses (P1, P2, P3, P4, P5) in the first source electrode part 2221 and filling the dielectric layer 23 into the recesses (P1, P2, P3, P4, P5), the rigidity of the material stack below the gate bonding pad 24 can be improved, thereby avoiding the problem of damage to the dielectric material caused by the deformation of the underlying metal under the mechanical stress applied in the wire bonding process, ensuring good stability of the semiconductor device, and also reducing the parasitic capacitance between the gate and the source.

[0075] Optionally, the shape of the recesses (P1, P2, P3, P4, P5) can include a strip, a dot matrix, a cross or an arc. The embodiments of the present application do not limit the shape of the recesses, as long as the shape of the recesses does not affect the normal flow of current in the source electrode 222. Figure 5 is a top view of a recess arrangement provided by an embodiment of the present application, as shown in Figure 5 The shape of the recesses (P1, P2, P3, P4, P5) can be arranged to be consistent with the current direction in the source electrode 222, which is more conducive to the transmission of source signals in the source electrode 222 while improving the rigidity of the material stack.

[0076] Figure 6 is Figure 2 Another cross-sectional structure schematic diagram of the semiconductor device provided by the present application along the cross-sectional line B-B’ is shown in the figure. Optionally, referring to Figure 6As shown, the electrode structure 22 may further include a source 222 and a drain 223, with the gate 221 located between the source 222 and the drain 223. The source 222 may include a source cutout portion 2221', where the vertical projection of the gate bonding disk 24 onto the plane of the substrate 21 overlaps with the vertical projection of the source cutout portion 2221' onto the plane of the substrate 21. The source cutout portion 2221' of the source 222 removes all the metal in the first source portion 2221 and fills it with a dielectric layer 23. By setting the vertical projection of the gate bonding disk 24 onto the plane of the substrate 21 to overlap with the vertical projection of the source cutout portion 2221' onto the plane of the substrate 21, the source metal layer vertically below the gate bonding disk 24 is removed. This reduces the parasitic gate-source capacitance between the gate bonding disk 24 and the source 222, improving the performance of the semiconductor device. Preferably, the semiconductor device 20 provided in the embodiments of the present invention can be configured such that the vertical projection of the gate bonding disk 24 on the plane of the substrate 21 falls completely within the vertical projection of the source cutout portion 2221' on the plane of the substrate 21. Moreover, the distance between the vertical projection of the gate bonding disk 24 on the plane of the substrate 21 and the vertical projection of the source cutout portion 2221' on the plane of the substrate 21 can be greater than or equal to 0.1 micrometers, thereby further reducing the parasitic gate-source capacitance.

[0077] Figure 7 yes Figure 2 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B'. Optional, such as... Figure 7 As shown, electrode structure 22 may also include multiple virtual electrodes ( Figure 7 The example illustrates K1, K2, K3, K4, and K5. Multiple virtual electrodes (K1, K2, K3, K4, and K5) are disposed in the source cutout portion 2221'. The vertical projection of the gate bonding disk 24 onto the plane of the substrate 21 overlaps with the vertical projection of the multiple virtual electrodes onto the plane of the substrate 21. Multiple virtual electrodes (K1, K2, K3, K4, and K5) are disposed in the source cutout portion 2221'. The potentials of these virtual electrodes can be electrically suspended, meaning they are not connected to an external potential. These virtual electrodes improve the flatness of the stacked layers below the gate bonding disk 24, ensuring good support for the structure below the gate bonding disk 24. When the gate bonding disk 24 is bonded to an external device, its structure below remains stable. It should be noted that the shape of the multiple virtual electrodes (K1, K2, K3, K4, and K5) is not limited in this embodiment; they can be arranged in an array of long strips, squares, or a grid.

[0078] Optionally, the semiconductor device 20 can further comprise a heterojunction structure (not shown in the figure) in which a two-dimensional electron gas is arranged; the vertical projection of the source hollow part 2221' on the plane of the substrate 21 is not overlapped with the vertical projection of the two-dimensional electron gas on the plane of the substrate 21. That is, the two-dimensional electron gas under the gate hollow part 2221' is removed, so as to avoid the formation of a parasitic capacitance between the gate bonding pad and the two-dimensional electron gas under the gate hollow part 2221', and improve the performance of the semiconductor device.

[0079] Each gate bonding pad at least comprises a part located on the side of the dielectric layer away from the substrate. It can be understood that each gate bonding pad is entirely located on the side of the dielectric layer away from the substrate, or that the gate bonding pad comprises a part located on the side of the dielectric layer away from the substrate and a part located in the dielectric layer. The above is a detailed description of the case that each gate bonding pad is entirely located on the side of the dielectric layer away from the substrate. Next, the case that the gate bonding pad comprises a part located on the side of the dielectric layer away from the substrate and a part located in the dielectric layer will be described in detail.

[0080] Figure 8 is Figure 2 Another schematic diagram of the cross-sectional structure of the semiconductor device along the cross-sectional line A-A' is provided. Optionally, referring to Figure 8 , along the direction perpendicular to the substrate 21, the gate bonding pad 24 can comprise a first part 241 and a second part 242 connected to each other; the second part 242 is embedded in the dielectric layer 23, and the first part 241 is located on the side of the dielectric layer 23 away from the substrate 21. Embedding the second part 242 of the gate bonding pad 24 in the dielectric layer 23 can increase the adhesion between the gate bonding pad 24 and the dielectric layer 23, improve the mechanical stability of the gate bonding pad 24, and thus make the structure of the semiconductor device 20 more stable. It should be noted that although the gate bonding pad 24 can be divided into the first part 241 and the second part 242, the first part 241 and the second part 242 are connected to each other and are formed at one time in the preparation process.

[0081] Optionally, continuing to refer to Figure 8As shown, the electrode structure 22 can further include a source electrode 222 and a drain electrode 223, and the gate electrode 221 is located between the source electrode 222 and the drain electrode 223; the source electrode 222 can include a source electrode hollow part 2221'; the vertical projection of the second subpart 242 on the plane where the substrate 21 is located is located within the vertical projection covering range of the source electrode hollow part 2221' on the plane where the substrate 21 is located. The source electrode hollow part 2221' of the source electrode 222 is to dig out all the metal in the first source electrode subpart 2221', and fill it with the dielectric layer 23. The vertical projection of the second subpart 242 on the plane where the substrate 21 is located is overlapped with the vertical projection of the source electrode hollow part 2221' on the plane where the substrate 21 is located, that is, the source electrode metal layer vertically below the second subpart 242 is removed, so that the parasitic gate-source capacitance between the gate bonding pad 24 and the source electrode 222 can be reduced. Preferably, the semiconductor device 20 provided by the embodiment of the present application can be configured such that the vertical projection of the second subpart 242 of the gate bonding pad 24 on the plane where the substrate 21 is located is completely within the vertical projection of the source electrode hollow part 2221' on the plane where the substrate 21 is located, and the distance between the vertical projection of the gate bonding pad 24 on the plane where the substrate 21 is located and the vertical projection of the source electrode hollow part 2221' on the plane where the substrate 21 is located can be greater than or equal to 0.1 microns, so as to further reduce the parasitic gate-source capacitance.

[0082] Figure 9 is Figure 2 A schematic diagram of another cross-sectional structure of the semiconductor device along the cross-sectional line B-B' is provided. Optionally, reference is made to Figure 9 As shown, the electrode structure 22 can further include a plurality of virtual electrodes (K1, K2, K3, K4, K5) (exemplarily shown in the middle) Figure 9 The plurality of virtual electrodes (K1, K2, K3, K4, K5) are arranged in the source electrode hollow part 2221', and the vertical projection of the second subpart 242 on the plane where the substrate 21 is located is overlapped with the vertical projection of the plurality of virtual electrodes (K1, K2, K3, K4, K5) on the plane where the substrate 21 is located. The plurality of virtual electrodes (K1, K2, K3, K4, K5) are arranged in the source electrode hollow part 2221', and the potential of the plurality of virtual electrodes can be electrically suspended, that is, the plurality of virtual electrodes are not connected to an external potential, and the plurality of virtual electrodes can improve the flatness of the structure below the gate bonding pad 24, ensure that the structure below the gate bonding pad 24 has good supportability, and the structure below the gate bonding pad 24 is stable when the gate bonding pad 24 is bonded with an external device. It should be noted that the shape of the plurality of virtual electrodes (K1, K2, K3, K4, K5) is not limited in the embodiment of the present application, and can be an array-arranged strip, a square, or a grid.

[0083] Optionally, reference is made to Figure 2 , Figure 3 and Figure 8As shown, the semiconductor device 20 can further include a source back electrode 25 located on the side of the substrate 21 away from the electrode structure 22, and the source 222 is electrically connected to the source back electrode 25 through a via 26; the via 26 penetrates the substrate 21; the vertical projection of the gate bonding pad 24 on the plane of the substrate 21 does not overlap with the vertical projection of the via 26 on the plane of the substrate 21. The source back electrode 25 is arranged on the side of the substrate 21 away from the electrode structure 22, and is electrically connected to the source 222 through the via 26 penetrating the substrate 21, so that the source back electrode 25 can be electrically connected to the external structure to realize normal transmission of the source signal. The vertical projection of the gate bonding pad 24 on the plane of the substrate 21 does not overlap with the vertical projection of the via 26 on the plane of the substrate 21, that is, the gate bonding pad 24 is not arranged above the via 26, which can avoid the problem of damage or collapse of the laminated material near the via 26 due to instability under the mechanical stress applied in the wire bonding process, and ensure good stability of the semiconductor device structure.

[0084] Optionally, continuing to refer to Figure 2 As shown, the plurality of gate bonding pads 24 can be located on the same side of the active area aa. The plurality of gate bonding pads 24 can be located on the same side of the active area aa, or on both sides of the active area aa, preferably, the plurality of gate bonding pads 24 are arranged on the same side of the active area aa in the embodiment of the application, so that the gate bonding pad 24 is away from the drain bonding pad 27, thereby facilitating the miniaturization of the overall layout of the semiconductor device 20 and the layout of the application circuit.

[0085] Optionally, continuing to refer to Figure 2 , Figure 3 and Figure 8 As shown, the semiconductor device 20 can further include a gate bonding pad connection part 243, and the gate bonding pad connection part 243 is electrically connected to the plurality of gates 221 and the plurality of gate bonding pads 24, respectively. As shown, Figure 2 The gate bonding pad connection part 243 can be located in the passive area bb to realize electrical connection between the plurality of gate bonding pads 24 and the plurality of gates 221. The technical scheme provided by the embodiment of the application arranges at least part of the gate bonding pads 24 in the active area aa, and realizes electrical connection between the plurality of gate bonding pads 24 and the plurality of gates 221 through the gate bonding pad connection part 243 located in the passive area bb, which can greatly reduce the area of the passive area bb, thereby reducing the overall area of the semiconductor device and improving the integration of the semiconductor device, while reducing the cost of the chip, and also facilitating the miniaturization design of the semiconductor device.

[0086] Figure 10 is Figure 2 The sectional structure schematic diagram of the semiconductor device provided by the embodiment of the application along the sectional plane C-C'. Optionally, referring to Figure 2 and Figure 10As shown, the electrode structure 22 can include a plurality of drain electrodes 223; the semiconductor device 20 can further include a plurality of drain bonding pads 27, a vertical projection of the drain bonding pads 27 on a plane where the substrate 21 is located overlaps a vertical projection of the drain electrodes 223 on the plane where the substrate 21 is located, and each of the drain bonding pads 27 further includes at least a portion located on a side of the dielectric layer 23 away from the substrate 21, and the drain bonding pads 27 are electrically connected to the drain electrodes 223.

[0087] By comparison Figure 1 and Figure 2 As can be seen, compared with the prior art in which the entire drain bonding pad 13 is arranged at the periphery of the active area a, the semiconductor device 20 provided by the embodiment of the present application adopts the inventive concept of "divide the whole into parts", divides the entire large-area drain bonding pad 13 in the prior art into a plurality of small-area drain bonding pads 27 having the embodiment of the present application, the plurality of small-area drain bonding pads 27 are used to be electrically connected to the plurality of drain electrodes 223, the drain bonding pads 27 are arranged in a flexible manner and can reduce the overall area of the drain bonding pads 27; further, by arranging the drain bonding pads 27 such that a vertical projection of the drain bonding pads 27 on a plane where the substrate 21 is located overlaps a vertical projection of the drain electrodes 223 on the plane where the substrate 21 is located, and each of the drain bonding pads 27 is arranged at least partially on a side of the dielectric layer 23 away from the substrate 21, the area of the drain bonding pads 27 in the passive area bb can be greatly reduced, thereby reducing the overall area of the semiconductor device and improving the integration of the semiconductor device, which is conducive to the miniaturization design of the semiconductor device while reducing the cost of the chip.

[0088] In summary, the semiconductor device provided by the embodiment of the present application has the following advantages. The electrode structure including the plurality of gates and the plurality of drains is arranged on one side of the active region of the substrate, the dielectric layer covering the electrode structure is arranged on the side of the electrode structure away from the substrate, the plurality of gate bonding pads electrically connected with the gates are further arranged, at least part of each gate bonding pad is located in the active region and overlaps with the vertical projection of the adjacent electrode of the gate on the plane of the substrate, each gate bonding pad at least includes the part located on the side of the dielectric layer away from the substrate, the plurality of drain bonding pads electrically connected with the drains are arranged, the vertical projection of the drain bonding pad on the plane of the substrate overlaps with the vertical projection of the drain on the plane of the substrate, and each drain bonding pad at least includes the part located on the side of the dielectric layer away from the substrate. The at least part of the gate bonding pad and the at least part of the drain bonding pad can be arranged in the active region, so that the area of the passive region is greatly reduced, the overall area of the semiconductor device is reduced, the integration of the semiconductor device is improved, the cost of the chip is reduced, and the miniaturization design of the semiconductor device is facilitated. Meanwhile, the plurality of grooves are arranged in the first source subpart directly below the gate bonding pad, and the dielectric layer is filled into the grooves, so that the rigidity of the material stack below the gate bonding pad is improved, and the problem of damage of the dielectric material caused by the deformation of the metal below under the mechanical stress applied in the wire bonding process is avoided. Further, the vertical projection of the gate bonding pad on the plane of the substrate is completely within the vertical projection of the source hollow part on the plane of the substrate, so that the parasitic gate-source capacitance is reduced. Further, the plurality of virtual electrodes are arranged in the source hollow part, so that the flatness of the stack below the gate bonding pad is improved. In addition, the second part of the gate bonding pad is embedded in the dielectric layer, so that the adhesion between the gate bonding pad and the dielectric layer is increased, the mechanical stability of the gate bonding pad is improved, and the structure of the semiconductor device is more stable.

[0089] Based on the same concept, the embodiment of the present application further provides a preparation method of a semiconductor device for preparing the semiconductor device described in any one of the above embodiments. Figure 11 is a flowchart of the preparation method of the semiconductor device provided by the embodiment of the present application. As shown in the figure, Figure 11 the preparation method of the semiconductor device includes the following steps.

[0090] S110, providing a substrate.

[0091] For example, the material of the substrate can be Si, SiC, gallium nitride or sapphire, and can also be other materials suitable for growing gallium nitride.

[0092] S120, preparing an electrode structure on one side of the substrate and in the active region, the electrode structure including a plurality of gates and a plurality of adjacent electrodes arranged adjacent to the gates.

[0093] S130, a dielectric layer is prepared on the side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure.

[0094] S140, a plurality of gate bonding pads are prepared at least on the active region and coinciding with the vertical projection of the adjacent electrode of the gate on the plane of the substrate, and at least on the side of the dielectric layer away from the substrate, the gate bonding pads being electrically connected with the gate.

[0095] The preparation method of the semiconductor device provided by the embodiment of the present application, by preparing the electrode structure containing a plurality of gates on the substrate and the active region, then preparing the dielectric layer covering the electrode structure on the side of the electrode structure away from the substrate, and preparing the plurality of gate bonding pads with small area and electrically connected with the gate at least on the active region and coinciding with the vertical projection of the adjacent electrode of the gate on the plane of the substrate, and at least on the side of the dielectric layer away from the substrate, makes the setting mode of the gate bonding pads flexible and convenient, greatly reduces the area of the passive region, thereby reducing the overall area of the semiconductor device and improving the integration of the semiconductor device, which is conducive to the miniaturization design of the semiconductor device while reducing the cost of the chip.

[0096] It should be noted that the above only describes the preferred embodiments of the present application and the principles of the applied technology. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises an active region; The semiconductor device further comprises: a substrate; an electrode structure located on one side of the substrate and in the active region, the electrode structure comprising a plurality of gates and a plurality of adjacent electrodes arranged adjacent to the gates, the adjacent electrodes being either source electrodes or drain electrodes, the gates being located between the source electrodes and the drain electrodes; a dielectric layer located on a side of the electrode structure away from the substrate, the dielectric layer covering the electrode structure; a plurality of gate bonding pads, each of the gate bonding pads being at least partially located in the active region and at least partially overlapping a vertical projection of the adjacent electrodes on a plane of the substrate, and each of the gate bonding pads further comprising at least a portion located on a side of the dielectric layer away from the substrate, the gate bonding pads being electrically connected to the gates; the semiconductor device further comprising a source back electrode located on a side of the substrate away from the electrode structure, the source electrodes being electrically connected to the source back electrode through vias; the vias penetrating the substrate; a vertical projection of the gate bonding pads on the plane of the substrate does not overlap a vertical projection of the vias on the plane of the substrate.

2. The semiconductor device according to claim 1, wherein The source electrodes comprise a first source sub-portion and a second source sub-portion connected to each other; a vertical projection of the gate bonding pads on the plane of the substrate overlaps a vertical projection of the first source sub-portion on the plane of the substrate.

3. The semiconductor device of claim 2, wherein The first source sub-portion is provided with a plurality of recesses; in a direction perpendicular to the substrate, the recesses penetrate the first source sub-portion or the bottoms of the recesses are located in the first source sub-portion; the dielectric layer fills the recesses.

4. The semiconductor device according to claim 3, wherein The shape of the recesses comprises a strip, a dot array, a cross or an arc.

5. The semiconductor device of claim 1, wherein The source electrodes comprise a source hollow portion, and a vertical projection of the gate bonding pads on the plane of the substrate overlaps a vertical projection of the source hollow portion on the plane of the substrate.

6. The semiconductor device according to claim 5, wherein The electrode structure further comprises a plurality of dummy electrodes; a plurality of the dummy electrodes are arranged in the source hollow portion, and a vertical projection of the gate bonding pads on the plane of the substrate overlaps a vertical projection of the plurality of the dummy electrodes on the plane of the substrate.

7. The semiconductor device of claim 5, wherein The semiconductor device further comprises a heterojunction structure, and the heterojunction structure is provided with a two-dimensional electron gas; a vertical projection of the source hollow portion on the plane of the substrate does not overlap a vertical projection of the two-dimensional electron gas on the plane of the substrate.

8. The semiconductor device of claim 1, wherein, In a direction perpendicular to the substrate, the gate bonding pads comprise a first sub-portion and a second sub-portion connected to each other; the second sub-portion is embedded in the dielectric layer, and the first sub-portion is located on a side of the dielectric layer away from the substrate.

9. The semiconductor device of claim 8, wherein, The source electrodes comprise a source hollow portion; a vertical projection of the second sub-portion on the plane of the substrate is located within a coverage range of a vertical projection of the source hollow portion on the plane of the substrate.

10. The semiconductor device of claim 9, wherein, The electrode structure further comprises a plurality of dummy electrodes; a plurality of the dummy electrodes are arranged in the source hollow portion, and a vertical projection of the second sub-portion on the plane of the substrate overlaps a vertical projection of the plurality of the dummy electrodes on the plane of the substrate.

11. The semiconductor device of claim 1, wherein A plurality of the gate bonding pads are located on the same side of the active region.

12. The semiconductor device of claim 1, wherein, The semiconductor device further comprises gate bonding pad connection portions, each of the gate bonding pad connection portions being electrically connected to a corresponding one of the plurality of gates and a corresponding one of the plurality of gate bonding pads.

13. The semiconductor device of claim 1, wherein The semiconductor device further comprises a plurality of drain bonding pads, the gate bonding pads vertically project onto the drains in a plane of the substrate, and each of the drain bonding pads further comprises at least a portion on a side of the dielectric layer distal to the substrate, the drain bonding pads being electrically connected to the drains.

14. A semiconductor device, characterized by comprising: The semiconductor device further comprises: a substrate; an electrode structure on a side of the substrate and in the active region, the electrode structure comprising a plurality of gates and a plurality of adjacent electrodes disposed adjacent to the gates; a dielectric layer on a side of the electrode structure distal to the substrate, the dielectric layer covering the electrode structure; a plurality of gate bonding pads, each of the gate bonding pads at least partially in the active region and at least partially overlapping a corresponding one of the adjacent electrodes in a plane of the substrate, and each of the gate bonding pads further comprising at least a portion on a side of the dielectric layer distal to the substrate, the gate bonding pads being electrically connected to the gates. The electrode structure further comprises a source and a drain, the gates being between the source and the drain. The source comprises a source hollow portion, the gate bonding pads vertically projecting onto the source hollow portion in a plane of the substrate. The electrode structure further comprises a plurality of dummy electrodes. The plurality of dummy electrodes are disposed in the source hollow portion, the gate bonding pads vertically projecting onto the plurality of dummy electrodes in a plane of the substrate.

15. A method for manufacturing a semiconductor device, the semiconductor device comprising an active region, the semiconductor device being any one of the semiconductor devices of claims 1-14. The method for manufacturing the semiconductor device comprises: characterized in that providing a substrate; manufacturing an electrode structure on a side of the substrate and in the active region, the electrode structure comprising a plurality of gates and a plurality of adjacent electrodes disposed adjacent to the gates, the adjacent electrodes being a source or a drain, the gates being between the source and the drain; manufacturing a dielectric layer on a side of the electrode structure distal to the substrate, the dielectric layer covering the electrode structure; manufacturing a plurality of gate bonding pads at least in the active region and at least on a side of the dielectric layer distal to the substrate, the gate bonding pads being electrically connected to the gates. ​

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