Shielded gate field effect transistor with high-k material and method of making same

Abstract

This application relates to a shielded gate field-effect transistor with a high-permeability material and its fabrication method. The transistor includes: a substrate region, a drift region, a base region, a source region, a high-permeability voltage-degrading region, a trench region, a source electrode, a drain electrode, and a metal gate. The drift region is disposed between the substrate region and the base region, and the drain electrode is disposed below the substrate region. The drift region includes an N-type voltage-degrading region and a high-permeability voltage-degrading region. The high-permeability voltage-degrading region is made of a high-permeability material. The N-type voltage-degrading region and the high-permeability voltage-degrading region are arranged side-by-side above the substrate region. The trench region includes a control gate and a shielding gate arranged sequentially from top to bottom, and an insulating layer that isolates the control gate and the shielding gate from each other. The trench region is disposed above the high-permeability voltage-degrading region, such that the top surface of the high-permeability voltage-degrading region is in contact with the bottom surface of the shielding gate. The solution provided in this application can improve the breakdown voltage of the transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to shielded gate field-effect transistors with high permeability materials and methods for their fabrication. Background Technology

[0002] Shielded gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. This is because SGTs offer high channel density and good charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the control gate and drain, significantly reducing transfer capacitance. This results in lower specific on-resistance, lower conduction and switching losses, and higher operating frequencies for SGTs.

[0003] However, a significant limitation on the performance improvement of power devices with majority carrier conduction lies in the trade-off between breakdown voltage and specific on-resistance. The primary limitation on breakdown voltage stems from the non-uniform electric field distribution in the breakdown region. In SGTs, the electric field concentration effect at the shielding gate corner is the limiting factor. Due to the inherent heavy polysilicon doping in the shielding gate structure of traditional SGTs, when the device is in forward blocking mode, the ionized donor charge flux in the breakdown region inevitably becomes excessively concentrated at this corner, resulting in a large peak electric field and reducing the device's breakdown voltage capability.

[0004] Therefore, there is an urgent need to provide a shielded gate trench field-effect transistor that can effectively improve the breakdown voltage of the device. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this application provides a shielded gate field-effect transistor with a high permeability material and its fabrication method, which can improve the breakdown voltage of the transistor.

[0006] The first aspect of this application provides a shielded gate field-effect transistor with a high permeability material, comprising: a substrate region 1, a drift region 2, a base region 3, a source region 4, a trench region 5, a source electrode 6, a drain electrode 7, and a metal gate.

[0007] The drift region 2 is disposed between the substrate region 1 and the base region 3, with the direction from the base region 3 to the substrate region 1 being downward, and the drain electrode 7 is disposed below the substrate region 1; the drift region 2 includes: an N-type withstand voltage region 21 and a high-capacitance withstand voltage region 22; the high-capacitance withstand voltage region 22 is made of a high-capacitance material; the N-type withstand voltage region 21 and the high-capacitance withstand voltage region 22 are distributed side by side above the substrate region 1;

[0008] The trench region 5 includes a control gate 51 and a shielding gate 52 arranged sequentially from top to bottom, and an insulating layer 53 that isolates the control gate 51 and the shielding gate 52 from each other; the trench region 5 is disposed above the high-capacitance withstand voltage region 22, such that the top surface of the high-capacitance withstand voltage region 22 is in contact with the bottom surface of the shielding gate 52; the control gate 51 and the shielding gate 52 are attached to one side of the source region 4 and the substrate region 3 through the insulating layer 53;

[0009] The metal gate is disposed above the control gate 51, and the source 6 is disposed above the source region 4.

[0010] In one embodiment, the bottom surface of the high-capacitance withstand voltage region 22 is connected to the top surface of the substrate region 1.

[0011] In one embodiment, the top surface dimension of the high-capacitance withstand voltage region 22 is the same as the bottom surface dimension of the trench region 5.

[0012] In one embodiment, the relative permittivity of the high-permittivity material is greater than 100.

[0013] In one embodiment, the height ratio of the high-capacitance withstand voltage region 22 to the height of the trench region 5 is 1 to 60:1.

[0014] In one embodiment, the insulating layer (53) has a thickness of 40-150 nm on the side of the substrate region, and the insulating layer between the shielding gate and the control gate has a thickness of 1-3 μm.

[0015] In one embodiment, the width ratio of the N-type withstand voltage region 21 to the high capacitance withstand voltage region 22 is 1 to 3:1; wherein the width direction is the direction from the substrate region to the trench region.

[0016] In one embodiment, the source region 4 includes an N-type source region 41 and a P-type source region 42, which are arranged in parallel above the substrate region 3.

[0017] A second aspect of this application provides a method for fabricating a shielded gate field-effect transistor with a high permeability material, used to fabricate a shielded gate field-effect transistor with a high permeability material as described in any of the preceding claims, comprising:

[0018] The substrate region is prepared using semiconductor materials;

[0019] An N-type withstand voltage region is epitaxially formed on the substrate region;

[0020] A matrix region is formed on the N-type withstand voltage region by ion implantation or diffusion;

[0021] A groove is etched on one side of the N-type pressure-resistant region;

[0022] A high-capacitance material, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a high-capacitance withstand voltage region, a shielding gate, a control gate and an insulating layer.

[0023] A source region is formed by doping on the substrate region;

[0024] Metal is deposited above the source region, above the control gate, and below the substrate region to form the source, metal gate, and drain, respectively.

[0025] In one embodiment, the trench is etched on one side of the N-type withstand voltage region until the top surface of the substrate region is exposed at the bottom of the trench.

[0026] The technical solution provided in this application may include the following beneficial effects:

[0027] This application provides a shielded gate field-effect transistor with a high-permeability material. A high-permeability breakdown voltage region using a high-permeability material is introduced below the shielded gate, so that the drift region includes two parts: an N-type breakdown voltage region and a high-permeability breakdown voltage region. By replacing the area below the shielded gate with a high-permeability material, while maintaining the original shielded gate structure with a low gate-drain capacitance, it is equivalent to introducing a thicker insulating layer below the shielded gate, which helps to alleviate the electric field between the metal gate and the drain, making the transistor less prone to premature breakdown.

[0028] Secondly, when the device is in forward blocking mode, induced polarization charge is formed at the interface between the high-permeability breakdown region and the N-type breakdown region. This polarization charge can attract the depleted positive charge in the N-type breakdown region, thereby alleviating the strong spike electric field between the substrate region and the drift region, and thus improving the breakdown voltage of the transistor.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0030] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0031] Figure 1 This is a schematic diagram of the structure of a shielded gate field-effect transistor with a high permeability material shown in an embodiment of this application;

[0032] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate field-effect transistor with a high permeability material, as shown in the embodiments of this application. Detailed Implementation

[0033] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0034] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0035] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. Example 1

[0036] Due to the inherent heavy polysilicon doping in the shielded gate structure of traditional SGTs, when the device is in forward blocking mode, the ionized donor charge flux in the breakdown region inevitably becomes excessively concentrated at the corner, resulting in a large peak electric field and reducing the device's breakdown voltage capability. Therefore, there is an urgent need to provide a shielded gate trench field-effect transistor that can effectively improve the device's breakdown voltage.

[0037] To address the aforementioned issues, this application provides a shielded gate field-effect transistor with a high-permeability material, which can improve the transistor's breakdown voltage.

[0038] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of the structure of a shielded gate field-effect transistor with a high-permeability material, as shown in an embodiment of this application.

[0040] See Figure 1A shielded gate field-effect transistor with a high permeability material includes: a substrate region 1, a drift region 2, a base region 3, a source region 4, a trench region 5, a source electrode 6, a drain electrode 7, and a metal gate.

[0041] The drift region 2 is disposed between the substrate region 1 and the base region 3, with the direction from the base region 3 to the substrate region 1 being downward, and the drain electrode 7 is disposed below the substrate region 1; the drift region 2 includes: an N-type withstand voltage region 21 and a high-capacitance withstand voltage region 22; the high-capacitance withstand voltage region 22 is made of a high-capacitance material; the N-type withstand voltage region 21 and the high-capacitance withstand voltage region 22 are distributed side by side above the substrate region 1;

[0042] The trench region 5 includes: a control gate 51 and a shielding gate 52 arranged sequentially from top to bottom, and an insulating layer 53 that isolates the control gate 51 and the shielding gate 52 from each other; the trench region 5 is disposed above the high-capacitance withstand voltage region 22, such that the top surface of the high-capacitance withstand voltage region 22 is in contact with the bottom surface of the shielding gate 52; the control gate 51 and the shielding gate 52 are attached to one side of the source region 4 and the substrate region 3 through the insulating layer 53; the metal gate is disposed above the control gate 51, and the source electrode 6 is disposed above the source region 4.

[0043] In this embodiment, the introduction of the high-permeability breakdown voltage region 22 is equivalent to replacing the N-type doped semiconductor material located below the shielding gate 52 with a high-permeability material, thereby forming a drift region composed of the N-type breakdown voltage region 21 and the high-permeability breakdown voltage region 22 side by side. Since the dielectric is polarized in a non-vacuum environment, the total electric field inside the material will decrease. Permeability is related to the dielectric's ability to transmit electric fields. After replacing part of the N-type doped semiconductor material with a high-permeability material, induced polarization charge is formed at the interface between the high-permeability breakdown voltage region and the N-type breakdown voltage region. This polarization charge can attract the depleted positive charge in the N-type breakdown voltage region, thereby alleviating the strong spike electric field between the substrate region and the drift region, thereby improving the breakdown voltage of the transistor.

[0044] Furthermore, the relative permittivity of the high-permittivity material is greater than 100.

[0045] Preferably, theoretically, the higher the value of the high-permeability material, the better the performance improvement of the transistor device. In order to achieve a significant improvement in breakdown voltage, the relative permittivity of the high-permeability material needs to be set to be greater than 100.

[0046] Furthermore, the bottom surface of the high-capacitance withstand voltage region 22 is connected to the top surface of the substrate region 1, that is, the high-capacitance withstand voltage region 22 completely fills the area between the substrate region 1 and the shielding gate 52.

[0047] Furthermore, the top surface dimension of the high-capacitance withstand voltage region 22 is the same as the bottom surface dimension of the trench region 5, that is, the interface between the trench region 5 and the substrate region 3 and the source region 4 is located on the same plane as the interface between the high-capacitance withstand voltage region 22 and the N-type withstand voltage region 21.

[0048] Furthermore, the height ratio of the high-capacitance withstand voltage region 22 to the height of the trench region 5 is 1 to 60:1.

[0049] It should be noted that the height ratio of the high-capacitance withstand voltage region 22 to the trench region 5 depends on the withstand voltage of the transistor device. Corresponding to a breakdown voltage of 100V to 950V, the height ratio can be set to 1:1 to 60:1.

[0050] Furthermore, the width ratio of the N-type withstand voltage region 21 and the high-capacitance withstand voltage region 22 is 1 to 3:1; wherein, the width direction is the direction from the substrate region 3 to the trench region 5.

[0051] Furthermore, in the insulating layer, the thickness of the insulating layer on the side of the substrate region is 40–150 nm; the thickness of the insulating layer between the shielding gate and the control gate is 1–3 μm.

[0052] In this embodiment, substrate region 1 is N-type doped with a heavy doping concentration; N-type breakdown voltage region 21 is lightly doped; substrate region 3 is P-type doped with a medium doping concentration; source region 4 is heavily doped; and shielding gate 52 and control gate 51 are P-type or N-type doped with heavy doping concentrations.

[0053] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0054] The shielded gate field-effect transistor provided in this application embodiment introduces a high-capacitance breakdown voltage region using a high-capacitance material below the shielded gate, so that the drift region includes two parts: an N-type breakdown voltage region and a high-capacitance breakdown voltage region. By replacing the area below the shielded gate with a high-capacitance material, while maintaining the original shielded gate structure with a low gate-drain capacitance, it is equivalent to introducing a thicker insulating layer below the shielded gate, which helps to alleviate the electric field between the metal gate and the drain, making the transistor less prone to premature breakdown.

[0055] Secondly, when the device is in forward blocking mode, induced polarization charge is formed at the interface between the high-permeability breakdown region and the N-type breakdown region. This polarization charge can attract the depleted positive charge in the N-type breakdown region, thereby alleviating the strong spike electric field between the substrate region and the drift region, and thus improving the breakdown voltage of the transistor. Example 2

[0056] Corresponding to the shielded gate field-effect transistor with high permeability material shown in Embodiment 1 above, this application also provides a method for fabricating a shielded gate field-effect transistor with high permeability material and corresponding embodiments.

[0057] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate field-effect transistor with a high permeability material, as shown in the embodiments of this application.

[0058] See Figure 2 The method for fabricating the shielded gate field-effect transistor with high permeability material includes:

[0059] 201. Fabrication of substrate regions using semiconductor materials;

[0060] In this embodiment, the substrate region is formed using an N-type heavily doped semiconductor material. The semiconductor material is either silicon or silicon carbide.

[0061] 202. An N-type breakdown voltage region is epitaxially formed on the substrate region;

[0062] 203. Form the matrix region on the N-type withstand voltage region by ion implantation or diffusion;

[0063] Epitaxial growth refers to the process of forming a single-crystal film on a single-crystal substrate, whereby the single-crystal film grows by extending along the crystal structure of the substrate. In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0064] 204. A groove is etched on one side of the N-type pressure-resistant area;

[0065] In this embodiment of the application, the depth of the etched trench can be the sum of the heights of the source region, the substrate region, and the drift region. That is, in step 204, the top surface of the substrate region is etched to expose the bottom of the trench, so that the high-capacitance material subsequently deposited is in contact with the top surface of the substrate region.

[0066] 205. High-permeability material, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form a high-permeability withstand voltage region, a shielding gate, a control gate and an insulating layer.

[0067] In the embodiments of this application, the polycrystalline silicon is a polycrystalline silicon material with a heavy doping concentration.

[0068] 206. Doping is performed on the substrate region to form the source region;

[0069] For example:

[0070] Above the substrate region, P-type and N-type source regions are formed by doping along the width direction of the drift region using P-type and N-type heavily doped semiconductor materials, respectively, so that the P-type and N-type source regions are arranged parallel above the substrate region.

[0071] In practical applications, P-type heavily doped semiconductor materials and N-type heavily doped semiconductor materials can be alternately doped along the length of the drift region to form staggered P-type and N-type source regions.

[0072] It should be noted that the above description of the source region structure is merely an example given in the embodiments of this application and does not constitute the sole limitation of this application.

[0073] In this embodiment of the application, there is no strict limitation on the execution order of steps 206 and 207. Step 207 can be executed before step 206.

[0074] 207. Deposit metal above the source region, above the control gate, and below the substrate region to form the source, metal gate, and drain, respectively.

[0075] It should be noted that, in the embodiments of this application, after the source region is doped, a metal can be deposited above the source region to form the source electrode; after a high-capacitance material, polysilicon, oxide, and polysilicon are sequentially deposited in the trench to form a high-capacitance withstand voltage region, a shielding gate, a control gate, and an insulating layer, a metal gate can be formed above the control gate; after the substrate region is formed, a drain can be formed at the bottom of the substrate region. That is, the timing of the execution of step 207 is not unique and should not be considered the sole limitation of this application.

[0076] The shielded gate field-effect transistor with high permeability material prepared by the preparation method shown in the embodiments of this application has an induced polarization charge formed at the interface between the high permeability breakdown region and the N-type breakdown region when it is in forward blocking. This polarization charge can attract the depleted positive charge in the N-type breakdown region, thereby alleviating the strong peak electric field between the substrate region and the drift region, thereby improving the breakdown voltage of the transistor.

[0077] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0078] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0079] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0080] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate field effect transistor having a high dielectric constant material, characterized by, It includes: Substrate area (1), drift area (2), base area (3), source area (4), trench area (5), source (6), drain (7) and metal gate; The drift area (2) is arranged between the substrate area (1) and the base area (3), and the base area (3) is directed to the direction of the substrate area (1) below, and the drain (7) is arranged below the substrate area (1); The drift area (2) includes: N-type voltage resistance area (21) and high dielectric constant voltage resistance area (22); The high dielectric constant voltage resistance area (22) adopts high dielectric constant material; The N-type voltage resistance area (21) and the high dielectric constant voltage resistance area (22) are distributed side by side above the substrate area (1); The trench area (5) includes: control gate (51) and shielding gate (52) arranged in turn from top to bottom, and insulation layer (53) for isolating the control gate (51) and the shielding gate (52) from each other; The trench area (5) is arranged above the high dielectric constant voltage resistance area (22), so that the top surface of the high dielectric constant voltage resistance area (22) is connected with the bottom surface of the shielding gate (52); The control gate (51) and the shielding gate (52) are attached to one side of the source area (4) and the base area (3) through the insulation layer (53); The metal gate is arranged above the control gate (51), and the source (6) is arranged above the source area (4); The bottom surface of the high dielectric constant voltage resistance area (22) is connected with the top surface of the substrate area (1); The interface between the high dielectric constant voltage resistance area (22) and the N-type voltage resistance area (21) forms induced polarization charge, and the induced polarization charge attracts the depleted positive charge in the N-type voltage resistance area (21); The shielding gate (52) is electrically connected with the source (6), and the control gate (51) is electrically connected with the metal gate.

2. The shielding gate field effect transistor with high dielectric constant material according to claim 1, wherein the top surface size of the high dielectric constant voltage resistance area (22) is consistent with the bottom surface size of the trench area (5).

3. The shielding gate field effect transistor with high dielectric constant material according to claim 1, wherein the relative dielectric constant of the high dielectric constant material is greater than 100.

4. The shielding gate field effect transistor with high dielectric constant material according to claim 1, wherein the height ratio of the high dielectric constant voltage resistance area (22) to the trench area (5) is 1-60:

1.

5. The shielding gate field effect transistor with high dielectric constant material according to claim 1, wherein in the insulation layer (53), the thickness of the insulation layer on the base area side is 40-150 nm, and the thickness of the insulation layer between the shielding gate and the control gate is 1-3 μm.

6. The shielding gate field effect transistor with high dielectric constant material according to claim 1, wherein the width ratio of the N-type voltage resistance area (21) to the high dielectric constant voltage resistance area (22) is 1-3:1; wherein the width direction is the direction of the base area to the trench area. ​ ​ ​ ​ ​ 7. The shielded gate field effect transistor with high-k material of claim 1, wherein: the source region (4) comprises an N-type source region (41) and a P-type source region (42), and the N-type source region (41) and the P-type source region (42) are arranged in parallel above the substrate region (3).

8. A method of fabricating a shielded gate field effect transistor having a high-k material, comprising: A method for manufacturing the shielded gate field effect transistor with high-k material as claimed in any one of claims 1-7, comprising: manufacturing a substrate region with a semiconductor material; forming an N-type voltage-resisting region epitaxially on the substrate region; forming a substrate region by ion implantation or diffusion on the N-type voltage-resisting region; etching a trench on one side of the N-type voltage-resisting region; sequentially depositing high-k material, polysilicon, oxide and polysilicon in the trench to form a high-k voltage-resisting region, a shielded gate, a control gate and an insulation layer; forming a source region by doping on the substrate region; depositing a metal source, a metal gate and a drain on the source region, above the control gate and below the substrate region respectively, the shielded gate is electrically connected with the source, and the control gate is electrically connected with the metal gate; in the etching a trench on one side of the N-type voltage-resisting region, the etching reaches the top surface of the substrate region and exposes the bottom of the trench.

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