A semiconductor device

Abstract

The present application provides a semiconductor device. The semiconductor device includes: a substrate having a first conductivity type; a shallow trench isolation structure disposed in the substrate and having a first annular structure, wherein the region of the substrate surrounded by the shallow trench isolation structure is an active region; a drain doped region having a second conductivity type, disposed on the upper surface of the central region of the active region; a source doped region having a second conductivity type, disposed on the upper surface of the active region on both sides of the drain doped region and spaced apart from the drain doped region; a field oxide layer disposed on the upper surface of the substrate within the active region and having a second annular structure, surrounding the drain doped region; a gate polycrystalline layer disposed on the upper surface of the substrate and having a third annular structure, surrounding the field oxide layer; and a drift region having a second conductivity type, disposed in the substrate and surrounding the drain doped region.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor device. Background Art

[0002] In the design of N-type lateral double-diffused metal oxide semiconductor (NLDMOS) devices, using STI (shallow trench isolation) in the drift region to enhance voltage resistance is no longer sufficient. This is primarily due to the following: To meet the high voltage and low on-resistance requirements of high-voltage NLDMOS devices, the doping concentration in the drift region must be increased. However, the STI structure, due to its inherent morphological characteristics, generates a large electric field at the corners. In high-voltage applications, especially ultra-high voltage applications with voltage requirements exceeding 100V, this electric field can cause premature device breakdown and severe degradation of electrical properties, thus limiting its application in ultra-high voltage NLDMOS devices.

[0003] To solve this problem, there are some improvement methods, such as replacing the STI structure in the drift region with a local oxidation of silicon (LOCOS) structure to help the device withstand voltage. Although this method can effectively help improve the device's withstand voltage, how to perfectly combine the LOCOS process with the STI process to reduce the adverse effects of process compatibility on the device is a problem that needs to be solved. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In order to overcome at least one of the existing problems, the present application provides a semiconductor device in a first aspect, comprising:

[0006] a substrate having a first conductivity type;

[0007] A shallow trench isolation structure is provided in the substrate and is in a first annular structure, wherein the area of ​​the substrate surrounded by the shallow trench isolation structure is an active area;

[0008] a drain doped region having a second conductivity type, the first conductivity type being opposite to the second conductivity type, and being disposed on an upper surface of a central region of the active region;

[0009] a source doped region having a second conductivity type, disposed on the upper surface of the active region on both sides of the drain doped region and spaced apart from the drain doped region, wherein a connection direction between the drain doped region and the source doped region is a first direction, and a direction in the plane of the substrate and perpendicular to the first direction is a second direction;

[0010] a field oxide layer, disposed on the upper surface of the substrate in the active area and having a second annular structure, surrounding the drain doping region, with a preset distance between an outer boundary of the field oxide layer and the shallow trench isolation structure, the preset distance being greater than 0;

[0011] a gate polycrystal, disposed on the upper surface of the substrate and in a third annular structure, surrounding the field oxide layer, wherein in the first direction, the gate polycrystal extends from above the source doping region to above the field oxide layer, and in the second direction, the gate polycrystal extends from above the shallow trench isolation structure to above the field oxide layer, and a gate oxide layer is further provided between the gate polycrystal and the substrate;

[0012] A drift region has a second conductivity type, is disposed in the substrate and surrounds the drain doping region and is spaced apart from the source doping region. The drift region further extends along the second direction to below the shallow trench isolation structure.

[0013] Optionally, an extension region of the active region in the second direction is a device voltage-withstanding region; and a region between the drain doping region and the source doping region of the active region in the first direction is a device working and voltage-withstanding region.

[0014] Optionally, a length dimension of the field oxide layer in the first direction is smaller than a length dimension of the field oxide layer in the second direction.

[0015] Optionally, a length dimension of the gate polycrystal in the first direction is smaller than a length dimension of the gate polycrystal in the second direction.

[0016] Optionally, in the second direction, a preset distance between an outer boundary of the field oxide layer and the shallow trench isolation structure is 0.5 um to 0.8 um.

[0017] Optionally, the second annular structure and the third annular structure are both octagonal annular structures.

[0018] Optionally, the outer contour of the drift region is an octagon in a plane.

[0019] Optionally, the geometric center of the first annular structure on the horizontal plane, the geometric center of the second annular structure on the horizontal plane, the geometric center of the third annular structure on the horizontal plane, and the geometric center of the outer contour of the drift zone on the horizontal plane coincide with each other.

[0020] Optionally, the field oxide layer is a silicon local oxidation field oxide layer.

[0021] Optionally, a metal field plate is further included, which is arranged across the gate polycrystalline and the field oxide layer, and a dielectric layer is provided between the metal field plate and the gate polycrystalline, and between the metal field plate and the field oxide layer.

[0022] In the semiconductor device described in the present application, the shallow trench isolation structure is used to define the boundary of the active area, and the field oxide layer is formed within the active area. Through the setting, the shallow trench isolation structure and the field oxide layer are completely separated from each other. Through the improvement, without sacrificing the overall size of the device and the high voltage resistance requirements, the surface damage of the device caused by the superposition of etching and exposure processes is effectively avoided, which is conducive to helping solve the degradation of device characteristics and reliability problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0024] In the attached figure:

[0025] Figure 1 1 shows a schematic top view of a semiconductor device according to an embodiment of the present application and a cross-sectional view along line A-A1;

[0026] Figure 2 A schematic top view of a semiconductor device in another embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0028] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0029] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0030] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] In order to fully understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0033] An exemplary structure compatible with the LOCOS process and the STI process is as follows:

[0034] The channel and source terminals of the NLDMOS device are centered, with the drift region and LOCOS layer distributed around them in a ring. The drain, as the drift region terminal, is distributed in the outermost ring. This method can distinguish STI from LOCOS. Its disadvantage is that since the device drift region is connected to the outer isolation region, its size needs to be expanded to meet the external PN junction withstand voltage. Ultimately, the drift region size is much larger than the drift region size required for the device's own withstand voltage, resulting in a significant waste of area and reduced product competitiveness.

[0035] In an NLDMOS device, the drift region and drain terminals are centered in a strip-like pattern; the channel and source terminals are arranged on either side of the device. The LOCOS strips extend from the active area within the drift region, overlapping the STI region. While this approach avoids the voltage withstand issues between the drift region and the surrounding P-type junction, it has a disadvantage: the partial overlap between the LOCOS and STI regions leads to repeated etching, exposure, and thermal processes in this area, causing surface defects and interface states on the device, disrupting the surface morphology. This ultimately causes device reliability tests to fail and severely degrades device characteristics.

[0036] The LOCOS and STI regional interfaces are directly divided to the periphery of the entire device working area. That is, the isolation of the device's internal areas, such as the source, body, and drain, is completely handled by the LOCOS region. LOCOS also meets the voltage resistance requirements of the device's drift region, while the STI portion is only located outside the device's bulk ring, used to distinguish and isolate one device from another. Although this method can clearly distinguish the STI and LOCOS regions, the characteristics of the LOCOS process itself result in the internal device isolation size being much larger than the STI isolation method. For example, for the source and body regions, conventional STI isolation only requires 0.36μm, while the LOCOS process requires at least 0.6-0.8μm. This results in a significant waste of area in highly integrated chip circuit design. In addition, because the isolation interface relationship between LOCOS and STI must be considered for each device, the platform development and design becomes more complex.

[0037] The present application provides a semiconductor device, such as Figure 1 As shown, the semiconductor device includes:

[0038] The substrate 101 has a first conductivity type;

[0039] A shallow trench isolation structure 108 is disposed in the substrate 101 and is in a first ring structure. The area of ​​the substrate 101 surrounded by the shallow trench isolation structure 108 is the active area 105;

[0040] a drain doped region 103 having a second conductivity type, the first conductivity type being opposite to the second conductivity type, and being disposed on the upper surface of the central region of the active region 105;

[0041] a source doped region 102 having a second conductivity type, disposed on the upper surface of the active region 105 on both sides of the drain doped region and spaced apart from the drain doped region 103; a connection direction between the drain doped region 103 and the source doped region 102 being a first direction, and a direction within the plane of the substrate 101 and perpendicular to the first direction being a second direction;

[0042] a field oxide layer 104 disposed on the upper surface of the substrate 101 within the active region 105 and having a second annular structure, surrounding the drain doped region 103 , with a preset distance between the outer boundary of the field oxide layer 104 and the shallow trench isolation structure 108 , the preset distance being greater than 0;

[0043] a gate polycrystal 106 disposed on the upper surface of the substrate 101 and having a third annular structure, surrounding the field oxide layer 104; in the first direction, the gate polycrystal 106 extends from above the source doped region 102 to above the field oxide layer 104; in the second direction, the gate polycrystal 106 extends from above the shallow trench isolation structure 108 to above the field oxide layer 104; a gate oxide layer is further provided between the gate polycrystal 106 and the substrate 101;

[0044] The drift region 107 has the second conductivity type and is disposed in the substrate 101 and surrounds the drain doping region 103 and is spaced apart from the source doping region 102 . The drift region 107 further extends along the second direction to below the shallow trench isolation structure 108 .

[0045] Among them, the shallow trench isolation structure described in this application is used to define the boundary of the active area, and the field oxide layer is formed within the active area. Through the setting, the shallow trench isolation structure and the field oxide layer are completely separated from each other. Through the improvement, without sacrificing the overall size of the device and the high voltage resistance requirements, the surface damage of the device caused by the superposition of etching and exposure processes is effectively avoided, which is conducive to helping solve the degradation of device characteristics and reliability problems.

[0046] The semiconductor device of the present application is described in detail below with reference to the accompanying drawings. Figure 1 1 shows a schematic top view of the semiconductor device described in an embodiment of the present application and a cross-sectional view along A-A1.

[0047] like Figure 1As shown, wherein the substrate 101 in the semiconductor device is Figure 1 The square area described in , wherein the substrate 101 can be at least one of the following materials: silicon, polysilicon or silicon on insulator (SOI).

[0048] In one embodiment of the present application, the substrate 101 is silicon.

[0049] In one embodiment of the present invention, the substrate 101 is a doped substrate 101 having a first conductivity type; for example, it is a P-type substrate 101 .

[0050] A shallow trench isolation (STI) structure 108 is formed in the semiconductor device and is disposed in the substrate in a first annular structure. The annular structure is a projection on a horizontal plane, and the area of ​​the substrate surrounded by the shallow trench isolation structure 108 is an active area 105. In one example, the first annular structure is an octagonal annular structure.

[0051] The shallow trench isolation structure 108 (STI) is located in the substrate 101, and the substrate 101 is divided into a field region and an active region 105 by the shallow trench isolation structure 108 (STI), wherein the active region 105 refers to the region in the substrate 101 surrounded by the shallow trench isolation structure 108, so the outer boundary of the active region 105 overlaps with the inner boundary of the STI structure.

[0052] The shallow trench isolation structure 108 includes a trench, or may be further filled with an isolation oxide in the trench. Its specific structure and preparation method may refer to conventional structures and processes, and will not be described in detail here.

[0053] In this application, continue as Figure 1 As shown, the extended area of ​​the active area 105 in the second direction B-B1 is the device voltage-withstand region; the area between the drain doping region and the source doping region of the active area in the first direction A-A1 is the device working and voltage-withstand region. The dimensions of the device voltage-withstand region and the dimensions of the device working and voltage-withstand region must both meet the voltage-withstand requirements of the semiconductor device of this application. The first direction A-A1 is the length direction of the device's conductive channel, and the second direction B-B1 is the width direction of the device's conductive channel.

[0054] The source doping region 102 and the drain doping region 103 are formed in the device working and voltage-resistant region, and the source doping region 102 and the drain doping region 103 are sequentially arranged along the first direction A-A1, as shown in FIG. Figure 1 shown.

[0055] In one embodiment of the present application, the first direction A-A1 is a horizontal direction, and a drain doping region 103, a gate polycrystalline 106 and a source doping region 102 are sequentially arranged from left to right along the horizontal direction. A P-type substrate 101 lead-out structure may be further arranged on the outside of the source doping region 102.

[0056] The source doping region 102 and the drain doping region 103 are formed by ion implantation, which will not be described in detail here.

[0057] Among them, the drain doping region 103 has a second conductivity type, for example, N-type doping, the first conductivity type and the second conductivity type are opposite conductivity types, and is arranged on the upper surface of the central area of ​​the active area; the source doping region 102 has a second conductivity type, for example, N-type doping, and is arranged on the upper surface of the active area on both sides of the drain doping region, and is spaced apart from the drain doping region.

[0058] On a horizontal plane, the extension regions are disposed at the upper and lower ends of the active region, and are located above the voltage-withstand region of the NLDMOS device. In this application, the voltage-withstand structure includes active regions 105 in both the first direction A-A1 (i.e., the length direction of the conductive channel) and the second direction B-B1 (i.e., the width direction of the conductive channel). Their structures are consistent, so the voltage-withstand dimensions in the first direction A-A1 can be applied to the second direction B-B1, helping to reduce the device's dimensions in the second direction B-B1.

[0059] The active region 105 is arranged in an octagonal shape in the second direction B-B1, and the region where the extended source doping region 102 is located is arranged in the first direction A-A1. Figure 1 As shown, the critical dimension of the active region 105 in the second direction B-B1 is greater than the critical dimension of the active region 105 in the first direction A-A1.

[0060] In the present application, a field oxide layer 104 is further provided in the active region 105 and has a second annular structure, surrounding the drain doping region. A preset distance is provided between the outer boundary of the field oxide layer 104 and the shallow trench isolation structure, and the preset distance is greater than 0. The second annular structure is an octagonal annular structure.

[0061] In one embodiment of the present application, the field oxide layer 104 is a local oxidation of silicon field oxide layer 104 (LOCOS). The local oxidation of silicon field oxide layer 104 is selectively oxidized using silicon nitride as a mask and is also referred to as a field oxide layer 104 .

[0062] The field oxide layer 104 is located within the boundary of the active area 105, and a certain distance is set between the boundary of the field oxide layer 104 and the boundary of the active area 105, and the inner boundary of the shallow trench isolation structure 108 overlaps with the outer boundary of the active area 105. By introducing the active area 105 layer in the second direction B-B1, the field oxide layer 104 (for example, the LOCOS area) and the STI area in the second direction B-B1 can be spaced and isolated from each other to avoid surface defects, interface states and morphology problems caused by repeated operations of etching, exposure and other processes in the STI process and the field oxide layer 104 preparation process (LOCOS process), which can further improve the performance and yield of the device.

[0063] In the second direction B-B1, the distance k between the boundary of the active area 105 and the boundary of the field oxide layer 104 should not be too small to ensure the withstand voltage of the NLDMOS device in the second direction B-B1, nor should it be too large. In one embodiment of the present application, the distance between the boundary of the active area 105 and the outer boundary of the field oxide layer 104 is 0.5um~0.8um, that is, in the second direction, the preset spacing between the outer boundary of the field oxide layer and the shallow trench isolation structure is 0.5um~0.8um.

[0064] The length of the field oxide layer 104 in the first direction A-A1 is smaller than the length of the field oxide layer in the second direction B-B1.

[0065] The present application further includes a drift region 107, such as Figure 1 As shown, the drift region 107 is formed in the substrate 101 and has a different doping type from the substrate 101. The drift region 107 is disposed in the substrate 101 and surrounds the drain doping region 103, and is spaced apart from the source doping region 102. The drift region 107 also extends along the second direction B-B1 to below the shallow trench isolation structure.

[0066] For example, in one embodiment of the present application, the substrate 101 is P-type doped, and the drift region 107 is N-type doped.

[0067] The drift region 107 is octagonal. For example, in one embodiment of the present application, the top view of the drift region 107 is an octagonal structure. The LOCOS is formed on the drift region 107. The outer boundary of the drift region 107 completely surrounds and encloses the outer boundary of the LOCOS.

[0068] In the present application, the semiconductor device further includes a gate polycrystalline 106 , which surrounds and encloses the field oxide layer 104 .

[0069] An N-well 110 is further formed in the drift region 107 , and the drain doping region 103 is formed in the N-well 110 . The doping depth of the N-well 110 may be greater than the doping depth of the drift region 107 .

[0070] In one embodiment of the present application, the gate polycrystalline 106 extends in a first direction from the boundary of the source doped region 102 within the active region 105 of the channel region to the field oxide layer 104. The gate polycrystalline 106 located on the field oxide layer acts as a field plate structure, further improving the device's withstand voltage. This arrangement can meet the withstand voltage requirements of high-voltage devices, particularly NLDMOS devices with withstand voltage requirements exceeding 100V. The gate polycrystalline 106 has a third ring structure, which is an octagonal ring structure.

[0071] The geometric center of the first annular structure on the horizontal plane, the geometric center of the second annular structure on the horizontal plane, the geometric center of the third annular structure on the horizontal plane, and the geometric center of the outer contour of the drift region on the horizontal plane coincide with each other.

[0072] Furthermore, the semiconductor device also includes: an interconnection structure, which can be one of a through-hole and a plug. By setting the interconnection structure, an electrical connection is formed with the source doping region 102, the drain doping region 103, the gate polycrystalline 106 and the substrate 101, so as to lead the source doping region 102, the drain doping region 103, the gate polycrystalline 106 and the substrate 101 out for packaging.

[0073] In one embodiment, the semiconductor device further includes: a metal field plate 109, and the top view of the semiconductor device is as shown in FIG. Figure 2 As shown. A metal field plate 109 is positioned above the gate polycrystalline 106 and the field oxide layer 104, with a dielectric layer disposed between the metal field plate 109 and the gate polycrystalline 106, and a dielectric layer also disposed between the metal field plate 109 and the field oxide layer 104. The metal field plate 109 is located above the drift region and is larger than the gate. This helps further improve the withstand voltage of the device's drift region, thereby meeting the withstand voltage requirements of high-voltage devices, particularly the withstand voltage requirement of NLDMOS devices exceeding 100V.

[0074] In the present application, through the improvements described, a field oxide layer is added to a platform based on the STI process, and a new high-voltage semiconductor device is proposed; the field oxide layer only exists in the drift region of the high-voltage device, and can be effectively isolated from the STI region in the first direction and the second direction. Without sacrificing the area of ​​the device and its isolation region, the adverse effects of repeated etching and exposure of the field oxide layer and the STI region, such as device surface defects and irregular morphology, are avoided due to the overlap of the field oxide layer and the STI region.

[0075] The technical terms used herein have the same meaning as those generally understood by those skilled in the art in the technical field of this application. The terms used herein are only for describing specific implementation purposes and are not intended to limit this application. Terms such as "part" and "component" appearing in this article may refer to either a single part or a combination of multiple parts. Terms such as "installation" and "setting" appearing in this article may refer to either a component being directly attached to another component or a component being attached to another component through an intermediate component. Features described in this article in one embodiment may be applied to another embodiment alone or in combination with other features, unless the feature is not applicable in the other embodiment or otherwise stated.

[0076] The present application has been described through the above-described embodiments, but it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present application to the described embodiments. In addition, it will be understood by those skilled in the art that the present application is not limited to the above-described embodiments, and that various variations and modifications may be made based on the teachings of the present application, all of which fall within the scope of protection claimed in the present application. The scope of protection of the present application is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; A shallow trench isolation structure is provided in the substrate and is in a first annular structure, wherein the area of ​​the substrate surrounded by the shallow trench isolation structure is an active area; a drain doped region having a second conductivity type, the first conductivity type being opposite to the second conductivity type, and being disposed on an upper surface of a central region of the active region; a source doped region having a second conductivity type, disposed on the upper surface of the active region on both sides of the drain doped region and spaced apart from the drain doped region, wherein a connection direction between the drain doped region and the source doped region is a first direction, and a direction in the plane of the substrate and perpendicular to the first direction is a second direction; a field oxide layer, disposed on the upper surface of the substrate in the active area and having a second annular structure, surrounding the drain doping region, with a preset distance between an outer boundary of the field oxide layer and the shallow trench isolation structure, the preset distance being greater than 0; a gate polycrystal, disposed on the upper surface of the substrate and in a third annular structure, surrounding the field oxide layer, wherein in the first direction, the gate polycrystal extends from above the source doping region to above the field oxide layer, and in the second direction, the gate polycrystal extends from above the shallow trench isolation structure to above the field oxide layer, and a gate oxide layer is further provided between the gate polycrystal and the substrate; a drift region having a second conductivity type, disposed in the substrate and surrounding the drain doping region, and spaced apart from the source doping region, wherein the drift region further extends along the second direction to below the shallow trench isolation structure; The extension area of ​​the active area in the second direction is a device voltage-resistant area, and the area between the drain doping area and the source doping area in the active area in the first direction is a device working and voltage-resistant area.

2. The semiconductor device according to claim 1, wherein A length dimension of the field oxide layer in the first direction is smaller than a length dimension of the field oxide layer in the second direction.

3. The semiconductor device according to claim 1, wherein The length dimension of the gate polycrystal in the first direction is smaller than the length dimension of the gate polycrystal in the second direction.

4. The semiconductor device according to claim 1, wherein In the second direction, a preset distance between an outer boundary of the field oxide layer and the shallow trench isolation structure is 0.5 um to 0.8 um.

5. The semiconductor device according to claim 1, wherein The second annular structure and the third annular structure are both octagonal annular structures. The semiconductor device according to claim 1 , wherein: The outer contour of the drift region is an octagon in a plane.

7. The semiconductor device according to claim 1, wherein The geometric center of the first annular structure on the horizontal plane, the geometric center of the second annular structure on the horizontal plane, the geometric center of the third annular structure on the horizontal plane, and the geometric center of the outer contour of the drift region on the horizontal plane coincide with each other.

8. The semiconductor device according to claim 1, wherein The field oxide layer is a silicon local oxidation field oxide layer.

9. The semiconductor device according to claim 1, wherein It also includes a metal field plate, which is arranged across the gate polycrystal and the field oxide layer, and a dielectric layer is provided between the metal field plate and the gate polycrystal, and between the metal field plate and the field oxide layer.

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