A solar cell structure with passivated contact grid lines and a method for preparing the same

Abstract

The present invention relates to a solar cell structure with a passivated contact grid line and a preparation method thereof, wherein the solar cell structure with a passivated contact grid line comprises: a p-type silicon base layer; a front electrode, arranged in a grid line region on the upper surface of the p-type silicon base layer; a passivation tunneling structure layer, arranged between the p-type silicon base layer and the front electrode, the passivation tunneling structure layer comprising a silicon oxide tunneling layer and a doped polysilicon layer stacked in sequence from bottom to top; and a front cell structure, comprising: an n++ diffusion layer, the n++ diffusion layer is stacked on the p-type silicon base layer and located in a non-grid line region on the upper surface of the p-type silicon base layer. The above-mentioned arrangement can solve the problems of the difficulty of the current poly-finger technology preparation process and the poor tunneling contact effect of the poly-finger structure, which leads to poor cell performance.

Description

Technical Field

[0001] The invention relates to the technical field of solar cells, and in particular to a solar cell structure with a passivated contact grid line and a preparation method thereof. Background Art

[0002] The conversion efficiency of PERC cells in the laboratory has reached more than 24%, and in actual mass production, its conversion efficiency is constantly approaching 23%. To further improve the conversion efficiency of cells, it is necessary to solve the problem of high recombination rate in the front metallization area of ​​the cell.

[0003] Generally speaking, passivation contact technology is adopted in the metallization area on the front of PERC cells to form poly-finger technology to significantly reduce the bottleneck problem of high composite current in the metallization area of ​​PERC cells.

[0004] However, from the perspective of the preparation process, all the current poly-finger technology preparation processes are extremely difficult, and there are process steps with low process yields such as mask back etching in the preparation process. For example, in general, after the passivation tunneling layer is deposited on the entire surface, a gate line pattern mask is formed by waxing and other means, and the unnecessary passivation tunneling layer is etched away to finally form a poly-finger structure. At the same time, the preparation process of the passivation tunneling layer is: first prepare a silicon oxide / intrinsic polysilicon layer, and then diffuse and dope the polysilicon layer in a diffusion furnace. The above process is relatively complicated.

[0005] In addition, from the perspective of battery structure, in order to form a good tunneling contact surface poly-finger, the n++ emitter formed by diffusion near the silicon substrate surface on both sides of the silicon oxide and the deposited polysilicon layer must form a significant difference in phosphorus doping concentration gradient, so that a good tunneling effect can be achieved. However, the current diffusion technology level for preparing n++ emitters in the industry is low, and it is difficult to form 1E20atom / cm 3 The surface doping concentration is below 100, and the saturation doping concentration of the polysilicon layer can only reach 1E21atom / cm 3 , so the difference in doping concentration gradient is small, the battery cannot form a good tunneling contact effect, the series resistance of the battery is too large, and the corresponding battery filling factor is worse.

[0006] Therefore, the conversion efficiency of PERC cells made by poly-finger technology is difficult to exceed that of PERC cells made by directly using silver grid contact on the front side. At the same time, the process difficulty is greatly increased and it is not feasible for mass production. Therefore, it is urgent to improve the existing passivation contact technology to improve the performance of PERC cells. Summary of the invention

[0007] In order to solve the above technical problems, the purpose of the present invention is to provide a solar cell structure with passivated contact grid lines and a preparation method thereof, so as to solve the problem that the current poly-finger technology preparation process is difficult and the tunneling contact effect of the poly-finger structure is poor, resulting in poor battery performance.

[0008] In order to achieve one of the above-mentioned purposes of the invention, an embodiment of the present invention provides a solar cell structure with a passivated contact grid line, comprising:

[0009] p-type silicon base layer;

[0010] A front electrode, disposed in a gate line region on the upper surface of the p-type silicon substrate layer;

[0011] A passivation tunneling structure layer is disposed between the p-type silicon base layer and the front electrode, wherein the passivation tunneling structure layer comprises a silicon oxide tunneling layer and a doped polysilicon layer stacked in sequence from bottom to top;

[0012] And a front battery structure, comprising: an n++ diffusion layer, wherein the n++ diffusion layer is stacked and arranged on the p-type silicon base layer and is located in a non-gate line area on the upper surface of the p-type silicon base layer.

[0013] Compared with the prior art, the beneficial effect of the above technical solution is that: a p-type silicon base layer and a front electrode are provided in the solar cell structure, the front electrode is provided on the p-type silicon base layer, and a passivation tunneling structure layer is provided between the two, and the passivation tunneling structure layer includes a silicon oxide tunneling layer and a doped polysilicon layer stacked from bottom to top; in addition, an n++ diffusion layer is stacked in other areas on the upper surface of the p-type silicon base layer, and the n++ diffusion layer is used to form a pn junction emission area on the front side of the solar cell structure; therefore, the passivation tunneling structure layer below the front electrode adopts a polysilicon / silicon oxide structure, and the silicon base below the passivation tunneling structure layer is not specially doped, so that the battery structure can be easily and better tunneled.

[0014] As a further improvement of an embodiment of the present invention, the front battery structure is further provided with a front anti-reflection film layer, and the front anti-reflection film layer is stacked and arranged on the upper surface of the n++ diffusion layer.

[0015] As a further improvement of one embodiment of the present invention, the solar cell structure further includes a back aluminum oxide silicon nitride stacked film, which is disposed on the lower surface of the p-type silicon base layer.

[0016] An embodiment of the present invention further provides a method for preparing a solar cell structure with a passivated contact grid line, comprising the steps of:

[0017] Step A: texturing a p-type silicon wafer to form a p-type silicon base layer;

[0018] Step B: preparing a silicon oxide layer in the gate line region on the upper surface of the p-type silicon base layer to form a silicon oxide tunneling layer;

[0019] Step C: depositing an amorphous silicon layer on the silicon oxide tunneling layer by using a mask PECVD method;

[0020] Step D: performing phosphorus diffusion on the front side of the solar cell structure in a diffusion furnace, so that an n++ diffusion layer is formed in the non-gate line region on the upper surface of the p-type silicon substrate layer, and the diffusion square resistance of the n++ diffusion layer is 100 to 220 ohms;

[0021] At the same time, the deposited amorphous silicon layer is partially crystallized to form a polycrystalline silicon layer, and further doped to form a doped polycrystalline silicon layer;

[0022] Step K: Printing and sintering are performed on the front side of the solar cell structure to form grid lines and front electrodes.

[0023] Compared with the prior art, the beneficial effects of the above technical solution are: first, a p-type silicon base layer is formed by texturing, and a silicon oxide tunneling layer is prepared in the gate line area on the upper surface of the p-type silicon base layer; then, deposition is performed on the silicon oxide tunneling layer by mask-based PECVD, and the polysilicon layer is doped and crystallized in the subsequent phosphorus diffusion process to form a doped polysilicon layer. At the same time, phosphorus diffusion causes other areas on the upper surface of the p-type silicon base layer to form an n++ diffusion layer, which is used to constitute the pn junction emission area on the front side of the solar cell structure; finally, a front electrode is formed by printing and sintering to form a passivated contact gate line structure; compared with the existing process technology, the above arrangement makes the overall process simple and convenient for industrial mass production.

[0024] As a further improvement of an embodiment of the present invention, step C specifically includes:

[0025] Covering the solar cell structure with a mask plate, and depositing the amorphous silicon layer by mask PECVD;

[0026] Among them, the opening pattern of the mask plate is consistent with the gate line pattern, the opening width is 10-150μm, and the distance between the mask plate and the p-type silicon base layer is no more than 2cm; the power of the deposition process is 1500-3000W, the deposition temperature is 200-500℃, and the deposition thickness is 20-200nm.

[0027] As a further improvement of one embodiment of the present invention, the method for preparing the silicon oxide layer in step B is one of the following:

[0028] Method a: thermal oxidation method, wherein the oxidation temperature is ≤900°C and the time is ≤20min;

[0029] Method b: nitric acid oxidation method, wherein the parameters are set as: 68wt% HNO3, solution temperature 80°C, oxidation time 10min;

[0030] Method c: in-situ oxidation deposition in PECVD, wherein the temperature is 400-700°C and the time is ≤60min.

[0031] As a further improvement of an embodiment of the present invention, after step D, the method further includes:

[0032] Step I: depositing silicon nitride on the front side of the solar cell structure by PECVD to form a front anti-reflection film layer.

[0033] As a further improvement of an embodiment of the present invention, between step D and step I, the method further includes:

[0034] Step E: etching and polishing the back side of the solar cell structure;

[0035] Step F: thermally oxidizing the front side of the solar cell structure;

[0036] Step G: depositing aluminum oxide on the back side of the solar cell structure;

[0037] Step H: After the aluminum oxide deposition is completed, silicon nitride is deposited on the back side of the solar cell structure to form a back side aluminum oxide silicon nitride stacked film.

[0038] As a further improvement of an embodiment of the present invention, after step I, the method further includes:

[0039] Step J: performing laser film opening on the back side of the solar cell structure, and performing partial laser ablation on the back side aluminum oxide silicon nitride laminate film.

[0040] As a further improvement of an embodiment of the present invention, step K specifically includes:

[0041] Step K1: preparing electrodes on the front and / or back side of the solar cell structure;

[0042] Step K2: using a chain sintering furnace to form a metallized contact by sintering to form a front electrode and / or a back electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a schematic structural diagram of a solar cell structure in one embodiment of the present invention;

[0045] Figure 2 , Figure 3 It is a process flow diagram of a method for preparing a solar cell structure in one embodiment of the present invention.

[0046] The reference numerals in the accompanying drawings are as follows:

[0047] Front electrode 1, front anti-reflection film layer 2, doped polysilicon layer 3, silicon oxide tunneling layer 4, n++ diffusion layer 5, p-type silicon base layer 6. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described implementation methods are only part of the implementation methods of the present invention, not all implementation methods. Based on the implementation methods of the present invention, all other implementation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0050] In the prior art, PERC cells with front passivated contacts have the following problems:

[0051] First, it is extremely difficult to form a passivation contact layer in the metallized gate line area, which requires a combination of masking, etching and other processes. At the same time, the front gate line needs to be printed on this passivation contact layer in the later stage. Therefore, there are high requirements for the graphic accuracy of the passivation contact layer, which is difficult and costly.

[0052] Second, it is impossible to form an effective doping concentration gradient difference, the tunneling contact effect is poor, the battery series resistance increases, and the battery fill factor decreases. The actual conversion efficiency of the battery cannot significantly surpass the existing PERC battery structure, and it does not have the advantage of improving conversion efficiency.

[0053] Third, the front silver paste cannot burn through the polysilicon layer in the passivation contact layer, otherwise it will easily cause battery leakage and reduce the battery open circuit voltage. Therefore, it is necessary to develop and use a front silver paste material for solar cells that is different from the current mass production. It can be seen that the mass production environment or mass production preparation is not mature.

[0054] like Figure 1As shown, based on the problems in the prior art, an embodiment of the present invention provides a solar cell structure with a passivated contact grid line, comprising:

[0055] p-type silicon base layer 6;

[0056] The front electrode 1 is provided in the gate line region on the upper surface of the p-type silicon base layer 6;

[0057] The passivation tunneling structure layer is disposed between the p-type silicon base layer 6 and the front electrode 1, and the passivation tunneling structure layer includes a silicon oxide tunneling layer 4 and a doped polysilicon layer 3 stacked in sequence from bottom to top;

[0058] The front battery structure includes an n++ diffusion layer 5 , which is stacked on a p-type silicon base layer 6 and located in a non-gate line area on the upper surface of the p-type silicon base layer 6 .

[0059] Specifically, a p-type silicon base layer 6 and a front electrode 1 are provided in the solar cell structure. The front electrode 1 is provided on the p-type silicon base layer 6, and a passivation tunneling structure layer is provided between the two. The passivation tunneling structure layer includes a silicon oxide tunneling layer 4 and a doped polysilicon layer 3 stacked from bottom to top. In addition, an n++ diffusion layer 5 is stacked in other areas on the upper surface of the p-type silicon base layer 6. The n++ diffusion layer 5 is used to constitute a pn junction emission region on the front side of the solar cell structure. Therefore, the passivation tunneling structure layer below the front electrode 1 adopts a polysilicon / silicon oxide structure, and the silicon base below the passivation tunneling structure layer is not specially doped, so that the battery structure can be easily and better tunneled.

[0060] In the actual structure, polysilicon / silicon oxide is located under the metal gate line, and there is no special doping under the silicon oxide; the front metal electrode is set as a conductive layer such as a silver layer; the thickness of the doped polysilicon layer 3 is 20 to 200nm; the thickness of the silicon oxide tunneling layer 4 is ≤1.5nm; the doping element of the n++ diffusion layer 5 is phosphorus, and the square resistance is 100 to 220Ω.

[0061] In the actual process, when depositing the passivation contact layer, PECVD mask deposition can be used, and the polysilicon layer can be doped and crystallized in the subsequent diffusion process. The overall process is simple and can be easily mass-produced.

[0062] Furthermore, the front battery structure is further provided with a front anti-reflection film layer 2 , and the front anti-reflection film layer 2 is stacked and arranged on the upper surface of the n++ diffusion layer 5 .

[0063] In the actual structure, the n++ diffusion layer 5 is also covered with a front anti-reflection film layer 2, and the anti-reflection film layer may be composed of one or more of silicon oxide, silicon nitride, silicon oxynitride, and MgF.

[0064] Furthermore, the solar cell structure also includes a back aluminum oxide silicon nitride stacked film, which is disposed on the lower surface of the p-type silicon base layer 6 .

[0065] In the actual structure, the lower surface of the p-type silicon base layer 6 can also form a back aluminum oxide silicon nitride stacked film by deposition to protect the back surface for subsequent processing.

[0066] The embodiment of the present invention further provides a method for preparing a solar cell structure with a passivated contact grid line, comprising the steps of:

[0067] Step A: texturing the p-type silicon wafer to form a p-type silicon base layer 6;

[0068] Step B: preparing a silicon oxide layer in the gate line region on the upper surface of the p-type silicon base layer 6 to form a silicon oxide tunneling layer 4;

[0069] Step C: depositing an amorphous silicon layer on the silicon oxide tunneling layer 4 by mask PECVD;

[0070] Step D: performing phosphorus diffusion on the front side of the solar cell structure in a diffusion furnace, so that an n++ diffusion layer 5 is formed in the non-gate line region on the upper surface of the p-type silicon substrate layer 6, and the diffusion square resistance of the n++ diffusion layer 5 is 100 to 220 ohms;

[0071] At the same time, the deposited amorphous silicon layer is partially crystallized to form a polysilicon layer, and further doped to form a doped polysilicon layer 3;

[0072] Step K: Printing and sintering are performed on the front side of the solar cell structure to form grid lines, thereby forming a front electrode 1 .

[0073] Specifically, a p-type silicon base layer 6 is first formed by texturing, and a silicon oxide tunneling layer 4 is prepared in the gate line area on the upper surface of the p-type silicon base layer 6; then deposition is performed on the silicon oxide tunneling layer 4 by masked PECVD, and the polysilicon layer is doped and crystallized in a subsequent phosphorus diffusion process, thereby forming a doped polysilicon layer 3. At the same time, phosphorus diffusion causes other areas on the upper surface of the p-type silicon base layer 6 to form an n++ diffusion layer 5, which is used to constitute a pn junction emission area on the front side of the solar cell structure; finally, a front electrode 1 is formed by printing and sintering to form a passivated contact gate line structure; compared with the existing process technology, the above-mentioned arrangement makes the overall process simple and convenient for industrial mass production.

[0074] like Figures 2 to 3 As shown, in the actual process, the detailed steps of process implementation are as follows:

[0075] →① Velvet making;

[0076] →② Mask PECVD deposition of amorphous silicon layer; wherein the mask opening width is 10-150μm, the opening shape is consistent with the front gate line pattern, and the distance between the mask and the silicon wafer is ≤2cm; the silicon oxide layer under the doped polysilicon layer 3 can be prepared by wet oxidation, thermal oxidation and other methods, or it can be prepared in situ before depositing the polysilicon layer in the PECVD equipment;

[0077] →③ Phosphorus diffusion, where the diffusion resistance is 100-220Ω; in this process, the amorphous silicon layer deposited by PERC will partially crystallize to form a polysilicon layer and further doped;

[0078] →④PECVD method to deposit the front silicon nitride anti-reflection layer;

[0079] →⑤ Printing and sintering to form grid lines;

[0080] In addition, when preparing PERC cells, back etching and edge isolation, thermal oxidation, back aluminum oxide silicon nitride laminated film deposition and other processing processes are generally added in sequence between process step ③ and process step ④, and a back laser grooving process is added after process step ④.

[0081] Further, step C specifically includes:

[0082] A mask plate is covered on the solar cell structure, and an amorphous silicon layer is deposited by mask-based PECVD;

[0083] Among them, the opening pattern of the mask plate is consistent with the gate line pattern, the opening width is 10-150μm, and the distance between the mask plate and the p-type silicon base layer 6 is not more than 2cm; the power of the deposition process is 1500-3000W, the deposition temperature is 200-500℃, and the deposition thickness is 20-200nm.

[0084] Therefore, the PECVD mask graphic deposition process is adopted, which is simple and convenient for industrial mass production.

[0085] Furthermore, the method for preparing the silicon oxide layer in step B is one of the following:

[0086] Method a: thermal oxidation method, wherein the oxidation temperature is ≤900°C and the time is ≤20min;

[0087] Method b: nitric acid oxidation method, wherein the parameters are set as: 68wt% HNO3, solution temperature 80°C, oxidation time 10min;

[0088] Method c: in-situ oxidation deposition in PECVD, wherein the temperature is 400-700°C and the time is ≤60min.

[0089] In this way, the preparation method can be selected according to the actual situation to facilitate process manufacturing.

[0090] Further, after step D, the method further comprises:

[0091] Step I: Silicon nitride is deposited on the front side of the solar cell structure by PECVD to form a front anti-reflection film layer 2.

[0092] Furthermore, between step D and step I, the method further comprises:

[0093] Step E: etching and polishing the back side of the solar cell structure;

[0094] Step F: thermally oxidizing the front side of the solar cell structure;

[0095] Step G: Depositing aluminum oxide on the back side of the solar cell structure;

[0096] Step H: After the aluminum oxide deposition is completed, silicon nitride is deposited on the back side of the solar cell structure to form a back side aluminum oxide silicon nitride stacked film.

[0097] Further, after step I, the method further comprises:

[0098] Step J: Laser film opening is performed on the back side of the solar cell structure, and a partial laser ablation is performed on the back side aluminum oxide silicon nitride laminate film.

[0099] This makes subsequent processing easier.

[0100] Furthermore, step K specifically includes:

[0101] Step K1: preparing electrodes on the front and / or back of the solar cell structure;

[0102] Step K2: using a chain sintering furnace to form a metallized contact by sintering to form a front electrode 1 and / or a back electrode.

[0103] In the embodiment provided by the present invention, the solar cell structure is a PERC cell, in which a passivation contact grid structure is provided. The overall preparation process of the solar cell structure is detailed in the following steps:

[0104] Step A, texturing: provide a p-type silicon wafer, and use KOH solution to texturize the silicon wafer to prepare a velvet structure with a pyramid base side length of 1 to 10 μm.

[0105] Step B: Preparation of silicon oxide layer:

[0106] Method a: thermal oxidation (oxidation temperature ≤ 900 ° C, time ≤ 20 min),

[0107] Method b: nitric acid oxidation (68wt% HNO3, solution temperature 80°C, oxidation time 10min),

[0108] Method c: In-situ oxidation deposition in PECVD (temperature 400-700°C, ≤60min)

[0109] Step C, mask PECVD deposition of amorphous silicon layer: Cover the surface of the silicon wafer with a mask plate (the opening pattern of the mask plate is consistent with the front gate line pattern, the opening width is 10-150 μm, and the distance between the mask plate and the silicon wafer is ≤2 cm), the power of the deposition process is 1500-3000 W, the deposition temperature is 200-500° C., and the deposition thickness is 20-200 nm;

[0110] Step D, front diffusion: Phosphorus diffusion is performed in a diffusion furnace to form an n++ layer, forming a front pn junction emitter region, and the diffusion square resistance is 100 to 220 ohms.

[0111] Step E, back side etching and polishing: Perform HNO3+HF acid polishing or KOH, NaOH alkaline polishing on the back side in an etcher.

[0112] Step F, front thermal oxidation: thermal oxidation is performed in an oxidation furnace to form a silicon oxide layer on the front side;

[0113] Step G, back aluminum oxide deposition: using PECVD to deposit aluminum oxide with a thickness of 5 to 20 nm, or using ALD to deposit aluminum oxide with a thickness of 1 to 10 nm;

[0114] Step H, back side silicon nitride deposition: using PECVD to deposit a 50-200 nm thick silicon nitride back side protective layer;

[0115] Step I, front silicon nitride deposition: using PECVD to deposit a 50-100 nm thick silicon nitride front protective layer;

[0116] Step J: Back laser film opening: Use 532nm laser to partially laser ablate the back aluminum oxide / silicon nitride stack.

[0117] Step K1, preparation of front and back electrodes: preparing the front and back electrodes by screen printing, evaporation, sputtering, etc.;

[0118] Step K2, sintering: using a chain sintering furnace to sinter to form metallized contacts.

[0119] In summary, the embodiments of the present invention provide a new low-cost solar cell structure and a preparation method thereof. The cell structure is provided with a passivation contact grid line structure, the overall structure is simple, the whole line process is simple, and it is convenient for industrial mass production.

[0120] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0121] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell structure with a passivated contact grid line, characterized in that: The following steps are involved: Step A: texturing a p-type silicon wafer to form a p-type silicon base layer; Step B: preparing a silicon oxide layer in the gate line region on the upper surface of the p-type silicon base layer to form a silicon oxide tunneling layer; Step C: depositing an amorphous silicon layer on the silicon oxide tunneling layer by mask PECVD; wherein step C specifically includes: Covering the solar cell structure with a mask plate, and depositing the amorphous silicon layer by mask PECVD; The opening pattern of the mask plate is consistent with the gate line pattern, the opening width is 10-150 μm, and the distance between the mask plate and the p-type silicon base layer is no more than 2 cm; the power of the deposition process is 1500-3000 W, the deposition temperature is 200-500° C., and the deposition thickness is 20-200 nm; Step D: performing phosphorus diffusion on the front side of the solar cell structure in a diffusion furnace, so that an n++ diffusion layer is formed in the non-gate line region on the upper surface of the p-type silicon substrate layer, and the diffusion square resistance of the n++ diffusion layer is 100 to 220 ohms; At the same time, the deposited amorphous silicon layer is partially crystallized to form a polycrystalline silicon layer, and further doped to form a doped polycrystalline silicon layer; Step E: etching and polishing the back side of the solar cell structure; Step F: thermally oxidizing the front side of the solar cell structure; Step G: depositing aluminum oxide on the back side of the solar cell structure; Step H: after the aluminum oxide deposition is completed, depositing silicon nitride on the back side of the solar cell structure to form a back aluminum oxide silicon nitride laminated film; Step I: depositing silicon nitride on the front side of the solar cell structure by a PECVD method to form a front anti-reflection film layer; Step K: Printing and sintering are performed on the front side of the solar cell structure to form grid lines and front electrodes; Step K specifically includes: Step K1: preparing electrodes on the front and / or back side of the solar cell structure; Step K2: using a chain sintering furnace to form a metallized contact by sintering to form a front electrode and / or a back electrode.

2. The method for preparing a solar cell structure with passivated contact lines according to claim 1, characterized in that: The method for preparing the silicon oxide layer in step B is one of the following: Method a: thermal oxidation method, wherein the oxidation temperature is ≤900°C and the time is ≤20min; Method b: nitric acid oxidation method, wherein the parameters are set as: 68wt% HNO3, solution temperature 80°C, oxidation time 10min; Method c: in-situ oxidation deposition in PECVD, wherein the temperature is 400-700°C and the time is ≤60min.

3. The method for preparing a solar cell structure with passivated contact lines according to claim 1, characterized in that: After step I, the method further comprises: Step J: performing laser film opening on the back side of the solar cell structure, and performing partial laser ablation on the back side aluminum oxide silicon nitride laminate film.

4. A solar cell structure with passivated contact grid lines, characterized in that: Prepared according to any one of claims 1 to 3, the solar cell structure comprises: p-type silicon base layer; A front electrode, disposed in a gate line region on the upper surface of the p-type silicon substrate layer; A passivation tunneling structure layer is disposed between the p-type silicon base layer and the front electrode, wherein the passivation tunneling structure layer comprises a silicon oxide tunneling layer and a doped polysilicon layer stacked in sequence from bottom to top; and a front cell structure, comprising: an n++ diffusion layer, the n++ diffusion layer being stacked and arranged on the p-type silicon base layer and being located in a non-gate line region on the upper surface of the p-type silicon base layer; The front battery structure is further provided with a front anti-reflection film layer, and the front anti-reflection film layer is stacked and arranged on the upper surface of the n++ diffusion layer; The solar cell structure further comprises a back aluminum oxide silicon nitride stacked film, which is arranged on the lower surface of the p-type silicon base layer.

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