A dual-stream network radar data collector and a data collection method

Abstract

The present invention provides a dual-stream network radar data collector and a data collection method, including: an analog signal conversion circuit, a digital signal receiving circuit, an AD acquisition circuit, a main control circuit, and a network driver circuit; after the analog signal conversion circuit and the AD acquisition circuit, the analog video is converted into a parallel digital signal and enters the FPGA in the main control circuit; the digital signal receiving circuit receives the radar status signal and sends it to the FPGA processor; the FPGA processor analyzes the radar data and processes the data into a main stream and a sub-stream, and the processed data is stored in the DDR3; the ARM processor respectively compresses the dual-stream data in the DDR3, and then sends the dual-stream data to the external network through the gigabit network driver circuit. The dual-stream network radar data collector of the present invention can process a large amount of radar data preprocessing work, and the dual-stream function meets the control requirements of users in multiple scenarios and multiple terminals.

Description

Technical Field

[0001] The present invention relates to the technical field of radar signal processing, and particularly to a dual-stream network radar data collector and a data collection method. Background Art

[0002] Currently, in the domestic and foreign radar application fields, shore-based detection radars and marine navigation radars usually adopt magnetron radars or solid-state radars in the X-band and S-band. Since these radars have been deployed for a long time, most of the radar signals are transmitted from the antenna in analog signals. The interface standards are inconsistent, and a supporting radar processor is required for signal processing and analog-to-digital conversion, and a display control device is used for display. And radar manufacturers only configure one processing and display control device for a single set of radar.

[0003] With the popularization of mobile communication devices such as mobile phones and PADs, and the development of multi-functional applications of radars, for a single radar device, application scenarios such as coexistence of remote monitoring and station monitoring, coexistence of full-area monitoring and key-area monitoring, and multi-mobile-terminal monitoring have been successively proposed. Traditional radar devices can only be operated and displayed by a fixed station, and a large number of users hope to remotely display and independently control the data of a single radar device in the above application scenarios.

[0004] In the field of radar signal acquisition, there are three common forms of signal acquisition devices: one is the acquisition circuit self-developed by radar manufacturers, which is generally specially developed for the overall radar system of the manufacturer. The acquisition circuit and the display control circuit are jointly packaged in the radar processor. Its interface only adapts to the original display control device and generally does not have the ability of remote transmission; another signal acquisition device is a radar data acquisition card based on the PCI or PCIE bus. Its operation requires a computer host with a corresponding slot, which is not flexible, has poor reliability, and is not suitable for high-vibration and humid environments such as ships; the third is a radar data collector using a network interface, which can package and transmit radar video through the network, but this device generally only has data of a single stream and cannot achieve independent display and control of multiple streams, and cannot meet the increasingly extensive diversified information processing and display control requirements. Summary of the Invention

[0005] The present invention provides a dual-stream network radar data collector and a data collection method to solve the defects that existing radar data acquisition devices generally have unopened interfaces or can only process a single stream.

[0006] In a first aspect, the present invention provides a dual-stream network radar data collector, including:

[0007] An analog signal conversion circuit, a digital signal receiving circuit, an analog-to-digital conversion AD acquisition circuit, a main control circuit, and a network driving circuit. After the analog signal conversion circuit is connected to the AD acquisition circuit, they are input to the main control circuit in parallel with the digital signal receiving circuit, and the main control circuit is connected to the network driving circuit;

[0008] The analog signal conversion circuit is used to receive a radar analog video signal and convert and process the radar analog video signal to obtain an analog video conversion signal;

[0009] The AD acquisition circuit is used to convert the analog video conversion signal into a parallel digital video signal and transmit it to the main control circuit;

[0010] The digital signal receiving circuit is used to receive a radar digital control signal and convert and process the radar digital control signal to obtain a digital control conversion signal;

[0011] The main control circuit is used to obtain a main code stream and a sub-code stream based on the parallel digital video signal and the digital control conversion signal, and process the main code stream and the sub-code stream to obtain dual-stream radar data;

[0012] The network driving circuit is used to transmit the dual-stream radar data to the external network.

[0013] According to a dual-stream network radar data collector provided by the present invention, the analog signal conversion circuit includes an operational amplifier circuit. The operational amplifier circuit converts the radar analog video signal into a differential signal through a single-ended to differential ADC driver chip to obtain the analog video conversion signal.

[0014] According to a dual-stream network radar data collector provided by the present invention, the digital signal receiving circuit includes a 422 chip receiving circuit and an optocoupler isolation circuit. The 422 chip receiving circuit and the optocoupler isolation circuit receive the radar digital control signal in parallel;

[0015] The 422 chip receiving circuit is used to receive and process the 422 standard digital signal in the radar digital control signal and convert it into a preset voltage signal;

[0016] The optocoupler isolation circuit is used to receive and process the different voltage single-ended digital signals in the radar digital control signal and convert it into the preset voltage signal.

[0017] According to a dual-stream network radar data collector provided by the present invention, the main control circuit includes an FPGA dual-stream processor and an ARM dual-stream processor;

[0018] The FPGA dual-stream processor is used to perform dual-stream processing on the parallel digital video signal and the digital control conversion signal and then transmit them to the ARM dual-stream processor to obtain the dual-stream radar data.

[0019] According to a dual-stream network radar data collector provided by the present invention, the main control circuit further includes a DDR3 memory, and the DDR3 memory is used to store the dual-stream radar data output by the FPGA dual-stream processor.

[0020] According to a dual-stream network radar data collector provided by the present invention, the FPGA dual-stream processor includes a control instruction receiving module, an AD acquisition module, an azimuth calculation module, a main-stream data processing module, and a sub-stream data processing module;

[0021] The control instruction receiving module is used to receive radar data processing control instructions from the ARM dual-stream processor through the Advanced eXtensible Interface AXI4 bus;

[0022] The AD acquisition module is used to sample the effective radar video data based on a trigger signal and a sampling control instruction, and respectively output the main stream to the main-stream data processing module and output the sub-stream to the sub-stream data processing module;

[0023] The azimuth calculation module is used to receive a radar trigger signal, a radar azimuth signal, and a radar zero position signal.

[0024] According to a dual-stream network radar data collector provided by the present invention, the ARM dual-stream processor includes a memory reading module, a first data compression module, a second data compression module, and an instruction receiving module;

[0025] The memory reading module is used to respectively obtain the main stream and the sub-stream from the DDR3 memory;

[0026] The first data compression module is used to perform data compression on the main stream and send the compressed main stream to the external network through the network driver circuit;

[0027] The second data compression module is used to perform data compression on the sub-stream and send the compressed sub-stream to the external network through the network driver circuit;

[0028] The instruction receiving module is used to receive radar data processing control instructions from the external network and send the radar data processing control instructions to the FPGA dual-stream processor through the AXI4 bus.

[0029] In a second aspect, the present invention further provides a dual-stream network radar data acquisition method, including:

[0030] Receive the radar analog video signal, and obtain the parallel digital video signal through the analog signal conversion circuit and the AD acquisition circuit;

[0031] Receive the radar digital control signal, and obtain the digital control conversion signal through the digital signal receiving circuit;

[0032] Input the parallel digital signal and the digital control conversion signal into the main control circuit to obtain the main code stream and the sub-code stream, process the main code stream and the sub-code stream through the FPGA dual-code stream processor, and process the main code stream and the sub-code stream through the ARM dual-code stream processor to obtain the dual-code stream radar data;

[0033] Transmit the dual-code stream radar data to the external network through the network driving circuit.

[0034] According to a dual-code stream network radar data acquisition method provided by the present invention, the processing of the main code stream and the sub-code stream by the FPGA dual-code stream processor includes:

[0035] Receive the radar trigger signal, the radar azimuth signal and the radar zero position signal respectively through the azimuth calculation module;

[0036] The control instruction receiving module receives the radar data processing control instruction from the ARM dual-code stream processor through the AXI4 bus;

[0037] The AD acquisition module samples the radar video valid data according to the trigger signal and the sampling control instruction, and outputs the main code stream to the main code stream data processing module respectively, and outputs the sub-code stream to the sub-code stream data processing module;

[0038] The main code stream data processing module performs sector blanking, sampling point merging and azimuth angle merging processing on the main code stream, and the sub-code stream data processing module performs the same processing on the sub-code stream to obtain the dual-code stream radar data;

[0039] Transmit the dual-code stream radar data to the DDR3 memory for storage through the AXI4 bus.

[0040] According to a dual-code stream network radar data acquisition method provided by the present invention, the processing of the main code stream and the sub-code stream by the ARM dual-code stream processor includes:

[0041] Obtain the dual-code stream radar data from the DDR3 memory through the memory reading module;

[0042] The first data compression module compresses the main code stream in the dual-code stream radar data to obtain the compressed main code stream;

[0043] The second data compression module compresses the sub-stream in the dual-stream radar data to obtain a compressed sub-stream;

[0044] The compressed main stream and the compressed sub-stream are respectively sent to the external network through the network drive circuit;

[0045] Based on the Web-Socket technology, the radar data processing control instruction from the external network is received, and the radar data processing control instruction is sent to the FPGA dual-stream processor through the AXI4 bus.

[0046] The dual-stream network radar data collector and data collection method provided by the present invention realize the digital signal processing work of dual-stream through FPGA, compress the dual-stream data through the ARM processor, and at the same time, based on Web-Socket, users can control the network radar collector only by using a browser. The dual-stream function meets the control requirements of users in multiple scenarios and multiple terminals. The main control chip integrating FPGA and ARM can perform a large amount of radar data processing work, reducing the requirements of users for the software and hardware performance of terminal devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 It is a schematic diagram of the overall structure of the dual-stream network radar data collector provided by the present invention;

[0049] Figure 2 It is a schematic diagram of the hardware structure of the dual-stream network radar data collector provided by the present invention;

[0050] Figure 3 It is a schematic diagram of the structure of the FPGA dual-stream processor provided by the present invention;

[0051] Figure 4 It is a schematic diagram of the structure of the ARM dual-stream processor provided by the present invention;

[0052] Figure 5 It is a schematic diagram of the flow of the dual-stream network radar data collection method provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will describe the technical solutions in the present invention clearly and completely in conjunction with the accompanying drawings in the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts fall within the protection scope of the present invention.

[0054] In view of the limitations of radar data collectors in the prior art, the present invention proposes a new dual-stream network radar data collector, which has good interface versatility, supports multiple radars, supports web control, can implement the dual-stream function, and is easy to carry.

[0055] Figure 1 is the overall structural schematic diagram of the dual-stream network radar data collector provided by the present invention, as Figure 1 shown, including:

[0056] An analog signal conversion circuit, a digital signal receiving circuit, an analog-to-digital conversion AD acquisition circuit, a main control circuit, and a network driving circuit. After the analog signal conversion circuit is connected to the AD acquisition circuit, it is input to the main control circuit in parallel with the digital signal receiving circuit, and the main control circuit is connected to the network driving circuit;

[0057] The analog signal conversion circuit is used to receive the radar analog video signal and convert and process the radar analog video signal to obtain an analog video conversion signal;

[0058] The AD acquisition circuit is used to convert the analog video conversion signal into a parallel digital video signal and transmit it to the main control circuit;

[0059] The digital signal receiving circuit is used to receive the radar digital control signal and convert and process the radar digital control signal to obtain a digital control conversion signal;

[0060] The main control circuit is used to obtain the main stream and the sub-stream based on the parallel digital signal and the digital control conversion signal, and process the main stream and the sub-stream to obtain dual-stream radar data;

[0061] The network driving circuit is used to transmit the dual-stream radar data to the external network.

[0062] Specifically, the dual-stream network radar data collector proposed by the present invention includes a set of hardware circuits, a set of FPGA programs, a set of ARM programs, and a set of mechanical casings. Among them, the FPGA program and the ARM program run in the main control circuit of the hardware circuit, and the main control circuit integrates the ZYNQ7Z020 chip of the FPGA and the ARM processor.

[0063] The hardware circuit includes an analog signal conversion circuit, a digital signal receiving circuit, an AD acquisition circuit, a main control circuit, and a network interface driver circuit. Both the analog video signal and the digital signal are introduced through a standard DB15 interface. The analog signal conversion circuit processes the analog video signals with different polarities, and then, after passing through the AD acquisition circuit, converts them into parallel digital signals and enters the FPGA side of the main control circuit. The digital signal receiving circuit receives and converts the radar azimuth, trigger, and other parameter signals and also enters the FPGA side of the main control circuit. The FPGA divides the radar signals into a main code stream and a sub-code stream, and after performing data processing such as sector blanking, sampling value merging, and azimuth angle merging, transfers the data to the ARM processor side of the main control circuit. The ARM processor side is connected to a gigabit network driver circuit.

[0064] In the present invention, the digital signal processing work of dual code streams is implemented through the FPGA, and the dual code stream data is compressed by the ARM processor. The main control chip integrating the FPGA and the ARM can perform a large amount of radar data processing work, reducing the requirements of users for the software and hardware performance of the terminal device.

[0065] Based on the above embodiment, the analog signal conversion circuit includes an operational amplifier circuit. The operational amplifier circuit converts the radar analog video signal into a differential signal through a single-ended to differential ADC driver chip to obtain the analog video conversion signal.

[0066] Specifically, as Figure 2 shown, the branch circuit that receives the radar analog video signal is an operational amplifier circuit. To achieve the acquisition of radar analog videos with different polarities and ensure the signal sampling rate, the operational amplifier circuit is used to convert the voltage range of the input signal. A single-ended to differential ADC driver chip is adopted to first convert the analog signal into a differential signal to obtain the analog video conversion signal.

[0067] In the present invention, at the initial stage of the input of the radar analog video signal, an operational amplifier circuit is adopted for video data acquisition and signal voltage range conversion, converting the analog video signal into a differential signal for subsequent analog-to-digital conversion.

[0068] The analog-to-digital conversion uses the analog-to-digital conversion chip AD9628 of AD Company. It can provide 12-bit precision at a data rate of 125 MSPS and ensure no missing codes within the entire operating temperature range. This chip receives the differential analog video signal and converts it into a 12-bit parallel differential digital video signal, which is sent to the FPGA processor.

[0069] Based on any of the above embodiments, the digital signal receiving circuit includes a 422 chip receiving circuit and an optocoupler isolation circuit. The 422 chip receiving circuit and the optocoupler isolation circuit receive the radar digital control signal in parallel;

[0070] The 422 chip receiving circuit is used to receive and process the 422 standard digital signal in the radar digital control signal, and convert it into a preset voltage signal;

[0071] The optocoupler isolation circuit is used to receive and process different voltage single-ended digital signals in the radar digital control signal, and convert it into the preset voltage signal.

[0072] Specifically, as Figure 2 shown, relative to the analog signal conversion circuit, another branch circuit is the digital signal receiving circuit, which simultaneously uses the 422 chip receiving circuit and the optocoupler isolation circuit in parallel for processing.

[0073] The 422 chip receiving circuit is used to receive and process the 422 standard digital signal in the radar digital control signal. The single-ended digital signals with different voltages pass through the optocoupler isolation chip and are all converted into a preset voltage signal, such as a standard 3.3V voltage signal, and then input into the FPGA of the main control circuit.

[0074] The 422 chip receiving circuit here uses an RS422 chip, which is a low-voltage high-speed four-channel differential line receiving chip and can simultaneously convert four 422 differential signals into single-ended 3.3V signals.

[0075] The present invention uses a digital signal receiving circuit to process the radar digital control signal, obtains a unified standard voltage digital signal, and realizes the control of the main control circuit.

[0076] Based on any of the above embodiments, the main control circuit includes an FPGA dual-stream processor and an ARM dual-stream processor;

[0077] The FPGA dual-stream processor is used to perform dual-stream processing on the parallel digital signal and the digital control conversion signal and then transmit them to the ARM dual-stream processor to obtain the dual-stream radar data.

[0078] The main control circuit further includes a DDR3 memory, and the DDR3 memory is used to store the dual-stream radar data output by the FPGA dual-stream processor.

[0079] Specifically, as Figure 3 shown, the FPGA dual-stream processor simultaneously receives the radar video signal and the digital signal, and processes the data in two different processing modes according to the main stream control instruction and the sub-stream control instruction, including sector blanking, sampling point merging, azimuth angle merging, etc., and finally forms the dual-stream radar data and stores it in the DDR3 through the AXI4 bus.

[0080] The ARM dual-stream processor further reads the radar data in the DDR3, can process the main-stream and sub-stream data in different compression ways, and then sends the data out through the standard gigabit network interface. At the same time, the ARM program receives the radar data control instructions from external devices through Web-Socket.

[0081] It should be noted that AXI (Advanced eXtensible Interface) in the present invention is a bus protocol, and AXI4 is in the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. AXI4 includes three types of interfaces:

[0082] 1) AXI4: mainly for the needs of high-performance address mapping communication;

[0083] 2) AXI4-Lite: is a lightweight one, suitable for address mapping communication buses with relatively small throughput;

[0084] 3) AXI4-Stream: for high-speed stream data transmission.

[0085] By breaking through the limitations of traditional radar signal acquisition and radar display and control systems, the present invention combines and develops the functions of the two, and realizes dual-stream processing through the FPGA and ARM of the main control circuit.

[0086] Based on any of the above embodiments, the FPGA dual-stream processor includes a control instruction receiving module, an AD acquisition module, an azimuth calculation module, a main-stream data processing module, and a sub-stream data processing module;

[0087] The control instruction receiving module is used to receive the radar data processing control instructions from the ARM dual-stream processor through the Advanced eXtensible Interface AXI4 bus;

[0088] The AD acquisition module is used to sample the effective radar video data based on the trigger signal and the sampling control instruction, and respectively output the main-stream to the main-stream data processing module and output the sub-stream to the sub-stream data processing module;

[0089] The azimuth calculation module is used to receive the radar trigger signal, the radar azimuth signal, and the radar zero position signal.

[0090] Specifically, as Figure 3 shown, the FPGA dual-stream processor includes a control instruction receiving module, an AD acquisition module, an azimuth calculation module, a main-stream data processing module, and a sub-stream data processing module;

[0091] Among them, the control instruction receiving module receives the radar data processing control instruction sent from the ARM dual-stream processor through the AXI4 bus; the azimuth calculation module receives the radar trigger, azimuth, and zero position signals, and calculates the azimuth of the current radar trigger signal; the AD acquisition module samples the effective radar video data according to the control instructions sent by the above two modules, based on the trigger signal and the sampling control instruction, and then sends the effective data to the main-stream and sub-stream data processing modules respectively. The processing methods of the main-stream and sub-stream for the radar data are the same here, but the processing instructions received from the control instruction receiving module are different, and the two processing instructions can be set through the host computer.

[0092] In the present invention, the FPGA dual-stream processor of the main control circuit realizes the digital signal processing work of the dual-stream, overcoming the limitation that the traditional data collector can only process a single stream.

[0093] Based on any of the above embodiments, the ARM dual-stream processor includes a memory reading module, a first data compression module, a second data compression module, and an instruction receiving module;

[0094] The memory reading module is used to respectively obtain the main-stream and the sub-stream from the DDR3 memory;

[0095] The first data compression module is used to compress the data of the main-stream, and send the compressed main-stream to the external network through the network driving circuit;

[0096] The second data compression module is used to compress the data of the sub-stream, and send the compressed sub-stream to the external network through the network driving circuit;

[0097] The instruction receiving module is used to receive the radar data processing control instruction from the external network, and send the radar data processing control instruction to the FPGA dual-stream processor through the AXI4 bus.

[0098] Specifically, as Figure 4 shown, in the main control circuit, the ARM dual-stream processor connected to the FPGA dual-stream processor includes a memory reading module, a first data compression module, a second data compression module, and an instruction receiving module.

[0099] Among them, the memory reading module respectively reads the main-stream and the sub-stream from the DDR3 memory, the first data compression module compresses the data of the main-stream, the second data compression module compresses the data of the sub-stream, and after compression, both are sent to the external network through the network driving circuit by the TCP / IP protocol;

[0100] Meanwhile, receive the radar data processing control instructions sent from the external network through the network drive circuit, send them to the instruction receiving module based on WebSocket, and then send them to the FPGA dual-stream processor through the AXI4 bus.

[0101] The present invention realizes the compression processing of dual-stream data through the ARM dual-stream processor of the main control circuit.

[0102] Figure 5 It is a schematic flow chart of the dual-stream network radar data acquisition method provided by the present invention, as Figure 5 shown, including:

[0103] Step S1, receive the radar analog video signal, and obtain the parallel digital signal through the analog signal conversion circuit and the AD acquisition circuit;

[0104] Step S2, receive the radar digital control signal, and obtain the digital control conversion signal through the digital signal receiving circuit;

[0105] Step S3, input the parallel digital signal and the digital control conversion signal into the main control circuit to obtain the main stream and the sub-stream, process the main stream and the sub-stream through the FPGA dual-stream processor, and process the main stream and the sub-stream through the ARM dual-stream processor to obtain the dual-stream radar data;

[0106] Step S4, transmit the dual-stream radar data to the external network through the network drive circuit.

[0107] Specifically, as Figure 2 shown, the radar analog video signal is respectively received by the analog signal conversion circuit and the AD acquisition circuit, and the parallel digital signal is obtained after conversion processing;

[0108] The radar digital control signal is received by the digital signal receiving circuit, and the digital control conversion signal is obtained after conversion;

[0109] The parallel digital signal and the digital control conversion signal are simultaneously input into the main control circuit to obtain the main stream and the sub-stream, and the FPGA dual-stream processor and the ARM dual-stream processor therein process the main stream and the sub-stream to obtain the dual-stream radar data;

[0110] Finally, the obtained dual-stream radar data is sent to the external network by the network drive circuit.

[0111] The dual-stream network radar data acquisition method of the present invention, by processing a large amount of radar data preprocessing work, the dual-stream function meets the control requirements of users in multiple scenarios and multiple terminals.

[0112] Based on the above embodiments, the processing of the main stream and the sub-stream by the FPGA dual-stream processor includes:

[0113] The azimuth calculation module respectively receives the radar trigger signal, the radar azimuth signal and the radar zero signal, and calculates the azimuth of the current radar trigger signal;

[0114] The control instruction receiving module receives the radar data processing control instruction from the ARM dual-stream processor through the AXI4 bus;

[0115] The AD acquisition module samples the effective radar video data according to the trigger signal and the sampling control instruction, and outputs the main stream to the main stream data processing module and the sub-stream to the sub-stream data processing module respectively;

[0116] The main stream data processing module performs sector blanking, sampling point merging and azimuth merging processing on the main stream, and the sub-stream data processing module performs the same processing on the sub-stream to obtain dual-stream radar data;

[0117] The dual-stream radar data is transmitted to the DDR3 memory through the AXI4 bus for storage.

[0118] Specifically, as Figure 3 shown, the FPGA end program of the main control chip receives the radar trigger, azimuth, and zero signals through the azimuth calculation module and calculates the azimuth of the current radar trigger signal, receives the radar data processing control instruction from the ARM through the control instruction receiving module from the AXI4 bus, and the AD acquisition module samples the effective radar video data according to the trigger signal and the sampling control instruction, and then sends the effective data to the main stream and sub-stream data processing modules respectively.

[0119] The processing flows of the main stream and the sub-stream for the radar data are the same, but the processing instructions received from the control instruction receiving module are different, and the two processing instructions can be set through the upper computer. The data processing methods of the two streams include sector blanking, sampling point merging, azimuth merging, etc. The processed dual-stream data is written into the external DDR3 through the AXI4 bus respectively.

[0120] The present invention realizes the digital signal processing work of the dual stream through the FPGA dual-stream processor, overcoming the limitation that the traditional data collector can only process a single stream.

[0121] Based on any of the above embodiments, the ARM dual-stream processor includes a memory reading module, a first data compression module, a second data compression module and an instruction receiving module;

[0122] The memory reading module is used to respectively obtain the main stream and the sub-stream from the DDR3 memory;

[0123] The first data compression module is used to compress the main code stream and send the compressed main code stream to the external network through the network driver circuit;

[0124] The second data compression module is used to compress the sub-code stream and send the compressed sub-code stream to the external network through the network driver circuit;

[0125] The instruction receiving module is used to receive the radar data processing control instruction from the external network and send the radar data processing control instruction to the FPGA dual-code stream processor through the AXI4 bus.

[0126] Specifically, as Figure 4 shown, when the ARM program of the main control circuit finishes output storage in the FPGA, it reads the dual-code stream radar data from the DDR3 respectively and performs real-time data compression processing on it. Here, the first data compression module compresses the main code stream, and the second data compression module compresses the sub-code stream.

[0127] The compressed data is sent to the external network through the network driver circuit using the TCP / IP protocol. At the same time, the ARM program receives the radar data processing control instruction from the network based on the WebSocket protocol and sends the control instruction to the FPGA side of the main control chip through the AXI4 bus.

[0128] The present invention realizes the compression processing of the code stream data through the ARM dual-code stream processor of the main control circuit, which is convenient for transmission to the external network through the network driver circuit.

[0129] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0130] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-stream network radar data collector, characterized in that, Including: An analog signal conversion circuit, a digital signal receiving circuit, an analog-to-digital (AD) acquisition circuit, a main control circuit, and a network driving circuit. After the analog signal conversion circuit is connected to the AD acquisition circuit, they are input to the main control circuit in parallel with the digital signal receiving circuit, and the main control circuit is connected to the network driving circuit; The analog signal conversion circuit is used to receive a radar analog video signal and convert and process the radar analog video signal to obtain an analog video conversion signal; The AD acquisition circuit is used to convert the analog video conversion signal into a parallel digital video signal and transmit it to the main control circuit; The digital signal receiving circuit is used to receive a radar digital control signal and convert and process the radar digital control signal to obtain a digital control conversion signal; The main control circuit is used to obtain a main code stream and a sub-code stream based on the parallel digital video signal and the digital control conversion signal, and process the main code stream and the sub-code stream to obtain dual-stream radar data; The network driving circuit is used to transmit the dual-stream radar data to the external network; The main control circuit includes an FPGA dual-stream processor and an ARM dual-stream processor; The FPGA dual-stream processor includes a control instruction receiving module, an AD acquisition module, an azimuth calculation module, a main code stream data processing module, and a sub-code stream data processing module; The specific way to obtain the dual-stream radar data is as follows: The azimuth calculation module respectively receives a radar trigger signal, a radar azimuth signal, and a radar zero position signal, and calculates the azimuth angle of the current radar trigger signal; The control instruction receiving module receives radar data processing control instructions from the ARM dual-stream processor through the AXI4 bus; The AD acquisition module samples the valid radar video data according to the trigger signal and the sampling control instruction, and outputs the main code stream to the main code stream data processing module and the sub-code stream to the sub-code stream data processing module respectively; The main code stream data processing module performs sector blanking, sampling point merging, and azimuth angle merging processing on the main code stream, and the sub-code stream data processing module performs the same processing on the sub-code stream to obtain dual-stream radar data.

2. The dual-stream network radar data collector according to claim 1, characterized in that The analog signal conversion circuit includes an operational amplifier circuit, which converts the radar analog video signal into a differential signal through a single-ended to differential ADC driver chip to obtain the analog video conversion signal.

3. The dual-stream network radar data collector according to claim 1, wherein The digital signal receiving circuit includes a 422 chip receiving circuit and an opto-isolation circuit, and the 422 chip receiving circuit and the opto-isolation circuit receive the radar digital control signal in parallel; The 422 chip receiving circuit is used to receive and process the 422 standard digital signal in the radar digital control signal and convert it into a preset voltage signal; The opto-isolation circuit is used to receive and process the different voltage single-ended digital signals in the radar digital control signal and convert them into the preset voltage signal.

4. The dual-stream network radar data collector according to claim 1, characterized in that The FPGA dual-stream processor is used to perform dual-stream processing on the parallel digital video signal and the digital control conversion signal and then transmit them to the ARM dual-stream processor to obtain the dual-stream radar data.

5. The dual-stream network radar data collector according to claim 4, wherein The main control circuit further includes a DDR3 memory, which is used to store the dual-stream radar data output by the FPGA dual-stream processor.

6. The dual-stream network radar data collector according to claim 5, characterized in that, The control instruction receiving module is used to receive the radar data processing control instruction from the ARM dual-stream processor through the Advanced eXtensible Interface AXI4 bus; The AD acquisition module is used to sample the valid radar video data based on the trigger signal and the sampling control instruction, and respectively output the main stream to the main stream data processing module and output the sub-stream to the sub-stream data processing module; The azimuth calculation module is used to receive the radar trigger signal, the radar azimuth signal and the radar zero position signal, and calculate the azimuth angle of the current radar trigger signal.

7. The dual-stream network radar data collector according to claim 5, wherein The ARM dual-stream processor includes a memory reading module, a first data compression module, a second data compression module and an instruction receiving module; The memory reading module is used to respectively obtain the main stream and the sub-stream from the DDR3 memory; The first data compression module is used to compress the main stream, and send the compressed main stream to the external network through the network driving circuit; The second data compression module is used to compress the sub-stream, and send the compressed sub-stream to the external network through the network driving circuit; The instruction receiving module is used to receive the radar data processing control instruction from the external network, and send the radar data processing control instruction to the FPGA dual-stream processor through the AXI4 bus.

8. A dual-stream network radar data acquisition method, based on the dual-stream network radar data collector as described in any one of claims 1 to 7, characterized in that, It includes: Receiving the radar analog video signal, and obtaining the parallel digital video signal through the analog signal conversion circuit and the AD acquisition circuit; Receiving the radar digital control signal, and obtaining the digital control conversion signal through the digital signal receiving circuit; Inputting the parallel digital video signal and the digital control conversion signal into the main control circuit to obtain the main stream and the sub-stream, processing the main stream and the sub-stream through the FPGA dual-stream processor, and processing the main stream and the sub-stream through the ARM dual-stream processor to obtain the dual-stream radar data; Transmitting the dual-stream radar data to the external network through the network driving circuit.

9. The dual-stream network radar data acquisition method according to claim 8, wherein The processing of the main stream and the sub-stream by the FPGA dual-stream processor includes: Receiving the radar trigger signal, the radar azimuth signal and the radar zero position signal respectively through the azimuth calculation module, and calculating the azimuth angle of the current radar trigger signal; The control instruction receiving module receives the radar data processing control instruction from the ARM dual-stream processor through the AXI4 bus; The AD acquisition module samples the valid radar video data according to the trigger signal and the sampling control instruction, and respectively outputs the main stream to the main stream data processing module and outputs the sub-stream to the sub-stream data processing module; The main stream data processing module performs sector blanking, sampling point merging and azimuth angle merging processing on the main stream, and the sub-stream data processing module performs the same processing on the sub-stream to obtain the dual-stream radar data; Transmitting the dual-stream radar data to the DDR3 memory for storage through the AXI4 bus.

10. The dual-stream network radar data acquisition method according to claim 8, characterized in that The processing of the main stream and the sub-stream by the ARM dual-stream processor includes: Obtaining dual-stream radar data from the DDR3 memory through the memory reading module; The first data compression module compresses the main stream in the dual-stream radar data to obtain a compressed main stream; The second data compression module compresses the sub-stream in the dual-stream radar data to obtain a compressed sub-stream; Sending the compressed main stream and the compressed sub-stream to the external network through the network driver circuit respectively; Receiving the radar data processing control instruction from the external network and sending the radar data processing control instruction to the FPGA dual-stream processor through the AXI4 bus.

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