3D prestack reverse time migration method based on wave field reconstruction method and FPGA multi-board architecture

Abstract

The present invention discloses a three-dimensional pre-stack reverse time migration method using a wavefield reconstruction method based on an FPGA multi-board architecture, which relates to the field of computer technology. The method comprises the following steps: S1, preparing the calculation data required for forward modeling on the CPU side and programming the calculation data using a programming language; S2, the CPU interacting with a first FPGA board, and the first FPGA board outputting corresponding parameters to a second FPGA board and a third FPGA board; S3, the second FPGA board calculating the forward modeling wavefield and outputting an end signal to the first FPGA board after the calculation is completed; S4, the first FPGA board starting counting and simultaneously outputting a signal to the second FPGA board and the third FPGA board to initiate the calculation of the forward wavefield and the reverse wavefield; S5, the second FPGA board and the third FPGA board outputting the forward wavefield and the reverse wavefield at the same time to the first FPGA board; S6, the first FPGA board completing the calculation at all times and outputting the final imaging result to the CPU. The method reduces unnecessary data cache transmission, reduces the consumption of computing resources, and improves computing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a three-dimensional pre-stack reverse time migration method based on a FPGA multi-board architecture using a wave field reconstruction method. Background Art

[0002] In recent years, with the rapid development of computer technology and the substantial increase in computing power, solutions for the large computational workload and storage requirements of reverse time migration have been explored. Large-scale computing methods and architectures for industrial applications have also been investigated. Improvements in computing performance are primarily due to the increase in microprocessor operating frequency, with Moore's Law dominating the pace of information technology development. However, the resulting increase in operating frequency leads to increasingly prominent system overheating and rising system power consumption, which are increasingly constrained by physical factors. To ensure continued improvement in microprocessor chip performance and, more importantly, to reduce chip power consumption and complexity, mainstream commercial CPU designs have fully adopted multi-threaded, multi-core architectures. Dual-core and quad-core CPUs have become mainstream, and hexa-core and octa-core CPUs are now in mass production. The continued increase in processor cores (referred to as many-core processors) is expected to be a major feature of CPU technology development for some time to come. The rapid and efficient development of multi-core parallel computing programs is crucial to fully exploiting the performance of multi-core processor systems.

[0003] In addition to the traditional CPU evolution from single-core to multi-core (many-core) technology, several new technology paths are currently underway that may represent important future development directions for high-performance computing. One key area is reconfigurable computing technology based on FPGAs (field-programmable gate arrays). Both internationally and domestically, the most advanced petascale computing systems utilize this heterogeneous parallel computing system architecture. Building multi-level parallel computing software development frameworks and programming tools for heterogeneous parallel computing systems, and facilitating the development and porting of large-scale parallel computing application software, is key to achieving widespread adoption of heterogeneous parallel computing systems. The development of heterogeneous collaborative parallel computing technology (FPGAs) can improve the computational performance of large-scale geophysical data computations, creating greater economic benefits for society. Furthermore, these technological advances can reduce the cost of computer hardware and software, enabling the introduction of more computers for high-performance computing.

[0004] The current challenges of high-density data acquisition and deep and ultra-deep imaging in oil exploration require enormous amounts of data for 3D-RTM calculations, placing high demands on computing power. Current FPGA chips have limited hardware resources per card. When using a single computing board to calculate large-scale, ultra-deep 3D-RTM, insufficient FPGA resources necessitate transferring large amounts of data to the CPU. This repeated data readout significantly increases the computing resource consumption associated with data transfer. Summary of the Invention

[0005] The purpose of the present invention is to provide a three-dimensional prestack reverse time migration method based on a wave field reconstruction method of an FPGA multi-board architecture, so as to solve the above technical problems.

[0006] The technical solution adopted in the present invention is as follows:

[0007] The 3D prestack reverse time migration method based on the wavefield reconstruction method of the FPGA multi-board architecture includes:

[0008] S1. Prepare the calculation data required for forward modeling on the CPU side, and use a programming language to complete the programming of the calculation data in the Linux operating system environment;

[0009] S2: The CPU exchanges data with the first FPGA board, and the first FPGA board outputs corresponding parameters to the second FPGA board and the third FPGA board;

[0010] S3, the second FPGA board calculates the forward wave field, and outputs an end signal to the first FPGA board after the calculation is completed;

[0011] S4: The first FPGA board starts counting and simultaneously outputs signals to the second FPGA board and the third FPGA board to start the calculation of the forward wavefield and the reverse wavefield;

[0012] S5. The second FPGA board and the third FPGA board output the forward wavefield and the reverse wavefield at the same moment to the first FPGA board, and the first FPGA board completes the imaging calculation;

[0013] S6. The first FPGA board completes the calculations at all times and outputs the final imaging results to the CPU.

[0014] Preferably, the calculation data includes constant differential coefficients, boundary absorption parameters, source wavelets and parameter information of the observation system required in the calculation process.

[0015] As a further preference, in S2, the CPU and the first FPGA board interact with each other in terms of parameter information of velocity parameters, the source wavelet, the constant differential coefficient, and the boundary absorption parameter.

[0016] Preferably, in S5, after the first FPGA board completes the imaging calculation, the second FPGA board and the third FPGA board start the wavefield calculation at the next moment.

[0017] Preferably, in S5, both the forward wavefield and the reverse wavefield are output to the first FPGA board through a high-speed GTY interface.

[0018] Preferably, in S6, after the first FPGA board outputs the imaging result to the CPU, data superposition and subsequent processing need to be completed on the CPU side.

[0019] Preferably, in S2, data is exchanged between the CPU and the first FPGA board through a hardware interface.

[0020] The above technical solution has the following advantages or beneficial effects:

[0021] (1) In the present invention, the wave field reconstruction algorithm implemented by multiple FPG boards and CPU heterogeneous architecture enables the 3D-RTM seismic imaging algorithm to greatly reduce the data storage requirements of each computing board during the calculation process. This pipeline architecture allows the calculated data to be transmitted to another computing board, and the next step of calculation is immediately obtained, which greatly reduces unnecessary data cache transmission and reduces the consumption of computing resources during the data transmission process. At the same time, three computing boards can calculate simultaneously, which greatly improves the computing efficiency by 3 times compared with a single computing board.

[0022] (2) In this invention, the wavefield reconstruction method greatly reduces the amount of data required in the calculation process, greatly reduces the pressure on hardware memory requirements, and provides practical computing power support for deep and ultra-deep formation imaging currently faced by the industry. The entire implementation fully utilizes the parallel computing advantages of FPGA, fully utilizes the balance between computing time and data transmission time in the entire calculation process, and greatly improves the utilization rate of hardware computing resources. This architecture avoids the transmission problem of data cache and eliminates the I / O bottleneck problem.

[0023] (3) In the present invention, the data processing part is implemented in the Linux environment using the C++ programming language, and data processing operations are reserved, so that the system can flexibly adapt to industrial production and meet academic research needs;

[0024] (4) In the present invention, the complexity of hardware operation is shielded by the overall architecture of the heterogeneous platform, and subsequent data processing functions are directly implemented through programming, which also provides greater convenience for data pre-processing and supports compatibility with commercial software;

[0025] (5) In the present invention, the overall architecture scheduling is implemented using C++ programming language, making the entire system cross-platform operable and enabling the expansion of dedicated hardware chips in different operating system environments. This can meet the computational requirements of ultra-large-scale seismic data 3DRTM, and its performance can reach a 200-fold acceleration ratio compared to the same CPU acceleration solution.

[0026] (6) In the present invention, the method uses an FPGA computing board (FPGA board) as a computing platform to make it possible for 3D-RTM to play a role in actual oil and gas exploration. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a flow chart of the three-dimensional prestack reverse time migration method based on the FPGA multi-board architecture of the present invention;

[0028] Figure 2 This is the architecture and data flow diagram between the three FPGA boards in the present invention;

[0029] Figure 3 This is a flow chart of the three FPGA boards in the present invention implementing the wave field reconstruction method and realizing RTM data. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not intended to indicate or imply relative importance.

[0032] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention in specific contexts.

[0033] Figure 1 This is a flow chart of the three-dimensional prestack reverse time migration method based on the FPGA multi-board architecture of the present invention; Figure 2 This is the architecture and data flow diagram between the three FPGA boards in the present invention; Figure 3 This is a flowchart of the three FPGA boards in the present invention to implement the wave field reconstruction method and realize RTM data, please refer to Figures 1 to 3 FIG. 1 shows a preferred embodiment of a three-dimensional prestack reverse time migration method using a wave field reconstruction method based on an FPGA multi-board architecture, comprising:

[0034] S1. Prepare the computational data required for forward modeling on the CPU and program the data using a programming language within the Linux operating system. In this embodiment, the programming language used is C++. During the programming process, the required constant differential coefficients, boundary absorption parameters, source wavelets, and observation system parameters are calculated.

[0035] S2. The CPU exchanges data with the first FPGA board, and the first FPGA board outputs corresponding parameters to the second FPGA board and the third FPGA board.

[0036] S3. The second FPGA board calculates the forward wave field and outputs an end signal to the first FPGA board after the calculation is completed.

[0037] S4, the first FPGA board starts counting and simultaneously outputs signals to the second FPGA board and the third FPGA board to start the calculation of the forward wave field and the reverse wave field. Figure 3 As shown, when the first FPGA board starts counting, it is necessary to control the time t of wavefield extrapolation. If the time t of wavefield extrapolation is greater than the preset time T, the second FPGA board outputs an end signal to the first FPGA board; if the time t of wavefield extrapolation is less than the preset time T, the second FPGA board will recalculate the forward wavefield. In this embodiment, it is worth noting that Figure 2 and Figure 3 FPGA board 1 and board 1 are both the first FPGA board, FPGA board 2 and board 2 are both the second FPGA board, and FPGA board 3 and board 3 are both the third FPGA board.

[0038] S5: The second and third FPGA boards output the forward and reverse wavefields at the same time to the first FPGA board, and the first FPGA board completes the imaging calculation. In this embodiment, the first FPGA board exchanges data with the CPU in the PC (personal computer) via a hardware (PCIE) interface. The first FPGA board then sends a control signal and a velocity model to the second FPGA board, causing the second FPGA board to perform forward wavefield modeling and reconstruction calculations. After the reconstruction calculations are complete, the second FPGA board outputs an end signal to the first FPGA board. At this point, the first FPGA board simultaneously outputs signals to the second and third FPGA boards, causing the second FPGA board to perform forward wavefield calculations and the third FPGA board to perform reverse wavefield calculations. The second FPGA board then sends the forward wavefield value to the first FPGA board, while the third FPGA board also sends the reverse wavefield value to the first FPGA board, allowing the first FPGA board to complete the imaging calculations and ultimately output the imaging results to the CPU.

[0039] S6. The first FPGA board completes calculations for all moments and outputs the final imaging results to the CPU. In this invention, a wavefield forward modeling calculation is performed on the second FPGA board, and the gather data reverse continuation process is performed simultaneously on another computing board. The forward wavefield values ​​are reconstructed using differential equations on the second FPGA board. Leveraging the FPGA's high parallel computing capabilities, this invention utilizes three FPGA boards to implement the 3D-RTM wavefield reconstruction method, with different computing boards performing simultaneous calculations at different stages. A wavefield forward modeling calculation is performed on the second FPGA board, and the effective wavefield boundary data is recorded in the DDR (memory) of the second FPGA board. Then, the gather data reverse continuation process is performed on the third FPGA board. The forward wavefield is reconstructed using differential equations on the second FPGA board, and the forward and reverse wavefield values ​​at that moment are simultaneously transferred to the first and second FPGA boards. Simultaneously, the second and third FPGA boards begin wavefield calculations for the next moment, continuing until all wavefield values ​​at each moment are calculated. This architecture greatly reduces the computing tasks shared by each computing board, greatly reduces the interaction between the data required for computing and the CPU, and greatly reduces the demand for data storage. At the same time, all data transmission in this architecture is carried out through high-speed transmission between chips, allowing data to flow in a streamlined manner throughout the entire computing process.

[0040] Furthermore, as a preferred embodiment, the calculation data includes constant differential coefficients, boundary absorption parameters, source wavelets and parameter information of the observation system required in the calculation process.

[0041] Furthermore, as a preferred implementation, in S2, the CPU and the first FPGA board exchange parameter information of velocity parameters, source wavelets, constant differential coefficients, and boundary absorption parameters.

[0042] Furthermore, as a preferred implementation, in S5, after the first FPGA board completes the imaging calculation, the second FPGA board and the third FPGA board start the next wavefield calculation.

[0043] Furthermore, as a preferred implementation, in S5, both the forward wavefield and the reverse wavefield are output to the first FPGA board through a high-speed GTY interface.

[0044] Furthermore, as a preferred embodiment, in S6, after the first FPGA board outputs the imaging result to the CPU, data superposition and subsequent processing need to be completed on the CPU side, such as low-frequency filtering, and the final processed imaging result is output.

[0045] Furthermore, as a preferred implementation, in S2, data is exchanged between the CPU and the first FPGA board through a hardware interface.

[0046] In the present invention, for 3D-RTM seismic imaging, the collected seismic data is used as the boundary data input for the two-way wave equation. Starting from the shot point, the wave equation is solved to obtain the forward wavefield. Simultaneously, the reverse wavefield values ​​are obtained by performing a zero-delay cross-correlation operation (using the cross-correlation imaging condition) between the forward and reverse wavefields at corresponding moments to obtain the imaging profile. A mobile observation system is used for data acquisition in actual seismic exploration, and the single-shot data for imaging calculations are independent of each other. In the entire calculation design process, single-shot data is used as the calculation unit. A complete forward modeling process is first completed on the second FPGA board, and the calculated wavefield boundary values ​​are stored in the DDR of the second FPGA board. Simultaneously, a signal is sent to the first FPGA board to start the second and third FPGA boards to calculate the reconstructed forward and reverse wavefield values. These values ​​are then synchronously transmitted to the first FPGA board for imaging calculation. Ultimately, the imaging result is output.

[0047] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional prestack reverse time migration method based on a wave field reconstruction method using an FPGA multi-board architecture, characterized in that: include: S1. Prepare the calculation data required for forward modeling on the CPU side, and use a programming language to complete the programming of the calculation data in the Linux operating system environment; S2: The CPU exchanges data with the first FPGA board, and the first FPGA board outputs corresponding parameters to the second FPGA board and the third FPGA board; S3, the second FPGA board calculates the forward wave field, and outputs an end signal to the first FPGA board after the calculation is completed; S4: The first FPGA board starts counting and simultaneously outputs signals to the second FPGA board and the third FPGA board to start the calculation of the forward wavefield and the reverse wavefield; S5. The second FPGA board and the third FPGA board output the forward wavefield and the reverse wavefield at the same moment to the first FPGA board, and the first FPGA board completes the imaging calculation; S6. The first FPGA board completes the calculations at all times and outputs the final imaging result to the CPU; The calculation data includes constant differential coefficients, boundary absorption parameters, source wavelets, and parameter information of the observation system required in the calculation process; in S2, the CPU and the first FPGA board exchange parameter information of velocity parameters, the source wavelets, the constant differential coefficients, and the boundary absorption parameters; and the CPU and the first FPGA board exchange data through a hardware interface; In S5, after the first FPGA board completes the imaging calculation, the second FPGA board and the third FPGA board start the next wavefield calculation; in S5, the forward wavefield and the reverse wavefield are both output to the first FPGA board through the high-speed GTY interface; in S6, after the first FPGA board outputs the imaging result to the CPU, data superposition and subsequent processing need to be completed on the CPU side.

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