Data processing method and device, chip, equipment and medium

Abstract

A data processing method and device, chip, equipment and medium are provided, relating to the technical field of data storage, and specifically relating to the technical field of chips. The implementation scheme is: in response to receiving a first read request and a first write request for a first single-port memory block in a plurality of single-port memory blocks in a first clock cycle, performing a read operation for the first single-port memory block according to the first read request, wherein the first write request includes first write data and a first write address; sending a cache request for the first write data to a shared cache block to cache the first write data to a target location in the shared cache block, wherein the target location is a storage location in the shared cache block corresponding to the first write address of the first single-port memory block; and in response to receiving a cache request for second write data for the target location of the shared cache block in a second clock cycle, performing an operation of transmitting the first write data to the first single-port memory block before caching the second write data to the shared cache block.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, specifically to the field of chip technology, and particularly to a data processing method, apparatus, chip, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] Many modern electronic circuits have independent memory. Memory in electronic circuits includes types such as single-port memory and dual-port memory. In single-port memory, for each single-port memory block, only one of the read and write operations is allowed to be performed in the same clock cycle; simultaneous read and write operations are not allowed. Summary of the Invention

[0003] This disclosure provides a method, apparatus, chip, electronic device, computer-readable storage medium, and computer program product for data processing.

[0004] According to one aspect of this disclosure, a data processing method is provided for a circuit with storage function, the circuit including a plurality of single-port memory blocks and a shared cache block, the method comprising: responding to receiving a first read request and a first write request for a first single-port memory block among the plurality of single-port memory blocks in a first clock cycle; performing a read operation for the first single-port memory block according to the first read request, wherein the first write request includes first write data and a first write address; sending a cache request for the first write data to the shared cache block to cache the first write data at a target location in the shared cache block, wherein the target location is a storage location in the shared cache block corresponding to the first write address of the first single-port memory block; and responding to receiving a cache request for second write data for the target location of the shared cache block in a second clock cycle, performing an operation to transfer the first write data to the first single-port memory block before caching the second write data to the shared cache block.

[0005] According to another aspect of this disclosure, a data processing apparatus is provided for a circuit with storage function, the circuit including a plurality of single-port memory blocks and a shared cache block, the apparatus comprising: a first read module configured to, in response to receiving a first read request and a first write request for a first single-port memory block among the plurality of single-port memory blocks in a first clock cycle, perform a read operation for the first single-port memory block according to the first read request, wherein the first write request includes first write data and a first write address; a write module configured to send a cache request for the first write data to the shared cache block to cache the first write data at a target location in the shared cache block, wherein the target location is a storage location in the shared cache block corresponding to the first write address of the first single-port memory block; and a transmission module configured to, in response to receiving a cache request for second write data for the target location of the shared cache block in a second clock cycle, perform an operation to transmit the first write data to the first single-port memory block before caching the second write data to the shared cache block.

[0006] According to another aspect of this disclosure, a chip is provided, comprising: at least one processor; and a memory having a computer program stored thereon, wherein the computer program, when executed by the processor, causes the processor to perform the methods described above.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the chip described above.

[0008] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores a computer program thereon, which, when executed by a processor, causes the processor to perform the methods described above.

[0009] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods described above.

[0010] According to one or more embodiments of this disclosure, when a single-port memory block in the circuit receives both a read request and a write request simultaneously within the same clock cycle, the circuit can still read data based on the read request and save the written data. The data interaction between the circuit and other processors can be performed normally in the event of a read-write conflict, thus avoiding the degradation of system performance caused by the read-write conflict.

[0011] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0012] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a flowchart illustrating a data processing method according to an exemplary embodiment;

[0014] Figure 2 This is a schematic diagram illustrating a data processing method according to an exemplary embodiment;

[0015] Figure 3 This is a timing diagram illustrating a data processing method according to an exemplary embodiment;

[0016] Figure 4 This is a timing diagram illustrating another data processing method according to an exemplary embodiment;

[0017] Figure 5 This is a schematic block diagram illustrating a data processing apparatus according to an exemplary embodiment; and

[0018] Figure 6 This is a block diagram illustrating an exemplary electronic device that can be applied to exemplary embodiments. Detailed Implementation

[0019] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0020] The terminology used in the description of the various examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context expressly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0021] Due to the read / write characteristics of single-port memory, if read and write requests are received simultaneously within the same clock cycle, only one request can be processed. In related technologies, to overcome this read / write conflict, the number of read / write ports on the single-port memory block is increased, allowing one port to perform data reading while another port performs data storage within the same cycle. However, increasing the number of read / write ports inevitably leads to an increase in circuit area, which undoubtedly contradicts the current demand for miniaturized integrated circuit design.

[0022] Based on this, this disclosure proposes a data processing method. In the event of a read-write conflict occurring in the first single-port memory block during the first clock cycle, the method prioritizes reading operations on the first single-port memory block while simultaneously buffering the first write data to be written to the first single-port memory block in a shared cache block. Until the second clock cycle, when the storage location in the shared cache block used to store the first write data receives a buffer request for the second write data, the method executes the operation of transferring the first write data to the first single-port memory block. Therefore, even when the single-port memory block in the circuit receives both read and write requests simultaneously during the first clock cycle, the circuit can still achieve both data reading based on the read request and saving of the write data. Data interaction between the circuit and other processors can be performed normally even in the event of a read-write conflict, avoiding system performance degradation caused by read-write conflicts.

[0023] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0024] Figure 1 This is a flowchart illustrating a data processing method 100 according to an exemplary embodiment. The data processing method 100 is for a circuit with storage functionality, the circuit including a plurality of single-port memory blocks and a shared cache block. The method 100 includes: step S101, in response to receiving a first read request and a first write request for a first single-port memory block among the plurality of single-port memory blocks in a first clock cycle, performing a read operation on the first single-port memory block according to the first read request, wherein the first write request includes first write data and a first write address; step S102, sending a cache request for the first write data to the shared cache block to cache the first write data at a target location in the shared cache block, wherein the target location is a storage location in the shared cache block corresponding to the first write address of the first single-port memory block; and step S103, in response to receiving a cache request for second write data at the target location of the shared cache block in a second clock cycle, performing an operation to transfer the first write data to the first single-port memory block before caching the second write data to the shared cache block.

[0025] Therefore, if a read request and a write request for the first single-port storage block are received within one clock cycle, i.e. a read-write conflict occurs, this disclosure can cache the first write data in a shared cache block, so that the data interaction between the circuit and other processors can be performed normally in the event of a read-write conflict, thus avoiding the system performance degradation caused by the read-write conflict.

[0026] Meanwhile, since the shared cache block enables faster data retrieval, this disclosure maximizes the caching time of the first write data in the shared cache block. Specifically, the operation of transferring the first write data to the first single-port memory block is only performed when the storage location in the shared cache block used to cache the first write data receives a caching request for the second write data during the second clock cycle. This fully utilizes the cache space in the shared cache block, improving the retrieval efficiency of the data stored in the circuit, while also avoiding the resource overhead caused by unnecessary data transfer between the shared cache block and the first single-port memory block.

[0027] In other words, this disclosure achieves the function of simultaneously processing read and write requests, which is only available with multi-port storage blocks, while using a single-port storage block. This not only reduces the cost but also effectively saves processing resources and reduces power consumption, thereby effectively improving the storage performance of the system without additional expansion of the circuit scale.

[0028] The aforementioned circuit with storage function can be a chip. Each of the multiple single-port memory blocks is a bank allocated from the available storage space of the circuit.

[0029] According to some embodiments, each of the multiple single-port memory blocks is the same size.

[0030] In one implementation, each of the plurality of single-port memory blocks contains the same number of memory cells. In particular, each single-port memory block has the same number of sequentially arranged entries.

[0031] Regarding step S101, if a first read request and a first write request for the first single-port memory block are received simultaneously in the first clock cycle, it can be determined that a read / write conflict has occurred for the first single-port memory block. To avoid system performance degradation caused by the processor's inability to obtain read data in a timely manner, the read operation based on the first read request is processed first.

[0032] In step S102, for the first write request that causes a read-write conflict, a cache request for the first write data in the first write request is sent to the shared cache block in the circuit, so as to cache the first write data at the target location in the shared cache block. Thus, the first write data that cannot be processed immediately due to the read-write conflict in the first clock cycle can be cached in the shared cache block to wait for processing in subsequent clock cycles.

[0033] According to some embodiments, each of the shared cache block and the plurality of single-port storage blocks contains the same number of storage units. For each of the plurality of single-port storage blocks, the plurality of storage units in the single-port storage block correspond one-to-one with the plurality of storage units in the shared cache block. The first write address indicates a first storage unit among the plurality of storage units in the first single-port storage block, and the target location is the target storage unit in the plurality of storage units in the shared cache block that corresponds to the first storage unit. Thus, the first write data for the first single-port storage block can be cached orderly within the shared cache block.

[0034] For example, each of the shared cache block and the multiple single-port storage blocks contains storage units entry1 to entry5, and the storage units entry1 to entry5 of each of the multiple single-port storage blocks correspond one-to-one with the entries1 to entry5 in the shared cache block. In the event of a read-write conflict, in response to a first write address instruction to write the first write data to entry3 in the first single-port storage block, the first write data can be cached in entry3 of the shared cache block.

[0035] Therefore, even if multiple write requests for storage units within the same single-port storage block result in read-write conflicts, the shared cache block can still cache the write data from these requests in an orderly manner, maximizing the reliability of the system during read-write conflicts.

[0036] According to some embodiments, after the first write data is cached at the target location in the shared cache block, the mapping relationship between the target location and the first single-port storage block is identified.

[0037] Therefore, based on the mapping relationship between the target location and the first single-port storage block, the single-port storage block to which the first write data cached at the target location is to be written can be determined as the first single-port storage block. In this way, it can be guaranteed that the first write data can be correctly written into the first single-port storage block in subsequent clock cycles.

[0038] Based on the above mapping relationship, the shared cache block can cache write data for multiple single-port storage blocks simultaneously.

[0039] Within a shared cache block, write data from multiple single-port storage blocks can be cached together. For example, for the same target location within a shared cache block, write data from different single-port storage blocks can be cached sequentially at that target location. A shared cache block does not require allocating a storage area for each single-port storage block, thus fully utilizing the cache space within the shared cache block and improving the flexibility of data caching.

[0040] In step S103, when the target location of the shared cache block needs to cache new write data, i.e., the second write data, during the second clock cycle, the operation of transferring the first write data to the first single-port storage block is performed.

[0041] The second clock cycle and the first clock cycle can be two consecutive clock cycles or two discontinuous clock cycles, and there is no limitation here.

[0042] According to some embodiments, the second write data comes from the second write request in the second read request and the second write request for the second single-port storage block among multiple single-port storage blocks in the second clock cycle. The second write request includes the second write data and the second write address, and the target location is the storage location in the shared cache block corresponding to the second write address of the second single-port storage block.

[0043] It can be seen that when a read / write conflict occurs for the second single-port storage block in the second clock cycle, the read operation for the second single-port storage block can be executed first, and the second write data in the second write request can be cached in the shared cache block.

[0044] Since read and write operations on different single-port memory blocks do not affect each other, read operations on the second single-port memory block and write operations on the first single-port memory block can be performed simultaneously within the second clock cycle.

[0045] According to some embodiments, the second write address indicates a second storage unit among multiple storage units of a second single-port storage block, and the target location is a target storage unit corresponding to the second storage unit among multiple storage units in a shared cache block.

[0046] Taking the example where each of the shared cache block and multiple single-port storage blocks contains storage units entry1 to entry5, when a read / write conflict occurs for the second single-port storage block, the second write data for the second single-port storage block is written to the shared cache block. Currently, the first write data is cached in entry3 of the shared cache block. When the second write address indicates that the second write data needs to be written to entry3 of the second single-port storage block, a cache request for the second write data is sent to the target location of the shared cache block, i.e., entry3. Before the second write data is cached in entry3 of the shared cache block, the first write data currently stored in entry3 of the shared cache block is read out.

[0047] According to some embodiments, performing the operation of transferring the first write data to the first single-port storage block includes: reading the first write data from a shared cache block; and writing the first write data to the first single-port storage block.

[0048] According to some embodiments, each of the plurality of single-port storage blocks has a corresponding buffer, and wherein performing the operation of transferring first write data to the first single-port storage block includes: reading the first write data from a shared buffer block; caching the first write data into the first buffer corresponding to the first single-port storage block; in response to receiving a caching request for third write data for the first buffer in a third clock cycle, reading the first write data from the first buffer before caching the third write data into the first buffer; and writing the first write data into the first single-port storage block.

[0049] In high-speed memory, it is difficult to complete both the reading of the first write data from the shared cache block and the writing of the first write data to the first single-port memory block within one clock cycle. To meet the time constraints of high-speed memory, a corresponding buffer is set for each of the multiple single-port memory blocks. By buffering the first write data in the first buffer, the operation of transferring the first write data to the first single-port memory block can be completed within two or more clock cycles.

[0050] Similar to the shared cache block, the first cache bar also supports efficient data reading. Therefore, in order to improve the system's data reading efficiency and avoid unnecessary data transfer, the cache duration of the first write data in the first cache bar can be extended to the maximum extent. That is, when a cache request for the third write data for the first cache bar is received in the third clock cycle, the first write data in the first cache bar is then read from the first cache bar and written to the first single-port storage block.

[0051] According to some embodiments, after the first write data is cached in the first cache bar corresponding to the first single-port storage block, the mapping relationship between the first cache bar and the first write address is identified.

[0052] Since each of the multiple single-port memory blocks has a corresponding cache slot, it can be determined that the first write data cached in the first cache slot should be written to the first single-port memory block. Based on this, it is only necessary to identify the mapping relationship between the first cache slot and the first write address in the first single-port memory block to ensure that the first write data can be correctly written to the storage location indicated by the first write address in the first single-port memory block within the third clock cycle.

[0053] Figure 2 A schematic diagram of a data processing method according to an exemplary embodiment of the present disclosure is shown, wherein, as in... Figure 2 The circuit shown includes multiple single-port memory blocks 261 to 265, and each of the multiple single-port memory blocks 261 to 265 has a corresponding buffer strip 251 to 255.

[0054] In the first clock cycle, a first read request 201 and a first write request 202 are received. In response to the read-write conflict determination module 210 determining that the first read request 201 and the first write request 202 are both for the same single-port storage block, a read-write conflict is determined to have occurred; otherwise, it is determined that no read-write conflict has occurred.

[0055] In the absence of read-write conflicts, a read operation can be performed simultaneously based on the first read request and a write operation based on the first write request within the first clock cycle.

[0056] In the event of a read-write conflict, a read operation is performed only in the first clock cycle based on the first read request. The following explanation uses the example where both the first read request 201 and the first write request 202 are for a single-port memory block 262.

[0057] The first read address in the first read request 201 is sent to the single-port storage block selection module 220. Subsequently, the single-port storage block selection module 220 sends the first read address to the single-port storage block 262 to read the first read data 203 to be read from the single-port storage block 262. The first read data 203 is output through the read data control module 270.

[0058] The read / write conflict determination module 210 inputs the first write address from the first write request 202 into the cache control module 240, and the first write data 204 is cached in the shared cache block 230 through the write data control module 250. Specifically, the first write address indicates that the first write data 204 should be written to entry2 in the single-port storage block 262. The cache control module 240 controls the caching of the first write data 204 into entry2 of the shared cache block 230 based on this first write address. Simultaneously, the cache control module 240 identifies the mapping relationship between entry2 and the single-port storage block 262.

[0059] In the second clock cycle, in response to the read-write conflict determination module 210 determining that a read-write conflict has occurred between the second read request and the second write request, and the shared cache block 230 receiving a cache request for the second write data of entry2, the first write data 204 is read from the shared cache block 230 and cached in the cache strip 252 corresponding to the single-port storage block 262. Simultaneously, the mapping relationship between the first write data 204 cached in the cache strip 252 and entry2 is marked.

[0060] In the third clock cycle, in response to the cache request for the third write data received by the cache bar 252, the first write data 204 is read from the cache bar 252 and written into the entry2 of the single-port storage block 262.

[0061] According to some embodiments, in response to receiving a third read request for a third single-port memory block among a plurality of single-port memory blocks in a fourth clock cycle, it is determined whether the shared cache block and the third cache bar corresponding to the third single-port memory block contain the data to be read by the third read request; and in response to the fact that either the shared cache block or the third cache bar contains the data to be read by the third read request, the data is read from the shared cache block or the third cache bar containing the data.

[0062] Since the data to be read by the third read request for the third single-port storage block may be cached in the shared cache block or the third cache bar, the data cached in these two places is checked first. If the data to be read by the third read request can be hit, the data can be read efficiently from these two places.

[0063] According to some embodiments, in response to the fact that neither the shared cache block nor the third cache block contains the data to be read by the third read request, the data can be read from the third single-port storage block.

[0064] Figure 3 A data processing timing diagram according to an exemplary embodiment of the present disclosure is shown.

[0065] exist Figure 3 In the sequence, 301 is the write address timing, 302 is the write data timing, 303 is the read address timing, 304 is the read data timing, 305 is the read-write conflict timing, 306 is the shared cache block write address timing, 307 is the shared cache block write data timing, 308 is the shared cache block read address timing, and 309 is the shared cache block read data timing.

[0066] like Figure 3 As shown, during clock cycles 2 to 4, write data 0xEA (corresponding to address 100), 0xEB (corresponding to address 101), and 0xEC (corresponding to address 102) for the first single-port memory block are received sequentially. Since no read / write conflict occurs during this period, write operations for write data 0xEA (corresponding to address 100), 0xEB (corresponding to address 101), and 0xEC (corresponding to address 102) can be executed normally.

[0067] During clock cycles 5-7, read and write requests for the first single-port memory block are received simultaneously. Specifically, write data 0xED (corresponding to address 103), 0xEE (corresponding to address 104), and 0xEF (corresponding to address 105) are received sequentially, along with read requests for addresses 100, 101, and 102 of the first single-port memory block. During this period, a read-write conflict occurs, and read-write conflict timing 305 is pulled high. Due to the read-write conflict, write data 0xED (corresponding to address 103), 0xEE (corresponding to address 104), and 0xEF (corresponding to address 105) are cached in the shared cache block.

[0068] During clock cycle 8, a read request for address 103 of the first single-port storage block is received. The data cached in the shared cache block is retrieved first. The write data 0xED (corresponding to address 103) cached in the shared cache block is found, and the write data 0xED (corresponding to address 103) is read from the shared cache block.

[0069] During clock cycles 9 and 10, read requests for addresses 104 and 105 of the first single-port memory block are received. Based on a similar approach to clock cycle 8, write data 0xEE (corresponding to address 104) and 0xEF (corresponding to address 105) are read from the shared cache block.

[0070] Figure 4 Another data processing timing diagram according to an exemplary embodiment of the present disclosure is shown.

[0071] exist Figure 4 In the sequence, 401 is the write address timing, 402 is the write data timing, 403 is the read address timing, 404 is the read data timing, and 405 is the read-write conflict timing. 406 is the shared cache block write address timing, 407 is the shared cache block write data timing, 408 is the shared cache block read address timing, and 409 is the shared cache block read data timing. 410 is the first single-port storage block address timing, 411 is the first single-port storage block read data timing, and 412 is the first single-port storage block write data timing. 413 is the first single-port storage block cache strip write address timing, 414 is the first single-port storage block cache strip write data timing, 415 is the first single-port storage block cache strip read address timing, and 416 is the first single-port storage block cache strip read data timing. 417 is the timing sequence for the second single-port storage block address, 418 is the timing sequence for reading data from the second single-port storage block, and 419 is the timing sequence for writing data to the second single-port storage block. 420 is the timing sequence for writing the cache strip of the second single-port storage block, 421 is the timing sequence for writing data to the cache strip of the second single-port storage block, 422 is the timing sequence for reading the cache strip of the second single-port storage block, and 423 is the timing sequence for reading data from the cache strip of the second single-port storage block.

[0072] During clock cycles 2-5, write data 0xEA (corresponding to address 100), 0xEB (corresponding to address 101), 0xEC (corresponding to address 102), and 0xED (corresponding to address 103) for the first single-port memory block are received sequentially. During clock cycles 6-9, write data 0xFA (corresponding to address 200), 0xFB (corresponding to address 201), 0xFC (corresponding to address 202), and 0xFD (corresponding to address 203) for the second single-port memory block are received sequentially. Since no read / write conflicts occur during clock cycles 2-5, the write operations for the above data can be executed normally.

[0073] To meet the time constraints of high-speed memory, the write data is first cached in the cache slot corresponding to the single-port memory block. Since the cache space in the cache slot can only hold one set of write data, when new write data needs to be cached in the cache slot, the current write data in the cache slot is written into the corresponding single-port memory block.

[0074] During clock cycles 13 to 15, read requests and write requests for the first single-port memory block are received simultaneously. Specifically, write data 0xE1 (corresponding to address 106), 0xE2 (corresponding to address 107), and 0xE3 (corresponding to address 108) for the first single-port memory block are received sequentially, along with read requests for addresses 100, 101, and 102 of the first single-port memory block. During this period, a read-write conflict occurs, and read-write conflict timing 405 is pulled high.

[0075] Since the read data for addresses 100, 101, and 102 in the first single-port storage block was not cached in the shared cache block, nor was it retrieved from the first cache entry corresponding to the first single-port storage block, the read data for addresses 100, 101, and 102 were read sequentially from the first single-port storage block. Due to the read-write conflict, the write data 0xE1 (corresponding to address 106), 0xE2 (corresponding to address 107), and 0xE3 (corresponding to address 108) were sequentially cached in entries 6, 7, and 8 of the shared cache block.

[0076] During clock cycle 16, a read request and a write request for the second single-port memory block are received simultaneously. That is, a write data 0×F1 (corresponding to address 206) for the second single-port memory block and a read request for address 201 of the second single-port memory block are received simultaneously. Therefore, a read-write conflict occurs, and the read-write conflict timing 405 is pulled high.

[0077] Since the read data for address 201 of the second single-port memory block is not cached in the shared cache block, and the read data for address 201 is not retrieved from the second cache slot corresponding to the second single-port memory block, the read data for address 201 is read from the second single-port memory block. Due to the read-write conflict, write data 0xF1 (corresponding to address 206) needs to be cached in entry 6 of the shared cache block. Since write data 0xE1 (corresponding to address 106) is currently stored in entry 6 of the shared cache block, write data 0xF1 (corresponding to address 206) needs to be read from entry 6 before writing write data 0xE1 (corresponding to address 106) to entry 6. The read write data 0xE1 (corresponding to address 106) is then written to the first cache slot corresponding to the first single-port memory.

[0078] During clock cycle 17, a read request and a write request for the second single-port memory block are received simultaneously. That is, a write data 0×F2 (corresponding to address 207) for the second single-port memory block and a read request for address 202 of the second single-port memory block are received simultaneously. Therefore, a read-write conflict occurs, and the read-write conflict timing 305 is pulled high.

[0079] Since the read data for address 202 of the second single-port storage block is not cached in the shared cache block, and the read data for address 202 is not retrieved from the second cache entry corresponding to the second single-port storage block, the read data for address 202 is read from the second single-port storage block. Due to the read-write conflict, write data 0xF2 (corresponding to address 207) needs to be cached in entry7 of the shared cache block. Since write data 0xE2 (corresponding to address 107) is currently stored in entry7 of the shared cache block, write data 0xF2 (corresponding to address 207) needs to be read from entry7 before writing write data 0xE2 (corresponding to address 107).

[0080] Since the first cache bar corresponding to the first single-port memory currently has write data 0×E1 (corresponding to address 106) cached, write data 0×E1 (corresponding to address 106) is first written into the first single-port memory, and then write data 0×E2 (corresponding to address 107) is written into the first cache bar.

[0081] During clock cycle 18, a read request and a write request for the second single-port memory block are received simultaneously. That is, a write data 0×F3 (corresponding to address 208) for the second single-port memory block and a read request for address 203 for the second single-port memory block are received simultaneously. Therefore, a read-write conflict occurs, and the read-write conflict timing 305 is pulled high.

[0082] Since read data for address 203 was retrieved from the second cache slot corresponding to the second single-port storage block, the read data for address 203 is read from the second cache slot. However, due to the read-write conflict, write data 0xF3 (corresponding to address 208) needs to be cached in entry8 of the shared cache block. Since write data 0xE3 (corresponding to address 108) is currently stored in entry8 of the shared cache block, write data 0xE3 (corresponding to address 108) needs to be read from entry8 before writing write data 0xF3 (corresponding to address 208) to entry8.

[0083] Since the first cache bar corresponding to the first single-port memory currently has write data 0×E2 (corresponding to address 107) cached, write data 0×E2 (corresponding to address 107) is first written into the first single-port memory, and then write data 0×E3 (corresponding to address 108) is written into the first cache bar.

[0084] Figure 5 This illustration shows a data processing apparatus 500 according to an exemplary embodiment, for a circuit with storage function, the circuit including a plurality of single-port memory blocks and a shared cache block. The apparatus 500 includes: a first read module 501 configured to, in response to receiving a first read request and a first write request for a first single-port memory block among the plurality of single-port memory blocks in a first clock cycle, perform a read operation for the first single-port memory block according to the first read request, wherein the first write request includes first write data and a first write address; a write module 502 configured to send a cache request for the first write data to the shared cache block to cache the first write data at a target location in the shared cache block, wherein the target location is a storage location in the shared cache block corresponding to the first write address of the first single-port memory block; and a transmission module 503 configured to, in response to receiving a cache request for second write data for the target location of the shared cache block in a second clock cycle, perform an operation to transmit the first write data to the first single-port memory block before caching the second write data to the shared cache block.

[0085] It should be understood that Figure 5 The various modules of the device 500 shown can be connected to the reference. Figure 1 The steps in method 100 described correspond to each other. Therefore, the operations, features, and advantages described above for method 100 also apply to device 500 and its included modules. For the sake of brevity, some operations, features, and advantages will not be repeated here.

[0086] According to some embodiments, the second write data comes from the second write request in the second read request and the second write request for the second single-port storage block among multiple single-port storage blocks in the second clock cycle. The second write request includes the second write data and the second write address, and the target location is the storage location in the shared cache block corresponding to the second write address of the second single-port storage block.

[0087] According to some embodiments, each of the shared cache block and the plurality of single-port storage blocks contains the same number of storage units. For each of the plurality of single-port storage blocks, the plurality of storage units in the single-port storage block correspond one-to-one with the plurality of storage units in the shared cache block. The first write address indicates the first storage unit in the plurality of storage units of the first single-port storage block, and the target location is the target storage unit in the plurality of storage units of the shared cache block that corresponds to the first storage unit.

[0088] According to some embodiments, the second write address indicates a second storage unit among multiple storage units of a second single-port storage block, and the target location is a target storage unit corresponding to the second storage unit among multiple storage units in a shared cache block.

[0089] According to some embodiments, the apparatus further includes a first identification module configured to identify the mapping relationship between the target location and the first single-port storage block after the first write data is cached at the target location in the shared cache block.

[0090] According to some embodiments, each of a plurality of single-port storage blocks has a corresponding buffer, and wherein the transmission module includes: a first read submodule configured to read first write data from a shared buffer block; a first write submodule configured to cache the first write data into a first buffer corresponding to the first single-port storage block; a second read submodule configured to, in response to receiving a caching request for third write data for the first buffer in a third clock cycle, read the first write data from the first buffer before caching the third write data into the first buffer; and a second write submodule configured to write the first write data into the first single-port storage block.

[0091] According to some embodiments, the device further includes a second identification module configured to identify the mapping relationship between the first cache bar and the first write address after the first write data is cached into the first cache bar corresponding to the first single-port storage block.

[0092] According to some embodiments, the apparatus further includes: a first determining module configured to determine, in response to receiving a third read request for a third single-port memory block among a plurality of single-port memory blocks in a fourth clock cycle, whether the shared cache block and the third cache strip corresponding to the third single-port memory block contain the data to be read by the third read request; and a second reading module configured to read the data from the shared cache block or the third cache strip containing the data in response to either the shared cache block or the third cache strip containing the data to be read by the third read request.

[0093] According to some embodiments, the device further includes a third read module configured to read the data from a third single-port storage block in response to the fact that neither the shared cache block nor the third cache bar contains the data to be read by the third read request.

[0094] While specific functions have been discussed above with reference to specific modules, it should be noted that the functions of the modules discussed herein can be divided into multiple modules, and / or at least some functions of multiple modules can be combined into a single module. The specific actions performed by the modules discussed herein include the specific module itself performing the action, or alternatively, the specific module calling or otherwise accessing another component or module that performs the action (or performs the action in conjunction with the specific module). Therefore, a specific module performing an action can include the specific module performing the action itself and / or another module that performs the action, called or otherwise accessed by the specific module.

[0095] It should also be understood that this article can describe various technologies in the general context of software and hardware components or program modules. The above regarding... Figure 5 The various modules described can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules can be implemented as computer program code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules can be implemented as hardware logic / circuit. For example, in some embodiments, Figure 5 One or more of the described modules may be implemented together in a System on Chip (SoC). The SoC may include an integrated circuit chip (which includes a processor (e.g., a Central Processing Unit (CPU), microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or one or more other components of circuitry), and may optionally execute received program code and / or include embedded firmware to perform functions.

[0096] According to one aspect of this disclosure, a chip is provided, comprising: at least one processor; and a memory having a computer program stored thereon, wherein the computer program, when executed by the processor, causes the processor to perform any of the methods described above.

[0097] According to one aspect of this disclosure, an electronic device is provided, including the chip described above.

[0098] According to one aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform any of the methods described above.

[0099] According to one aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform any of the methods described above.

[0100] In the following text, combined with Figure 6 Illustrative examples describing such electronic devices, non-transitory computer-readable storage media, and computer program products.

[0101] Figure 6 An example configuration of electronic device 1700 that can be used to implement the methods described herein is shown. The data processing apparatus described above can also be implemented wholly or at least partially by electronic device 1700 or similar devices or systems.

[0102] Electronic device 1700 can be a variety of different types of devices. Examples of electronic device 1700 include, but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless phones (e.g., smartphones), notebook computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to a display device, game consoles), televisions or other display devices, automotive computers, and so on.

[0103] Electronic device 1700 may include at least one processor 1702, memory 1704, multiple communication interfaces 1706, display device 1708, other input / output (I / O) devices 1710, and one or more mass storage devices 1712 capable of communicating with each other, such as via system bus 1714 or other suitable connections.

[0104] Processor 1702 may be a single processing unit or multiple processing units, and all processing units may include single or multiple computing units or multiple cores. Processor 1702 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operating instructions. Among other capabilities, processor 1702 may be configured to fetch and execute computer-readable instructions stored in memory 1704, mass storage device 1712, or other computer-readable media, such as program code of operating system 1716, program code of application program 1718, program code of other program 1720, etc.

[0105] Memory 1704 and mass storage device 1712 are examples of computer-readable storage media for storing instructions that are executed by processor 1702 to perform the various functions described above. For example, memory 1704 may generally include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). Furthermore, mass storage device 1712 may generally include hard disk drives, solid-state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network-attached storage, storage area networks, etc. Both memory 1704 and mass storage device 1712 may be collectively referred to herein as memory or computer-readable storage media, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which may be executed by processor 1702 as a specific machine configured to perform the operations and functions described in the examples herein.

[0106] Multiple programs may be stored on mass storage device 1712. These programs include operating system 1716, one or more application programs 1718, other programs 1720, and program data 1722, and they may be loaded into memory 1704 for execution. Examples of such application programs or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing components / functions such as method 100 (including any suitable steps of method 100), and / or other embodiments described herein.

[0107] Although Figure 6The modules 1716, 1718, 1720, and 1722, or portions thereof, are illustrated as being stored in memory 1704 of electronic device 1700. However, modules 1716, 1718, 1720, and 1722 may be implemented using any form of computer-readable medium accessible by electronic device 1700. As used herein, “computer-readable medium” includes at least two types of computer-readable media: computer-readable storage media and communication media.

[0108] Computer-readable storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD, or other optical storage devices, magnetic cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by electronic devices. In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms. Computer-readable storage media as defined herein do not include communication media.

[0109] One or more communication interfaces 1706 are used for exchanging data with other devices, such as via a network, direct connection, etc. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, Wi-MAX interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth. TM Interfaces include near-field communication (NFC) interfaces. Communication interface 1706 facilitates communication across various network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. Communication interface 1706 can also provide communication with external storage devices (not shown) such as storage arrays, network-attached storage, storage area networks, etc.

[0110] In some examples, a display device 1708, such as a monitor, may be included for displaying information and images to the user. Other I / O devices 1710 may be devices that receive various inputs from the user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and so on.

[0111] The technologies described herein can be supported by these various configurations of electronic device 1700, and are not limited to specific examples of the technologies described herein. For example, the functionality can also be implemented wholly or partially on a “cloud” using a distributed system. A cloud includes and / or represents a platform for resources. The platform abstracts the underlying functionality of the cloud’s hardware (e.g., servers) and software resources. Resources may include applications and / or data that can be used when performing computational processing on a server remote from electronic device 1700. Resources may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks. The platform can abstract resources and functionality to connect electronic device 1700 to other electronic devices. Therefore, the implementation of the functionality described herein can be distributed throughout the cloud. For example, the functionality can be implemented partly on electronic device 1700 and partly through the platform that abstracts the functionality of the cloud.

[0112] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practice with respect to the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "a plurality" means two or more, and the term "based on" should be interpreted as "at least partially based on". The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

Claims

1. A data processing method for a circuit with storage function, the circuit including multiple single-port storage blocks and a shared cache block, the method comprising: In response to receiving a first read request and a first write request for a first single-port memory block among the plurality of single-port memory blocks in a first clock cycle, a read operation for the first single-port memory block is performed according to the first read request, wherein the first write request includes first write data and a first write address; Send a cache request for the first written data to the shared cache block to cache the first written data at a target location in the shared cache block, wherein the target location is the storage location in the shared cache block corresponding to the first write address of the first single-port storage block; and In response to receiving a cache request for second write data for a target location of the shared cache block during the second clock cycle, an operation to transfer the first write data to the first single-port storage block is performed before caching the second write data into the shared cache block. The second write data comes from the second write request in the second read request and the second write request for the second single-port storage block among the plurality of single-port storage blocks in the second clock cycle. The second write request includes the second write data and the second write address. The target location is the storage location in the shared cache block corresponding to the second write address of the second single-port storage block.

2. The method of claim 1, wherein, Each of the shared cache block and the plurality of single-port storage blocks contains the same number of storage units. For each of the plurality of single-port storage blocks, the plurality of storage units in that single-port storage block corresponds one-to-one with the plurality of storage units in the shared cache block. Furthermore, the first write address indicates the first storage unit among the multiple storage units of the first single-port storage block, and the target location is the target storage unit among the multiple storage units of the shared cache block that corresponds to the first storage unit.

3. The method of claim 2, wherein, The second write address indicates the second storage unit among the multiple storage units of the second single-port storage block, and the target location is the target storage unit among the multiple storage units in the shared cache block that corresponds to the second storage unit.

4. The method according to claim 1, further comprising: After caching the first write data to the target location in the shared cache block, the mapping relationship between the target location and the first single-port storage block is identified.

5. The method according to claim 1, wherein, Each of the plurality of single-port storage blocks has a corresponding buffer, and the operation of transferring the first write data to the first single-port storage block includes: Read the first write data from the shared cache block; The first written data is cached in the first cache slot corresponding to the first single-port storage block; In response to receiving a cache request for third write data for the first cache bar in the third clock cycle, the first write data is read from the first cache bar before the third write data is cached in the first cache bar; and Write the first data into the first single-port storage block.

6. The method according to claim 5, further comprising: After caching the first write data into the first cache bar corresponding to the first single-port storage block, the mapping relationship between the first cache bar and the first write address is identified.

7. The method of claim 6, further comprising: In response to receiving a third read request for a third single-port memory block among the plurality of single-port memory blocks in the fourth clock cycle, determine whether the shared cache block and the third cache entry corresponding to the third single-port memory block contain the data to be read by the third read request; and In response to the fact that either the shared cache block or the third cache bar contains the data to be read by the third read request, the data is read from the shared cache block or the third cache bar containing the data.

8. The method according to claim 7, further comprising: If neither the shared cache block nor the third cache block contains the data to be read by the third read request, the data is read from the third single-port storage block.

9. A data processing apparatus for a circuit with storage function, the circuit including a plurality of single-port memory blocks and a shared cache block, the apparatus comprising: The first read module is configured to respond to receiving a first read request and a first write request for a first single-port memory block among the plurality of single-port memory blocks in a first clock cycle, and to perform a read operation for the first single-port memory block according to the first read request, wherein the first write request includes first write data and a first write address; The write module is configured to send a cache request for the first write data to the shared cache block, so as to cache the first write data at a target location in the shared cache block, wherein the target location is the storage location in the shared cache block corresponding to the first write address of the first single-port storage block; and The transmission module is configured to, in response to receiving a cache request for second write data for a target location of the shared cache block in a second clock cycle, perform an operation to transmit the first write data to the first single-port storage block before caching the second write data into the shared cache block. The second write data comes from the second write request in the second read request and the second write request for the second single-port storage block among the plurality of single-port storage blocks in the second clock cycle. The second write request includes the second write data and the second write address. The target location is the storage location in the shared cache block corresponding to the second write address of the second single-port storage block.

10. The apparatus according to claim 9, wherein, Each of the shared cache block and the plurality of single-port storage blocks contains the same number of storage units. For each of the plurality of single-port storage blocks, the plurality of storage units in that single-port storage block corresponds one-to-one with the plurality of storage units in the shared cache block. Furthermore, the first write address indicates the first storage unit among the multiple storage units of the first single-port storage block, and the target location is the target storage unit among the multiple storage units of the shared cache block that corresponds to the first storage unit.

11. The apparatus according to claim 10, wherein, The second write address indicates the second storage unit among the multiple storage units of the second single-port storage block, and the target location is the target storage unit among the multiple storage units in the shared cache block that corresponds to the second storage unit.

12. The apparatus according to claim 9, further comprising: The first identification module is configured to identify the mapping relationship between the target location and the first single-port storage block after the first write data is cached at the target location in the shared cache block.

13. The apparatus according to claim 9, wherein, Each of the plurality of single-port storage blocks has a corresponding buffer, and the transmission module includes: The first read submodule is configured to read the first write data from the shared cache block; The first write submodule is configured to cache the first write data into the first cache bar corresponding to the first single-port storage block; The second read submodule is configured to, in response to receiving a cache request for third write data for the first cache bar in a third clock cycle, read the first write data from the first cache bar before caching the third write data into the first cache bar; and The second write submodule is configured to write the first write data into the first single-port storage block.

14. The apparatus of claim 13, further comprising: The second identification module is configured to identify the mapping relationship between the first cache bar and the first write address after the first write data is cached in the first cache bar corresponding to the first single-port storage block.

15. The apparatus of claim 14, further comprising: The first determining module is configured to, in response to receiving a third read request for a third single-port storage block among the plurality of single-port storage blocks in a fourth clock cycle, determine whether the shared cache block and the third cache bar corresponding to the third single-port storage block contain the data to be read by the third read request; as well as The second read module is configured to read the data from the shared cache block or the third cache block containing the data requested by the third read request in response to either the shared cache block or the third cache block containing the data.

16. The apparatus of claim 15, further comprising: The third read module is configured to read the data from the third single-port storage block in response to the fact that neither the shared cache block nor the third cache bar contains the data to be read by the third read request.

17. A chip, comprising: At least one processor; as well as The memory, on which computer programs are stored, When the computer program is executed by the processor, it causes the processor to perform the method according to any one of claims 1 to 8.

18. An electronic device comprising the chip as claimed in claim 17.

19. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the method of any one of claims 1 to 8.

20. A computer program product comprising a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1 to 8.

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