A digital simulation verification method, device, and storage medium based on coroutines

Abstract

The present invention relates to a digital simulation verification method, device, and storage medium based on coroutines. The method includes the following steps: building a simulation platform and a verification platform, and establishing a data channel between the simulation platform and the verification platform; based on digital design, confirming associated simulation tasks and verification tasks; generating simulation coroutines in the simulation platform according to the simulation tasks, generating verification coroutines in the verification platform according to the verification tasks, and associating the simulation coroutines and verification coroutines based on the associated simulation tasks and verification tasks; based on the advancement program of the digital design, synchronously running the associated simulation coroutines and verification coroutines, and performing data transmission of the simulation coroutines and verification coroutines through the data channel between the simulation platform and the verification platform to complete the simulation and verification of the digital design; the present invention realizes synchronous operation and switching between the simulation platform and the verification platform of the digital design through coroutines, and realizes the synchronization of lightweight digital design simulation and verification tasks.

Description

Technical Field

[0001] The present invention relates to a digital simulation verification method, device, and storage medium based on coroutines, belonging to the technical field of digital design verification. Background Art

[0002] Currently, the mainstream chip designs are all implemented using Verilog / SystemVerilog languages for coding. After the coding is completed, it is necessary to verify whether the previous coding is correct, and this process is verification. Only the chip design that has passed the verification can finally be taped out for production. Therefore, in the chip design process, verification is an indispensable part. As the scale of the chip increases, the time required for verification in chip design becomes longer and the proportion in the entire design cycle becomes larger. In order to improve the verification speed, various automated verification languages (such as SystemVerilog, etc.) and verification tools (most of these verification tools support random verification) and various verification methodologies, such as OVM and VMM, have emerged. Therefore, how to quickly build an efficient verification platform, improve verification efficiency, shorten the verification cycle, and increase the process success rate has become the biggest challenge for verification engineers and one of the biggest pain points experienced by each chip company.

[0003] As Figure 1 shown, in order to achieve the synchronization between the verification platform and the simulation platform, the current mainstream method is to use semaphores to synchronize between processes / threads to achieve the synchronization between the verification platform and the simulation, and realize the "alternate execution" of the simulation platform and the verification platform. Since the semaphore-based synchronization method requires process / thread switching, the switching cost is relatively large, resulting in a large performance loss and being prone to deadlocks. Summary of the Invention

[0004] In order to solve the problems existing in the above-mentioned prior art, the present invention proposes a digital simulation verification method, device, and storage medium based on coroutines, which realizes the synchronous operation and switching between the simulation platform and the verification platform of digital design through coroutines, and realizes the synchronization of lightweight digital design simulation and verification tasks.

[0005] The technical solution of the present invention is as follows:

[0006] On the one hand, the present invention provides a digital simulation verification method based on coroutines, including the following steps:

[0007] Build a simulation platform and a verification platform, and establish a data channel between the simulation platform and the verification platform;

[0008] Based on the digital design, confirm the associated simulation tasks and verification tasks;

[0009] Generate a simulation coroutine in the simulation platform according to the simulation task, generate a verification coroutine in the verification platform according to the verification task, and associate the simulation coroutine and the verification coroutine based on the associated simulation task and verification task;

[0010] Based on the propulsion program of digital design, synchronously run the associated simulation coroutine and verification coroutine, and perform data transmission of the simulation coroutine and the verification coroutine through the data channel between the simulation platform and the verification platform to complete the simulation and verification of digital design.

[0011] As a preferred embodiment, the step of the propulsion program based on digital design synchronously running the associated simulation coroutine and verification coroutine and performing data transmission of the simulation coroutine and the verification coroutine through the data channel between the simulation platform and the verification platform is specifically as follows:

[0012] Based on the propulsion program of digital design, run the simulation coroutine;

[0013] After the simulation coroutine runs, the simulation platform gives an input data to the digital design;

[0014] Suspend the simulation coroutine and switch to the verification coroutine associated with the running simulation coroutine. The verification platform injects an excitation into the verification coroutine, samples the output data of the digital design of the simulation platform, verifies the output data to obtain a verification result, and switches back to the simulation coroutine after obtaining the verification result;

[0015] The simulation coroutine performs logical simulation calculation according to the verification result.

[0016] As a preferred embodiment, generate simulation subtasks based on the simulation task. When there are multiple simulation subtasks, generate a sorting relationship corresponding to the multiple simulation subtasks; generate a simulation coroutine corresponding to one simulation subtask;

[0017] Generate verification subtasks based on the verification task. When there are multiple verification subtasks, generate a sorting relationship corresponding to the multiple verification subtasks; generate a verification coroutine corresponding to one verification subtask.

[0018] As a preferred embodiment, when running the simulation coroutine, select the simulation coroutine corresponding to the simulation subtask ranked first according to the sorting relationship of the simulation subtasks to run;

[0019] After the operation of the simulation coroutine ends, wait for the operation instruction of the next propulsion program of the digital design, and continue to select the simulation coroutine corresponding to the simulation subtask ranked later to run until all the simulation coroutines corresponding to the simulation subtasks have been run.

[0020] As a preferred embodiment, when there are multiple verification subtasks for a verification task associated with a simulation subtask, in the step of suspending the simulation coroutine and switching to the verification coroutine associated with the running simulation coroutine:

[0021] According to the sorting relationship of multiple verification coroutines corresponding to multiple verification subtasks generated by the verification task associated with this simulation subtask, first switch to the verification coroutine ranked first. After the verification coroutine ranked first finishes running, then switch to the verification coroutine ranked later until all the verification coroutines corresponding to each verification subtask have finished running, and then switch back to the simulation coroutine corresponding to the simulation subtask.

[0022] As a preferred embodiment, the advancement program is a digital clock program;

[0023] Synchronously run the associated simulation coroutine and verification coroutine at the rising edge or falling edge of each clock cycle of the digital clock program.

[0024] On the other hand, the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the digital simulation verification method based on coroutines as described in any embodiment of the present invention.

[0025] On yet another aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the digital simulation verification method based on coroutines as described in any embodiment of the present invention.

[0026] The present invention has the following beneficial effects:

[0027] A digital simulation verification method based on coroutines according to the present invention uses the coroutine method to synchronously run and switch simulation tasks and verification tasks. Compared with the switching method of threads / processes, coroutine switching does not require interruption and the corresponding on-site saving and restoration, does not require address conversion, and the context switching of coroutines is much lighter than that of threads / processes, and better performance can be obtained. Description of the Drawings

[0028] Figure 1 It is a flowchart of the traditional digital simulation verification method in the background technology;

[0029] Figure 2 It is a flowchart of the digital simulation verification method based on coroutines according to the embodiment of the present invention;

[0030] Figure 3 It is a flowchart of the traditional process switching given in the embodiment of the present invention;

[0031] Figure 4 It is a flowchart of the coroutine switching given in the embodiment of the present invention;

[0032] Figure 5 This is an example flowchart for digital simulation verification in an embodiment of the present invention;

[0033] Figure 6 This is an example diagram for the switching of traditional thread - or process - based simulation tasks and verification tasks;

[0034] Figure 7 This is an example diagram for task switching using coroutines proposed based on an embodiment of the present invention. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0036] It should be understood that the step numbers used in the text are only for convenience of description and do not limit the execution order of the steps.

[0037] It should be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0038] The terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0039] The term "and / or" refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0040] Regarding the problem of switching cost in the simulation and verification of digital design in the prior art, an embodiment of the present application provides a digital simulation verification method based on coroutines, in which simulation tasks and verification tasks are synchronously run and switched through coroutines; a coroutine is a lightweight user-mode thread that implements non-preemptive scheduling, that is, the switch from the current coroutine to other coroutines is controlled by the current coroutine. A coroutine is an execution unit smaller than a thread and can be regarded as a lightweight thread. The scheduling of a thread is carried out in the operating system. When the operating system schedules a thread, it needs to save the execution environment of the thread (such as all variables and storage units), while the coroutine scheduling is implemented through user code, and the user realizes the scheduling of the coroutine by actively switching the coroutine instruction.

[0041] Because coroutines can be scheduled at the user code level, coroutines can yield the right of execution through coroutine switching instructions when they do not require CPU resources for coroutine switching. A general usage scenario is that coroutines can temporarily yield CPU resources for other coroutines to execute when performing I / O operations to improve CPU utilization.

[0042] The coroutine mechanism is also very suitable for scenarios where the simulation platform needs to be synchronized every clock cycle. After the calculation of each task / coroutine ends in each clock cycle, it can actively yield CPU computing resources for the coroutines that have not been executed in the current clock cycle. The switching of tasks is realized through the coroutine method to achieve lightweight task synchronization.

[0043] See Figure 2 , a digital simulation verification method based on coroutines provided by an embodiment of the present application specifically includes the following steps:

[0044] Build a simulation platform and a verification platform, and establish a data channel between the simulation platform and the verification platform; the simulation platform and the verification platform can be built using design languages such as Verilog / System Verilog / System C / Chisel / C / C++. In this embodiment, because the C / C++ language has the advantages of wide use, excellent performance, and complete ecosystem, and can be seamlessly integrated with the chip design language Verilog and has a very high acceptance in the field of chip verification, the simulation platform is built using Verilog and the verification platform is built using C / C++.

[0045] The IC design process generally has the following steps:

[0046] 1. Requirement design, formulating the chip function specification;

[0047] 2. Code in a specific language (such as Verilog) according to the chip function specification to implement the specific functions of the function specification.

[0048] 3. Verify whether the quality of the code meets the function specification (similar to software coding, it is necessary to test whether the code is correct).

[0049] 4. If the verification meets the specification, proceed with the subsequent process: until the chip is actually produced.

[0050] Based on the digital design (i.e., the design program code obtained through coding in the second step of the above IC design process), identify the associated simulation tasks and verification tasks; for the verification of the digital design (i.e., the third step in the above IC design process), it can actually be abstracted into one or more associated simulation tasks and verification tasks, and these simulation tasks and verification tasks need to be executed alternately within each task cycle.

[0051] Generate corresponding simulation coroutines in the simulation platform according to the generated simulation tasks, and generate corresponding verification coroutines in the verification platform according to the generated verification tasks; based on the association relationship between these simulation tasks and verification tasks, perform the association of the corresponding simulation coroutines and verification coroutines.

[0052] Based on the advancement program of the digital design, synchronously run the associated simulation coroutines and verification coroutines periodically, and perform data transmission of the simulation coroutines and verification coroutines through the data channel between the simulation platform and the verification platform to complete the simulation and verification of the digital design. For the simulation coroutines, they are mainly used for logical simulation calculations of the digital design; for the verification coroutines, they are mainly used for sampling the output of the digital design, injecting stimuli, and verifying the output.

[0053] For the existing digital simulation verification method of processes / threads mentioned in the background technology, Figure 1 on the left side is a looped simulation task process / thread sem_post(&sem1), which will continuously loop and execute during the simulation. When the simulation task reaches the rising edge of the clock, it cannot immediately perform the subsequent logical simulation calculations and must wait until the stimulus injection of the verification task process / thread sem_post(&sem2) on the right side is completed; therefore, the simulation task process / thread needs to stop execution, let the verification task process / thread execute, and then wait for the stimulus injection of the verification task process / thread to be completed. So the program execution process must be: at each rising edge of the clock -> stimulus injection of the verification task process / thread -> logical simulation calculation of the simulation task process / thread -> the next rising edge of the clock, and so on in a loop.

[0054] Taking a process as an example, the process switching process is as Figure 3 shown.

[0055] In this embodiment, the co-routine method is used to switch between simulation tasks and verification tasks. Compared with the switching method of threads / processes, co-routine switching does not require interruption and the corresponding on-site saving and restoration, does not require address conversion, and the context switching of co-routines is much lighter than that of threads / processes, so better performance can be obtained. The switching process of co-routines is as Figure 4 shown.

[0056] In a specific implementation manner of the embodiment of the present application, the steps of the propulsion program based on digital design to synchronously run associated simulation co-routines and verification co-routines and perform data transmission of the simulation co-routines and verification co-routines through the data channel between the simulation platform and the verification platform are specifically as follows:

[0057] The propulsion program based on digital design runs the simulation co-routine; wherein, the propulsion program of digital design periodically issues a running signal. After the simulation platform and the verification platform are initialized, the corresponding simulation co-routine and verification co-routine wait for the running signal. When the running signal arrives, the simulation co-routine / verification co-routine enters the running state;

[0058] After the simulation co-routine runs, the simulation platform gives an input data to the digital design;

[0059] Suspend the simulation co-routine and switch to the verification co-routine associated with the running simulation co-routine. The verification platform injects an excitation into the verification co-routine, samples the output data of the digital design of the simulation platform, verifies the output data to obtain a verification result, and after obtaining the verification result, switches back to the simulation co-routine and transmits the verification result back to the simulation co-routine;

[0060] The simulation co-routine performs logical simulation calculation according to the verification result.

[0061] In a specific implementation manner of the embodiment of the present application, simulation sub-tasks are generated based on the simulation task. When there are multiple simulation sub-tasks, a sorting relationship is generated corresponding to the multiple simulation sub-tasks; a simulation co-routine is generated corresponding to one simulation sub-task; for the simulation of a digital design, it can or can be abstracted as being composed of multiple simulation sub-tasks, and there is a sorting / sequential relationship between the multiple simulation sub-tasks. Therefore, in the implementation manner of this embodiment, when a simulation task is split into multiple simulation sub-tasks, first, each simulation sub-task needs to be sorted, and at the same time, several simulation co-routines are respectively generated corresponding to each simulation sub-task.

[0062] Generate verification subtasks based on the verification task. When there are multiple verification subtasks, generate a sorting relationship corresponding to the multiple verification subtasks; generate a verification coroutine for each verification subtask; for the verification task of digital design simulation, while performing verification, a series of logical calculations may also need to be performed on the initial verification results. This process can be abstracted as a composition of a verification task and multiple verification subtasks, and there is a sorting / sequential relationship among the multiple verification subtasks. Therefore, in the implementation manner of this embodiment, when a series of logical calculations need to be performed on the verification task, it is necessary to sort each verification subtask first, and at the same time, generate several verification coroutines corresponding to the verification task and each verification subtask respectively.

[0063] In a specific implementation manner of the embodiment of the present application, when the running signal sent by the advancement program arrives and a simulation coroutine needs to be run, if there are multiple simulation coroutines, first, according to the sorting relationship of the simulation subtasks, select the simulation coroutine corresponding to the simulation subtask ranked first to run;

[0064] After the operation of this simulation coroutine ends, wait for the running signal of the advancement program for the next digital design, and continue to select the simulation coroutine corresponding to the simulation subtask ranked later to run until the simulation coroutines corresponding to all simulation subtasks have finished running, and the simulation platform ends this simulation.

[0065] In a specific implementation manner of the embodiment of the present application, when there are multiple verification subtasks for the verification task associated with a simulation subtask, in the step of suspending the simulation coroutine and switching to the verification coroutine associated with the running simulation coroutine:

[0066] According to the sorting relationship of the multiple verification coroutines corresponding to the multiple verification subtasks generated by the verification task associated with this simulation subtask, first switch to the verification coroutine ranked first. After the verification coroutine ranked first has finished running, then switch to the verification coroutine ranked later until all the verification coroutines corresponding to each verification subtask have finished running, and then switch back to the simulation coroutine corresponding to the simulation subtask.

[0067] Specifically, the advancement program of the digital design in this embodiment uses a digital clock program;

[0068] Synchronously run the associated simulation coroutine and verification coroutine at the rising edge or falling edge of each clock cycle of the digital clock program.

[0069] Specifically taking Figure 5 as an example, at the rising edge / falling edge of each clock cycle, the simulation coroutine corresponding to the simulation task can perform coroutine switching, yield the CPU usage right, and the verification coroutine of the verification task associated with this simulation task obtains the CPU usage right and can execute the verification of the current clock cycle;

[0070] After the verification of the current clock cycle is completed, if there are still verification subtasks that require logical calculation in this verification task, this verification coroutine also yields the CPU usage right through coroutine switching, and the verification coroutine corresponding to the verification subtask obtains the CPU usage right to perform the logical calculation of the current clock cycle;

[0071] Until all verification coroutines corresponding to the current verification task have completed running, the last running verification coroutine yields the CPU usage right through coroutine switching, and the corresponding simulation coroutine obtains the CPU usage right again. After the simulation coroutine completes the logical calculation of the current clock cycle, the simulation platform determines whether all simulation tasks have ended. If all have ended, this simulation is completed. If not, the simulation time axis of the digital clock program is advanced, and the simulation enters the next clock cycle.

[0072] For the traditional way of switching simulation tasks and verification tasks through multiple processes / threads, there is a certain task switching cost for each process / thread switch, as shown in Figure 6 shown.

[0073] Based on the embodiment of the present application, the simulation tasks and verification tasks are switched through coroutines. As shown in Figure 7 shown, the execution efficiency of coroutines is very high, without the overhead of process / thread switching. Compared with multiple processes / threads, the more the number of processes / threads, the more obvious the advantages of the same number of coroutines. And because there is only one process / thread, there is no conflict of writing variables at the same time. When controlling shared resources in a coroutine, there is no need to lock, only the state of the data needs to be judged, so the execution efficiency is much higher than that of processes / threads.

[0074] The present application also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the coroutine-based digital simulation verification method as described in any embodiment of the present invention.

[0075] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the coroutine-based digital simulation verification method as described in any embodiment of the present invention.

[0076] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent the cases of A existing alone, A and B existing simultaneously, and B existing alone. Wherein A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one of the following" and its similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, and c may represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c may be single or plural.

[0077] Those of ordinary skill in the art can realize that the units and algorithm steps described in the embodiments disclosed herein can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0078] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0079] In several embodiments provided by the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (hereinafter referred to as ROM), random access memories (hereinafter referred to as RAM), magnetic disks, or optical discs that can store program codes.

[0080] The above are only the embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A digital simulation verification method based on coroutines, characterized in that The following steps are involved: Build a simulation platform and a verification platform, and establish a data channel between the simulation platform and the verification platform; Based on digital design, confirm the associated simulation and verification tasks; Generate a simulation coroutine in a simulation platform according to the simulation task, generate a verification coroutine in a verification platform according to the verification task, and associate the simulation coroutine with the verification coroutine based on the associated simulation task and verification task; Based on the promotion program of digital design, the associated simulation coroutines and verification coroutines are run synchronously, and the data of the simulation coroutines and verification coroutines are transmitted through the data channel between the simulation platform and the verification platform to complete the simulation and verification of the digital design.

2. The digital simulation verification method based on coroutine according to claim 1, characterized in that The digital design-based advancement program synchronously runs the associated simulation coroutine and verification coroutine, and the steps of transmitting data of the simulation coroutine and the verification coroutine through the data channel between the simulation platform and the verification platform are specifically as follows: Run simulation programs based on digitally designed propulsion programs; After the simulation coroutine runs, the simulation platform gives the digital design an input data; Suspend the simulation coroutine and switch to the verification coroutine associated with the running simulation coroutine, the verification platform injects stimulus into the verification coroutine, samples the output data of the digital design of the simulation platform, verifies the output data, obtains the verification result, and switches back to the simulation coroutine after obtaining the verification result; The simulation coroutine performs logic simulation calculations based on the verification results.

3. A digital simulation verification method based on coroutine according to claim 2, characterized in that: Generate a simulation subtask based on the simulation task, and when there are multiple simulation subtasks, generate a sorting relationship corresponding to the multiple simulation subtasks; Generate a simulation coroutine corresponding to a simulation subtask; Generating a verification subtask based on the verification task, and when there are multiple verification subtasks, generating a sorting relationship corresponding to the multiple verification subtasks; A verification coroutine is generated for each verification subtask.

4. The digital simulation verification method based on coroutine according to claim 3 is characterized in that: When running the simulation coroutine, according to the order of the simulation subtasks, the simulation coroutine corresponding to the simulation subtask with the first order is selected to run; After the simulation coroutine is finished, wait for the running instruction of the next digital design advancement program, and continue to select the simulation coroutine corresponding to the simulation subtask with a lower ranking to run until the simulation coroutines corresponding to all simulation subtasks are finished.

5. A digital simulation verification method based on coroutines according to claim 3, characterized in that When a verification task associated with a simulation subtask has multiple verification subtasks, in the step of suspending the simulation coroutine and switching to the verification coroutine associated with the running simulation coroutine: According to the sorting relationship of multiple verification coroutines corresponding to multiple verification subtasks generated by the verification task associated with the simulation subtask, first switch to the verification coroutine with the first sorting, and then switch to the verification coroutine with the later sorting after the verification coroutine with the first sorting is completed, until all the verification coroutines corresponding to each verification subtask are completed, and then switch back to the simulation coroutine corresponding to the simulation subtask.

6. A digital simulation verification method based on coroutine according to claim 1, characterized in that: The advancement program is a digital clock program; Synchronously run the associated simulation coroutine and the verification coroutine at the rising edge or falling edge of each clock cycle of the digital clock program.

7. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that: When the processor executes the program, it implements the coroutine-based digital simulation verification method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by the processor, it implements the coroutine-based digital simulation verification method according to any one of claims 1 to 6.

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