Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: providing a bonding structure, wherein the bonding structure comprises a semiconductor structure, a bonding interface, a step region and a stacked structure arranged in sequence; removing part of the stacked structure, so that part of the surface of the step region away from the bonding interface is exposed, and the remaining stacked structure forms a plurality of spaced semiconductor parts, wherein each semiconductor part comprises a first conductive part, an insulating medium part and a second conductive part arranged in sequence, and part of the surface of each first conductive part away from the step region is exposed; forming a dielectric layer on the exposed surface of the bonding structure; forming a plurality of first conductive structures and a plurality of second conductive structures, wherein the first conductive structures penetrate the dielectric layer and are in one-to-one correspondence with the first predetermined surface, and the second conductive structures penetrate the dielectric layer and are in one-to-one correspondence with the surface of the second conductive part away from the insulating medium part. The method is beneficial to reducing the size of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the development of 3D NAND X-stacking technology, the number of memory layers is constantly increasing, requiring the size of CMOS (Complementary Metal Oxide Semiconductor) wafers to be continuously reduced. CMOS wafer area is gradually becoming a key factor restricting die size.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device and a semiconductor device in general, so as to at least partially solve the problem that the area of ​​3D NAND CMOS wafers is difficult to reduce in the prior art.

[0005] According to one aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided, comprising: providing a bonding structure, the bonding structure including a semiconductor structure, a bonding interface, a step region, and a stacked structure arranged sequentially, the stacked structure including a first conductive layer, an insulating dielectric layer, and a second conductive layer arranged sequentially; removing a portion of the stacked structure, such that a portion of the step region's surface away from the bonding interface is exposed, the remaining stacked structure forming a plurality of spaced semiconductor portions, each semiconductor portion including a first conductive portion, an insulating dielectric portion, and a second conductive portion arranged sequentially, and a first predetermined surface of each first conductive portion being exposed, the first predetermined surface being a portion of the first conductive portion's surface away from the step region; forming a dielectric layer on the exposed surface of the bonding structure; forming a plurality of first conductive structures and a plurality of second conductive structures, the first conductive structures penetrating the dielectric layer and correspondingly contacting the first predetermined surfaces, the second conductive structures penetrating the dielectric layer and correspondingly contacting the surfaces of the second conductive portions away from the insulating dielectric portions.

[0006] Optionally, removing a portion of the stacked structure exposes a portion of the surface of the stepped region away from the bonding interface, leaving the remaining stacked structure to form a plurality of spaced semiconductor portions. This includes: etching the stacked structure to form a plurality of holes, the holes exposing a portion of a second predetermined surface, the second predetermined surface being the surface of the stepped region away from the bonding interface; the remaining first conductive layer forming a plurality of first conductive portions; the remaining insulating dielectric layer forming a plurality of pre-insulating dielectric portions; and the remaining second conductive layer forming a plurality of second pre-conductive portions; sequentially removing portions of each of the second pre-conductive portions and portions of each of the pre-insulating dielectric portions, exposing the corresponding first predetermined surfaces; the remaining pre-insulating dielectric portions forming the insulating dielectric portions; and the remaining second pre-conductive portions forming the second conductive portions.

[0007] Optionally, etching the stacked structure to form a plurality of holes penetrating the surface of the stepped region away from the bonding interface includes: forming a first mask layer on the exposed surface of the stacked structure; using the first mask layer as a mask, etching the stacked structure to form the plurality of holes; and removing the first mask layer.

[0008] Optionally, sequentially removing portions of each of the pre-insulating dielectric portions and portions of each of the second pre-conductive portions to expose the corresponding first predetermined surfaces includes: forming a sacrificial layer on the exposed surface of the bonding structure where the holes are formed, the sacrificial layer filling each of the holes; forming a second mask layer on the exposed surface of the sacrificial layer; using the second mask layer as a mask, etching the sacrificial layer and the stacked structure to expose the portion of each pre-insulating dielectric portion away from the first conductive portion, the remaining second pre-conductive portions forming each second conductive portion; removing portions of each of the pre-insulating dielectric portions to expose each of the first predetermined surfaces, the remaining pre-insulating dielectric portions forming the insulating dielectric portion; and removing the remaining sacrificial layer.

[0009] Optionally, forming a plurality of first conductive structures and a plurality of second conductive structures includes: etching the bonding structure on which the dielectric layer is formed to form a plurality of first grooves and a plurality of second grooves, the first grooves penetrating to the first predetermined surface, and the second grooves penetrating to the surface of the second conductive portion away from the insulating dielectric portion; filling the first grooves and the second grooves with conductive materials respectively to form a first conductive pillar and a second conductive pillar; forming a first metal portion on the exposed surface of the first conductive pillar, the first metal portion and the first conductive pillar constituting the first conductive structure, and forming a second metal portion on the exposed surface of the second conductive pillar, the second metal portion and the second conductive pillar constituting the second conductive structure, wherein the first metal portion and the second metal portion are not in contact.

[0010] Optionally, a bonding structure is provided, comprising: providing a first structure to be bonded, the first structure to be bonded comprising the semiconductor structure and a first layer to be bonded sequentially disposed, the semiconductor structure comprising a first substrate; providing a second structure to be bonded, the second structure to be bonded comprising a second substrate, the stacked structure, the step region, and a second layer to be bonded sequentially disposed; bonding the first structure to be bonded and the second structure to be bonded using the first layer to be bonded and the second layer to be bonded as a bonding interface, the first layer to be bonded and the second layer to be bonded forming the bonding interface; removing at least a portion of the second substrate, thereby exposing the surface of the stacked structure away from the step region, to form the bonding structure.

[0011] Optionally, in any of the semiconductor device fabrication methods, the materials of the first conductive layer and the second conductive layer respectively include polycrystalline silicon, the material of the insulating dielectric layer includes silicon oxide, and the materials of the first conductive structure and the second conductive structure respectively include tungsten.

[0012] According to another aspect of the embodiments of this application, a semiconductor device is also provided, comprising: a semiconductor structure, a bonding interface, a step region, a plurality of spaced semiconductor portions, a dielectric layer, a plurality of first conductive structures, and a plurality of second conductive structures disposed sequentially, wherein each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion, and a first predetermined surface of each first conductive portion is exposed, the first predetermined surface being a portion of the first conductive portion away from the step region; the dielectric layer is located on the step region and the surface of each semiconductor portion away from the bonding interface; the first conductive structures penetrate the dielectric layer and are in contact with the first predetermined surfaces one by one, and the second conductive structures penetrate the dielectric layer and are in contact with the surfaces of the second conductive portions away from the insulating dielectric portions one by one.

[0013] Optionally, the first conductive structure includes a first conductive post and a first metal portion disposed in contact, the first metal portion being located on the surface of the first conductive post away from the semiconductor portion, and the second conductive structure includes a second conductive post and a second metal portion disposed in contact, the second metal portion being located on the surface of the second conductive post away from the semiconductor portion.

[0014] According to another aspect of the embodiments of this application, a memory is also provided, the memory including a semiconductor device formed using any of the described manufacturing methods or the semiconductor device and a memory array, the memory array being connected to the semiconductor device.

[0015] Optionally, the memory includes a three-dimensional NAND memory.

[0016] According to another aspect of the embodiments of this application, a storage system is also provided, the storage system including a controller and the memory, the controller being coupled to the memory and used to control the memory to store data.

[0017] According to another aspect of the embodiments of this application, an electronic device is also provided, the electronic device including the aforementioned memory.

[0018] Optionally, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

[0019] According to the technical solution of the embodiments of this application, in the method for fabricating the semiconductor device, firstly, a bonding structure is provided, comprising a semiconductor structure, a bonding interface, a step region, and a stacked structure arranged sequentially. The stacked structure includes a first conductive layer, an insulating dielectric layer, and a second conductive layer arranged sequentially. Secondly, a portion of the stacked structure is removed, exposing the surface of the step region away from the bonding interface. The remaining stacked structure forms a plurality of spaced semiconductor portions. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion arranged sequentially, and a first predetermined surface of each first conductive portion is exposed. Then, a dielectric layer is formed on the exposed surface of the bonding structure. Finally, a plurality of first conductive structures and a plurality of second conductive structures are formed, wherein the first conductive structures penetrate the dielectric layer and contact the first predetermined surfaces one by one, and the second conductive structures penetrate the dielectric layer and contact the surface of the second conductive portion away from the insulating dielectric portion (i.e., the upper surface of the second conductive portion). The method for fabricating the semiconductor device, by forming a capacitor structure on the stacked structure corresponding to the unused area of ​​the bonding structure, i.e. the step region, achieves the transfer of at least part of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, frees up part of the area in the semiconductor structure, which is beneficial to reduce the size of the semiconductor structure and ensures the utilization rate of the stacked structure. Attached Figure Description

[0020] The accompanying drawings, which form part of the embodiments of this application, are used to provide a further understanding of the embodiments of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. In the drawings:

[0021] Figure 1 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0022] Figure 2 A schematic diagram of the structure of a semiconductor device after bonding is shown in the method for fabricating a semiconductor device according to an embodiment of this application;

[0023] Figure 3 A schematic diagram of the structure of a semiconductor device fabrication method according to an embodiment of this application after the formation of the first mask layer is shown;

[0024] Figure 4 A schematic diagram of the structure of a semiconductor device after the formation of a hole is shown in the method for fabricating a semiconductor device according to an embodiment of this application;

[0025] Figure 5 A schematic diagram of the structure of a semiconductor device fabrication method according to an embodiment of this application after the formation of the second mask layer is shown;

[0026] Figure 6 A schematic diagram of the structure of a semiconductor device after the formation of the second conductive portion is shown in the method for fabricating a semiconductor device according to an embodiment of this application;

[0027] Figure 7 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0028] The above figures include the following reference numerals:

[0029] 10. Semiconductor structure; 101. First conductive layer; 102. Insulating dielectric layer; 103. Second conductive layer; 20. Bonding interface; 201. First conductive portion; 202. Insulating dielectric portion; 203. Second conductive portion; 30. Step region; 40. Stacked structure; 401. First mask layer; 402. Second mask layer; 403. Sacrificial layer; 404. Hole; 50. Dielectric layer; 60. First conductive structure; 61. Second conductive structure; 600. First conductive pillar; 601. Second conductive pillar; 602. First metal portion; 603. Second metal portion; 70. Source contact structure; 700. Third conductive pillar; 701. Fourth conductive pillar; 702. Third metal portion; 80. Contact hole connection structure; 800. Fifth conductive pillar; 801. Fourth metal portion. Detailed Implementation

[0030] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0035] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0036] As described in the background section, the main objective of the embodiments of this application is to provide a method for manufacturing a semiconductor device and a semiconductor device, so as to at least partially solve the problem that the area of ​​3D NAND CMOS wafer is difficult to reduce in the prior art.

[0037] According to a typical embodiment of the present application, a method for fabricating a semiconductor device is provided. Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, such as... Figure 1 As shown, the method for fabricating this semiconductor device includes the following steps:

[0038] Step S101, provide as follows Figure 2 The bonding structure shown includes a semiconductor structure 10, a bonding interface 20, a step region 30 and a stacked structure 40 arranged in sequence. The stacked structure 40 includes a first conductive layer 101, an insulating dielectric layer 102 and a second conductive layer 103 arranged in sequence.

[0039] Step S102, as follows Figures 3 to 7 As shown, by removing a portion of the stacked structure 40, the surface of the stepped region 30 away from the bonding interface 20 is exposed. The remaining stacked structure 40 forms a plurality of spaced semiconductor portions. Each semiconductor portion includes a first conductive portion 201, an insulating dielectric portion 202, and a second conductive portion 203 arranged sequentially. A first predetermined surface of each first conductive portion 201 is exposed. The first predetermined surface is the surface of the first conductive portion 201 away from the stepped region 30.

[0040] Step S103, as follows Figure 7 As shown, a dielectric layer 50 is formed on the exposed surface of the bonding structure;

[0041] Step S104: Multiple first conductive structures 60 and multiple second conductive structures 61 are formed, resulting in the following... Figure 7 In the structure shown, the first conductive structure 60 penetrates the dielectric layer 50 and is in contact with the first predetermined surface, and the second conductive structure 61 penetrates the dielectric layer 50 and is in contact with the surface of the second conductive portion 203 that is away from the insulating dielectric portion 202.

[0042] In the method for fabricating the semiconductor device, firstly, a bonding structure is provided, comprising a semiconductor structure, a bonding interface, a stepped region, and a stacked structure arranged sequentially. The stacked structure includes a first conductive layer, an insulating dielectric layer, and a second conductive layer arranged sequentially. Secondly, a portion of the stacked structure is removed, exposing the surface of the stepped region away from the bonding interface. The remaining stacked structure forms a plurality of spaced semiconductor portions. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion arranged sequentially, with a first predetermined surface of each first conductive portion exposed. Then, a dielectric layer is formed on the exposed surface of the bonding structure. Finally, a plurality of first conductive structures and a plurality of second conductive structures are formed, wherein the first conductive structures penetrate the dielectric layer and contact the first predetermined surfaces one by one, and the second conductive structures penetrate the dielectric layer and contact the surface of the second conductive portion away from the insulating dielectric portion (i.e., the upper surface of the second conductive portion). The method for fabricating the semiconductor device, by forming a capacitor structure on the stacked structure corresponding to the unused area of ​​the bonding structure, i.e. the step region, achieves the transfer of at least part of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, frees up part of the area in the semiconductor structure, which is beneficial to reduce the size of the semiconductor structure and ensures the utilization rate of the stacked structure.

[0043] In practical applications, the bonding structure is the structure obtained by bonding a CMOS wafer to an array wafer. The CMOS wafer includes the semiconductor structure, and the array wafer includes the stepped region and the stacked structure. The method described in this application facilitates the miniaturization of the CMOS wafer by transferring at least a portion of the capacitor structure from the CMOS wafer to the back side of the array wafer, effectively solving the problem of the difficulty in reducing the area of ​​3D NAND CMOS wafers in the prior art. Furthermore, the method utilizes the stacked structure corresponding to the stepped region of the array wafer to form the capacitor structure, ensuring a high utilization rate of the array wafer.

[0044] To facilitate the formation of the conductive portions, in one specific embodiment, a portion of the stacked structure is removed, exposing the surface of the stepped region 30 away from the bonding interface 20. The remaining stacked structure forms a plurality of spaced semiconductor portions, including: Figure 4 As shown, the stacked structure is etched to form multiple holes 404, which expose a portion of the second predetermined surface. The second predetermined surface is the surface of the stepped region 30 away from the bonding interface 20. The remaining first conductive layer 101 forms multiple first conductive portions 201, the remaining insulating dielectric layer 102 forms multiple pre-insulating dielectric portions, and the remaining second conductive layer 103 forms multiple second pre-conductive portions. Figure 6 As shown, portions of each of the second pre-conductive portions and portions of each of the pre-insulating dielectric portions are sequentially removed, exposing the corresponding first predetermined surfaces. The remaining pre-insulating dielectric portions form the insulating dielectric portion 202, and the remaining second pre-conductive portions form the second conductive portion 203. The etching process forms multiple spaced semiconductor portions in the stacked structure, i.e., forming the upper and lower plates of multiple capacitor structures and the insulating layer between the upper and lower plates, facilitating the subsequent formation of multiple capacitor structures on the back side of the bonding structure.

[0045] In one specific embodiment, the stacked structure is etched to form a plurality of holes penetrating to the surface of the stepped region away from the bonding interface, including: such as Figure 3 as well as Figure 4 As shown, a first mask layer 401 is formed on the exposed surface of the stacked structure; using the first mask layer as a mask, the stacked structure is etched to form a plurality of holes 404; the first mask layer is then removed. This process forms the lower electrode of a plurality of capacitor structures, thereby further facilitating the subsequent formation of capacitor structures.

[0046] According to another specific embodiment of the present application, portions of each of the prepared insulating dielectric portions and portions of each of the second prepared conductive portions are removed sequentially, exposing the corresponding first predetermined surface, including: as... Figure 4 as well as Figure 5 As shown, a sacrificial layer 403 is formed on the exposed surface of the bonding structure where the holes 404 are formed. The sacrificial layer 403 fills each of the holes 404. Optionally, the sacrificial layer 403 can completely fill each of the holes 404. A second mask layer 402 is formed on the exposed surface of the sacrificial layer 403. Using the second mask layer 402 as a mask, the sacrificial layer 403 and the stacked structure are etched so that the surface of each of the pre-insulating dielectric portions away from the first conductive portion 201 is exposed, and the remaining second pre-insulating dielectric portions form each second conductive portion 203. A portion of each of the pre-insulating dielectric portions is removed so that each of the first predetermined surfaces is exposed, and the remaining pre-insulating dielectric portions form the insulating dielectric portion 202. The remaining sacrificial layer 403 is removed to obtain... Figure 6 The structure shown further ensures that the first predetermined surface of the first conductive portion can be exposed more easily, and that the insulating dielectric portion and the second conductive portion can be formed.

[0047] It should be noted that the technical means of removing part of the stacked structure are not limited to the process described above, and those skilled in the art can also use other feasible methods in the prior art to achieve the same result.

[0048] In another specific embodiment of this application, each mask layer is a photoresist layer. There are many methods for forming the photoresist layer of this application embodiment, and those skilled in the art can choose a suitable method to form the photoresist layer of this application embodiment according to the actual situation. The sacrificial layer is an N-well extraction layer.

[0049] To facilitate the formation of each of the first conductive structures and each of the second conductive structures, according to another specific embodiment of the present application, a plurality of first conductive structures and a plurality of second conductive structures are formed, such as... Figure 7As shown, the process includes: etching the bonding structure on which the dielectric layer 50 is formed to form a plurality of first grooves and a plurality of second grooves, the first grooves penetrating to the first predetermined surface, and the second grooves penetrating to the surface of the second conductive portion 203 away from the insulating dielectric portion 202; filling the first grooves and the second grooves with conductive material to form a first conductive post 600 and a second conductive post 601 respectively; forming a first metal portion 602 on the exposed surface of the first conductive post 600, the first metal portion 602 and the first conductive post 600 constituting the first conductive structure 60; and forming a second metal portion 603 on the exposed surface of the second conductive post 601, the second metal portion 603 and the second conductive post 601 constituting the second conductive structure 61, wherein the first metal portion 602 and the second metal portion 603 are not in contact. The process of forming a plurality of first conductive structures and a plurality of second conductive structures realizes the connection between the capacitor structure and the outside.

[0050] Those skilled in the art can choose any feasible method in the prior art to form the first metal part and the second metal part. In a specific embodiment, forming the first metal part and the second metal part includes: sequentially forming a metal layer and a mask on the dielectric layer 50; using the mask as a mask, etching the metal layer to form a plurality of first metal parts and a plurality of second metal parts; and removing the mask.

[0051] In addition, such as Figure 7As shown, during the etching of the bonding structure on which the dielectric layer is formed to form a plurality of first grooves and a plurality of second grooves, a third groove, a fourth groove, and a fifth groove are also formed. The third groove and the fourth groove penetrate the dielectric layer 50 to the surface of the second conductive layer 103, respectively, and the fifth groove penetrates the dielectric layer 50, the stacked structure 40, and the surface of the contact hole CL. Conductive material is filled into the third groove, the fourth groove, and the fifth groove to form a third conductive post 700, a fourth conductive post 701, and a fifth conductive post 800, respectively, wherein the fifth conductive post 800 contacts the contact hole CL. A third metal portion 702 is formed on the exposed surface of the fourth conductive post 700 and the fourth conductive post 701. The third metal portion 702 is in contact with the third conductive post 700 and the fourth conductive post 701 respectively. The third conductive post 700, the fourth conductive post 701 and the third metal portion 702 constitute a source contact structure 70. The source contact structure 70 is used to connect the source of the array wafer in the bonding structure. A fourth metal portion 801 is formed on the exposed surface of the fifth conductive post 800. The fourth metal portion 801 and the fifth conductive post 800 constitute the contact hole connection structure 80. The contact hole connection structure 80 is used to connect the contact hole of the array wafer in the bonding structure.

[0052] In practical applications, the materials of the first metal part and the second metal part can be any feasible metal material in the prior art. In one specific embodiment, the materials of the first metal part and the second metal part respectively include aluminum. In a more specific embodiment, the materials of both the first metal part and the second metal part are aluminum.

[0053] According to another specific embodiment of the present application, a bonding structure is provided, comprising: providing a first structure to be bonded, the first structure to be bonded comprising the semiconductor structure and a first layer to be bonded sequentially disposed, the semiconductor structure comprising a first substrate; providing a second structure to be bonded, the second structure to be bonded comprising a second substrate, the stacked structure, the step region, and the second layer to be bonded sequentially disposed; bonding the first structure to be bonded and the second structure to be bonded using the first layer to be bonded and the second layer to be bonded as a bonding interface, the first layer to be bonded and the second layer to be bonded forming the bonding interface; removing at least a portion of the second substrate, thereby exposing the surface of the stacked structure away from the step region, to form the bonding structure.

[0054] In one specific embodiment, such as Figures 2 to 7As shown, the bonding structure is an array backside source connection structure. The first structure to be bonded is a CMOS wafer, and the second structure to be bonded is an array wafer. The semiconductor structure of the CMOS wafer includes a stacked structure, contact holes (CTs), gate lines (GLs), dummy channel holes (DCHs), and channel holes (CHs). The stacked structure includes alternately arranged metal gates and insulating dielectric layers, and the stacked structure includes the stepped region.

[0055] It should be noted that each step in the substrate formation embodiment can be implemented using feasible methods in the prior art. The substrate in the substrate can be selected according to the actual needs of the device, and may include a silicon substrate, a germanium substrate, a silicon-germanium composite, an SOI (Silicon on Insulator) substrate, or a GOI (Germanium on Insulator) substrate. In other embodiments, the substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon on Germanium Insulator). Of course, it may also be other substrates feasible in the prior art.

[0056] Those skilled in the art can remove part of the second substrate by means of etching or chemical mechanical polishing. Of course, the technical means of removing part of the second substrate are not limited to the process described above. Those skilled in the art can also use other feasible methods in the prior art to achieve at least partial removal of the second substrate.

[0057] In practical applications, the first conductive layer and the second conductive layer are each made of polycrystalline silicon, the insulating dielectric layer is made of silicon oxide, and the first conductive structure and the second conductive structure are each made of tungsten. In a more specific embodiment, the first conductive layer and the second conductive layer are each made of doped polycrystalline silicon, and the insulating dielectric layer is made of silicon oxide.

[0058] It should be noted that the second structure to be bonded already includes a first polysilicon layer and a second polysilicon layer. Through polysilicon doping, the conductivity of the first and second polysilicon layers can be achieved, resulting in a first conductive layer and a second conductive layer. This further ensures a high utilization rate of the second structure to be bonded. It should also be noted that during the fabrication of the second structure to be bonded, the first and second polysilicon layers can be made to a predetermined thickness to facilitate subsequent capacitor formation.

[0059] These structural layers may be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0060] According to another typical embodiment of the present application, a semiconductor device is also provided, which is fabricated using any of the semiconductor device fabrication methods described above.

[0061] The semiconductor device is fabricated using any of the fabrication methods described above. The fabrication method forms a capacitor structure on the stacked structure corresponding to the unused area of ​​the bonding structure, i.e. the step area, thereby transferring at least part of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, frees up some area in the semiconductor structure, which is beneficial to reducing the size of the semiconductor structure and ensuring the utilization rate of the stacked structure.

[0062] According to another typical embodiment of the present application, a semiconductor device is also provided, such as... Figure 7 As shown, the structure includes: a semiconductor structure 10, a bonding interface 20, a stepped region 30, multiple spaced semiconductor portions, a dielectric layer 50, multiple first conductive structures 60, and multiple second conductive structures 61 arranged sequentially. Each semiconductor portion includes a first conductive portion 201, an insulating dielectric portion 202, and a second conductive portion 203. A first predetermined surface of each first conductive portion 201 is exposed, and the first predetermined surface is a portion of the first conductive portion 201 that is away from the stepped region 30. The dielectric layer 50 is located on the stepped region 30 and on the surface of each semiconductor portion that is away from the bonding interface 20. Each first conductive structure 60 penetrates the dielectric layer 50 and is in contact with the first predetermined surface. Each second conductive structure 61 penetrates the dielectric layer 50 and is in contact with the surface of the second conductive portion 203 that is away from the insulating dielectric portion 202.

[0063] The semiconductor device includes a semiconductor structure, a bonding interface, a stepped region, multiple spaced semiconductor portions, a dielectric layer, multiple first conductive structures, and multiple second conductive structures arranged sequentially. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion. The first conductive structures penetrate the dielectric layer and make corresponding contacts with a first predetermined surface. The second conductive structures penetrate the dielectric layer and make corresponding contacts with the surfaces of the second conductive portions away from the insulating dielectric portions. By forming a capacitor structure on the unused area of ​​the bonding structure, i.e., on the stacked structure corresponding to the stepped region, the semiconductor device achieves the transfer of at least a portion of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, freeing up some area in the semiconductor structure, which is beneficial for reducing the size of the semiconductor structure and ensuring the utilization rate of the stacked structure.

[0064] In one specific embodiment, the first conductive structure includes a first conductive post and a first metal portion disposed in contact, the first metal portion being located on the surface of the first conductive post away from the semiconductor portion; the second conductive structure includes a second conductive post and a second metal portion disposed in contact, the second metal portion being located on the surface of the second conductive post away from the semiconductor portion.

[0065] According to another typical embodiment of the present application, a memory is also provided, the memory including a semiconductor device formed by any of the manufacturing methods described above, or the semiconductor device and a memory array, the memory array being connected to the semiconductor device.

[0066] Specifically, the memory includes a three-dimensional NAND memory.

[0067] According to another typical embodiment of the present application, a storage system is also provided, the storage system including a controller and the memory, the controller being coupled to the memory and used to control the memory to store data.

[0068] According to another typical embodiment of the present application, an electronic device is also provided, the electronic device including the aforementioned memory.

[0069] Optionally, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

[0070] As can be seen from the above description, the embodiments described in this application achieve the following technical effects:

[0071] 1) In the method for fabricating a semiconductor device according to the embodiments of this application, a bonding structure is first provided, comprising a semiconductor structure, a bonding interface, a step region, and a stacked structure arranged sequentially. The stacked structure includes a first conductive layer, an insulating dielectric layer, and a second conductive layer arranged sequentially. Next, a portion of the stacked structure is removed, exposing a portion of the surface of the step region away from the bonding interface. The remaining stacked structure forms a plurality of spaced semiconductor portions. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion arranged sequentially, and a first predetermined surface of each first conductive portion is exposed. Then, a dielectric layer is formed on the exposed surface of the bonding structure. Finally, a plurality of first conductive structures and a plurality of second conductive structures are formed, wherein the first conductive structures penetrate the dielectric layer and contact the first predetermined surfaces one by one, and the second conductive structures penetrate the dielectric layer and contact the surface of the second conductive portion away from the insulating dielectric portion (i.e., the upper surface of the second conductive portion). The method for fabricating the semiconductor device, by forming a capacitor structure on the stacked structure corresponding to the unused area of ​​the bonding structure, i.e. the step region, achieves the transfer of at least part of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, frees up part of the area in the semiconductor structure, which is beneficial to reduce the size of the semiconductor structure and ensures the utilization rate of the stacked structure.

[0072] 2) The semiconductor device described in this application embodiment is fabricated using any of the fabrication methods described above. The fabrication method forms a capacitor structure on the stacked structure corresponding to the unused area of ​​the bonding structure, i.e. the step area, thereby transferring at least part of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, frees up part of the area in the semiconductor structure, which is beneficial to reducing the size of the semiconductor structure and ensuring the utilization rate of the stacked structure.

[0073] 3) The semiconductor device described in this application includes a semiconductor structure, a bonding interface, a stepped region, multiple spaced semiconductor portions, a dielectric layer, multiple first conductive structures, and multiple second conductive structures arranged sequentially. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion. The first conductive structures penetrate the dielectric layer and are in contact with a first predetermined surface. The second conductive structures penetrate the dielectric layer and are in contact with a surface of the second conductive portion away from the insulating dielectric portion. By forming a capacitor structure on the unused area of ​​the bonding structure, i.e., on the stacked structure corresponding to the stepped region, the semiconductor device achieves the transfer of at least a portion of the capacitor structure from the semiconductor structure to the back side of the bonding structure. This ensures that the area occupied by the capacitor in the semiconductor structure is small, freeing up some area in the semiconductor structure, which is beneficial for reducing the size of the semiconductor structure and ensuring the utilization rate of the stacked structure.

[0074] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations can be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of the present application should be included within the protection scope of the embodiments of the present application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A bonding structure is provided, the bonding structure comprising a semiconductor structure, a bonding interface, a step region and a stacked structure arranged sequentially, the stacked structure comprising a first conductive layer, an insulating dielectric layer and a second conductive layer arranged sequentially. By removing part of the stacked structure, the surface of the step region away from the bonding interface is exposed, and the remaining stacked structure forms a plurality of spaced semiconductor portions. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion arranged in sequence, and a first predetermined surface of each first conductive portion is exposed. The first predetermined surface is the surface of the first conductive portion away from the step region. A dielectric layer is formed on the exposed surface of the bonding structure; Multiple first conductive structures and multiple second conductive structures are formed. The first conductive structures penetrate the dielectric layer and are in contact with the first predetermined surface. The second conductive structures penetrate the dielectric layer and are in contact with the surface of the second conductive portion away from the insulating dielectric portion.

2. The method according to claim 1, characterized in that, Removing a portion of the stacked structure exposes the surface of the stepped region away from the bonding interface, leaving the remaining stacked structure forming a plurality of spaced semiconductor portions, including: The stacked structure is etched to form a plurality of holes, the holes exposing a portion of the second predetermined surface, the second predetermined surface being the surface of the step region away from the bonding interface, the remaining first conductive layer forming a plurality of first conductive portions, the remaining insulating dielectric layer forming a plurality of pre-insulating dielectric portions, and the remaining second conductive layer forming a plurality of second pre-conductive portions. Sequentially remove portions of each of the second pre-conductive portions and portions of each of the pre-insulating dielectric portions, exposing the corresponding first predetermined surfaces. The remaining pre-insulating dielectric portions form the insulating dielectric portions, and the remaining second pre-conductive portions form the second conductive portions.

3. The method according to claim 2, characterized in that, Etching the stacked structure to form multiple holes penetrating the surface of the stepped region away from the bonding interface, including: A first mask layer is formed on the exposed surface of the stacked structure; Using the first mask layer as a mask, the stacked structure is etched to form a plurality of holes; Remove the first mask layer.

4. The method according to claim 2, characterized in that, Sequentially removing each of the pre-insulating dielectric portions and each of the second pre-conductive portions, so that the corresponding first predetermined surface is exposed, includes: A sacrificial layer is formed on the exposed surface of the bonded structure in which the pores are formed, the sacrificial layer filling each of the pores; A second mask layer is formed on the exposed surface of the sacrificial layer; Using the second mask layer as a mask, the sacrificial layer and the stacked structure are etched so that the surface of each of the pre-insulating dielectric portions away from the first conductive portion is exposed, and the remaining second pre-conductive portions form each second conductive portion. Remove portions of each of the pre-insulating dielectric portions to expose each of the first predetermined surfaces, and the remaining portions of each of the pre-insulating dielectric portions form the insulating dielectric portion; Remove the remaining sacrificial layer.

5. The method according to claim 1, characterized in that, Forming multiple first conductive structures and multiple second conductive structures, including: The bonding structure on which the dielectric layer is formed is etched to form a plurality of first grooves and a plurality of second grooves, the first grooves extending to the first predetermined surface and the second grooves extending to the surface of the second conductive portion away from the insulating dielectric portion; Conductive material is filled into the first groove and the second groove respectively to form a first conductive pillar and a second conductive pillar. A first metal portion is formed on the exposed surface of the first conductive post, the first metal portion and the first conductive post constituting the first conductive structure, and a second metal portion is formed on the exposed surface of the second conductive post, the second metal portion and the second conductive post constituting the second conductive structure, wherein the first metal portion and the second metal portion do not contact each other.

6. The method according to claim 1, characterized in that, Provides bonding structures, including: A first structure to be bonded is provided, the first structure to be bonded includes the semiconductor structure and the first layer to be bonded sequentially disposed therefrom, the semiconductor structure including a first substrate; A second structure to be bonded is provided, the second structure to be bonded includes a second substrate, the stacked structure, the stepped region and the second layer to be bonded, which are arranged sequentially. Using the first layer to be bonded and the second layer to be bonded as bonding interfaces, the first structure to be bonded and the second structure to be bonded are bonded together, and the first layer to be bonded and the second layer to be bonded together form the bonding interface; At least a portion of the second substrate is removed, exposing the surface of the laminated structure away from the step region, to form the bonding structure.

7. The method according to any one of claims 1 to 6, characterized in that, The first conductive layer and the second conductive layer are respectively made of polycrystalline silicon, the insulating dielectric layer is made of silicon oxide, and the first conductive structure and the second conductive structure are respectively made of tungsten.

8. A semiconductor device, characterized in that, include: A semiconductor structure, a bonding interface, a step region, and a plurality of spaced semiconductor portions are arranged sequentially. Each semiconductor portion includes a first conductive portion, an insulating dielectric portion, and a second conductive portion. A first predetermined surface of each first conductive portion is exposed. The first predetermined surface is a portion of the first conductive portion that is away from the step region. A dielectric layer is located on the stepped region and on the surface of each of the semiconductor portions away from the bonding interface; The device includes a plurality of first conductive structures and a plurality of second conductive structures. The first conductive structures penetrate the dielectric layer and are in contact with the first predetermined surface in a corresponding manner. The second conductive structures penetrate the dielectric layer and are in contact with the surface of the second conductive portion away from the insulating dielectric portion in a corresponding manner.

9. The semiconductor device according to claim 8, characterized in that, The first conductive structure includes a first conductive post and a first metal portion disposed in contact, the first metal portion being located on the surface of the first conductive post away from the semiconductor portion. The second conductive structure includes a second conductive post and a second metal portion disposed in contact, the second metal portion being located on the surface of the second conductive post away from the semiconductor portion.

10. A memory, characterized in that, include: A semiconductor device formed by the manufacturing method according to any one of claims 1 to 7, or a semiconductor device according to claim 8 or 9; as well as, A storage array connected to the semiconductor device.

11. The memory according to claim 10, characterized in that, The memory includes a three-dimensional NAND memory.

12. A storage system, characterized in that, It includes a controller and the memory as described in claim 10 or 11, the controller being coupled to the memory and used to control the memory to store data.

13. An electronic device, characterized in that, include: The memory according to claim 10 or 11.

14. The electronic device according to claim 13, characterized in that, The electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

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