A feedback type two-terminal fuse memory cell and a manufacturing method thereof

Abstract

The present invention discloses a feedback two-terminal fuse memory cell and a preparation method thereof. Based on the traditional two-terminal fuse, the feedback two-terminal fuse memory cell of the present invention adds a vertical metal gate, and the gate is made on the drain side and electrically connected to the drain. After applying a voltage at the drain end, a lateral voltage VDS and a vertical voltage VGS will be generated simultaneously, and the magnitudes of the two voltages are equal. By reasonably designing the thickness of the gate oxide layer, the breakdown from the gate to the channel in the vertical direction can occur first. The breakdown in the vertical direction is achieved through the tunneling current from the gate to the channel. This design can reduce the programming voltage and programming current and achieve mild low power consumption. The present invention uses electron beam lithography and lift-off processes to realize the preparation of the fuse memory cell. The process is simple, can realize the preparation of large-area devices and save process costs.

Description

Technical Field

[0001] The present invention relates to a nano-semiconductor device and a preparation method thereof, and particularly to a feedback type two-terminal fuse device and a preparation method thereof. Background Art

[0002] One-time programmable memory is a type of non-volatile memory. During application, it only allows one-time writing, and the information cannot be changed once written. Generally speaking, it currently has two forms: fuse and antifuse. Due to its one-time programming characteristic, it has more advantages in terms of reliability and security. It can be integrated inside one-time programmable memories such as FPGA and PROM (programmable read only memory), and is widely used in high-reliability fields such as aerospace and military FPGA.

[0003] Traditional electric fuse (e-Fuse) has a two-terminal structure, including an anode, a cathode, and a thin strip-shaped fuse connecting the anode and the cathode. The device is in a conducting state before programming. During programming, a transient large current is used to burn out the fuse, achieving the conversion from low resistance (logic 1) to high resistance (logic 0) through current. The fuse is equivalent to a resistor before programming and equivalent to a capacitor after programming.

[0004] The physical mechanism of traditional fuses is based on the electromigration effect. When the device works, electrons in the metal wire generate electron migration under the action of a large current, and metal ions generate mass transport along the conductor, causing voids or whiskers (hills) in certain parts of the conductor, and the metal wire breaks to form a high-resistance state; traditional two-terminal fuses require a large current or a large voltage for programming, and at the same time, they rely on heat for programming, and heat accumulation is required during programming, resulting in slow programming speed and high power consumption;

[0005] Therefore, how to obtain a fuse device with low programming voltage and low power consumption and be compatible with the CMOS process is a major problem currently faced. Summary of the Invention

[0006] In view of the above problems existing in the prior art, in order to obtain a fuse device with low programming voltage and low power consumption, the present invention proposes a graphene-based feedback type two-terminal fuse storage unit and a preparation method thereof. The technical solution of the present invention is as follows:

[0007] An embodiment of the first aspect of the present invention proposes a feedback type two-terminal fuse storage unit, which has a substrate. A graphene channel is provided on the substrate. A drain and a source are respectively provided at both ends of the graphene channel. A gate window is formed between the drain and the source. A metal gate in electrical contact with the drain is provided at the drain end of the gate window. There is a gate oxide layer between the metal gate (5) and the graphene channel.

[0008] In an embodiment of the first aspect of the present invention, the graphene channel is monolayer graphene or a graphene nanoribbon.

[0009] In an embodiment of the first aspect of the present invention, the metal gate is a metal Al gate, and the gate oxide layer is Al2O3.

[0010] In an embodiment of the first aspect of the present invention, the drain or source is a single-layer or double-layer structure composed of Ti and Au.

[0011] In an embodiment of the first aspect of the present invention, the metal gate is perpendicular to the extension direction of the graphene channel.

[0012] An embodiment of the second aspect of the present invention provides a method for fabricating a feedback two-terminal fuse memory cell, including the following steps:

[0013] Provide a substrate and form a graphene channel on the substrate;

[0014] Deposit a drain and a source at both ends of the graphene channel to form a gate window;

[0015] Deposit a dielectric layer on the gate window, the drain, and the source, pattern the dielectric layer, and etch it to expose part of the drain and the source;

[0016] Form a metal gate at one end of the drain, and the metal gate makes electrical contact with the drain.

[0017] In an embodiment of the second aspect of the present invention, a graphene material is formed on the substrate by mechanical exfoliation or CVD in-situ growth, and then the graphene material is patterned and etched to form the graphene channel.

[0018] In an embodiment of the second aspect of the present invention, the gate window is patterned by electron beam lithography, and then the gate metal Al is deposited by electron beam evaporation to form the metal gate.

[0019] An embodiment of the third aspect of the present invention provides another method for fabricating a feedback two-terminal fuse memory cell, including the following steps:

[0020] Provide a substrate and transfer a graphene channel onto the substrate;

[0021] Deposit a drain and a source at both ends of the graphene channel to form a gate window;

[0022] Deposit a metal gate that makes electrical contact with the drain between the gate windows;

[0023] Through annealing oxidation, an oxide layer is formed on the surface of the metal gate, and a gate oxide layer is formed at the interface between the graphene channel and the metal gate.

[0024] In the embodiment of the third aspect of the present invention, an oxide layer is formed on the surface of the above-mentioned metal gate by annealing at a temperature of 120°C - 150°C for 30 - 60 minutes, and at the same time, the above-mentioned gate oxide layer is formed at the interface between the above-mentioned graphene channel and the above-mentioned metal gate.

[0025] Based on the traditional two-terminal fuse, the present invention adds a vertical metal gate and makes the gate on the drain side and connect it to the drain electrode. For the device after the gate and the drain are electrically connected, there will be a competition between two working mechanisms. One is the traditional two-terminal fuse based on the electromigration effect ( Figure 1 ), applying a large lateral voltage VDS (about 10V) across the source and drain to blow the fuse and achieve programming; the other is the tunneling in the vertical direction ( Figure 2 ), applying a voltage VGS (about 4V) on the gate to blow the channel through the tunneling current from the gate to the channel. By reasonably designing the thickness of the gate oxide layer, the vertical tunneling mechanism can occur first. The main advantages of the fuse storage unit of the present invention are as follows: First, compared with the traditional two-terminal fuse, it can reduce the programming voltage and programming current and reduce power consumption; second, compared with the three-terminal vertical fuse, the two-terminal vertical fuse is simpler electrically and easier to integrate. Description of the Drawings

[0026] By describing the technical solutions of the present invention with reference to the following drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0027] Figure 1 is the structure of a traditional two-terminal fuse device;

[0028] Figure 2 is the structure of a conventional three-terminal fuse device;

[0029] Figure 3 is the three-dimensional structure diagram of the feedback two-terminal fuse storage unit of the present invention;

[0030] Figure 4 is the step of forming a graphene channel on the substrate in Embodiment 2;

[0031] Figure 5 is the step of depositing source and drain electrodes in Embodiment 2;

[0032] Figure 6 is the step of depositing a dielectric layer in Embodiment 2;

[0033] Figure 7 is the step of forming a photolithography mask pattern in Embodiment 2

[0034] Figure 8 is the step of etching part of the dielectric layer in Embodiment 2;

[0035] Figure 9 The step of forming a metal gate at the drain end in Example 2;

[0036] Figure 10 Schematic diagram of the graphene channel fusing after programming the memory cell in Example 2;

[0037] Figure 11 The step of depositing a metal Al gate in Example 3;

[0038] Figure 12 The step of annealing and oxidizing to form a gate oxide layer in Example 3;

[0039] Figure 13 Schematic diagram of the graphene channel fusing after programming the memory cell in Example 3; Detailed implementation manners

[0040] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals, and the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps may be described in one drawing.

[0041] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "on top of" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0042] If it is to describe the case of being directly above another layer or another region, the expression "A is directly on top of B" or "A is on top of B and adjacent thereto" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0043] Example 1

[0044] An embodiment of the present invention provides a feedback type two-terminal fuse memory cell, as Figure 3As shown, there is a substrate 1, on which there is a graphene channel 2. At both ends of the graphene channel 2, there are a drain 3 and a source 4 respectively. A gate window is formed between the drain 3 and the source 4. In the gate window, there is a metal gate 5. The metal gate 5 is perpendicular to the extension direction of the graphene channel 2 and is in electrical contact with the above-mentioned drain. An oxide layer is formed on the outer surface of the metal gate 5, and there is a gate oxide layer between the metal gate 5 and the graphene channel 2. In this embodiment, the graphene channel 2 is a single-layer graphene material. In another embodiment, the above-mentioned graphene channel 2 is a graphene nanoribbon. At both ends of the above-mentioned graphene channel 2, there are a drain 3 and a source 4 respectively. A gate window is formed between the above-mentioned drain 3 and the above-mentioned source 4. In the above-mentioned gate window, there is a metal gate 5. The metal gate 5 is perpendicular to the extension direction of the graphene 2 and is in electrical contact with the above-mentioned drain 3.

[0045] In this embodiment, the metal gate 5 is a metal Al gate, and the metal Al gate is in electrical contact with the drain 3. A dense aluminum oxide thin film is formed on the upper surface of the metal Al gate and the overlapping area between the metal Al gate and the graphene channel. The structural schematic diagram of the gate window is as Figure 3 shown. The aluminum oxide thin film between the metal Al gate and the graphene channel serves as the gate oxide layer 6 of the fuse memory cell. The above-mentioned drain 3 or source 4 can be of the same material. In this embodiment, it is a bilayer structure composed of Ti and Au. In other embodiments, the drain 3 or source 4 can be a single-layer structure of Ti or Au.

[0046] Embodiment 2

[0047] This embodiment proposes a preparation method for a feedback two-terminal fuse memory cell, including the following steps:

[0048] For the subsequent micro-nano processing and pattern alignment of the device, first make a mark on the substrate. Because titanium has strong adhesion to the substrate, 5nm titanium and 50nm gold are used to make the mark to prevent the mark from falling off.

[0049] As Figure 4 shown, provide a silicon oxide substrate 101, and transfer a layer of graphene material on the silicon oxide substrate 101. Specifically, first obtain the graphene material by in-situ CVD growth on a copper foil, and then transfer the graphene material on the copper foil to the silicon oxide substrate. The above-mentioned graphene material is patterned and etched by electron beam lithography (EBL) and inductively coupled plasma etching (ICP) respectively to obtain the graphene channel 102. In other embodiments, the graphene material can be transferred by mechanical exfoliation, then patterning and etching are not required, and the graphene is positioned by an optical microscope, and then the source-drain electrodes are placed on the graphene material.

[0050] As Figures 5 - 9As shown, the source and drain electrodes are patterned by electron beam lithography, and then the contact metal layers Ti and Au are deposited by electron beam evaporation to form the above-mentioned drain 103 and source 104, and a gate window is formed at the same time. Then, a dielectric layer is deposited on the above-mentioned gate window, drain and source by a conventional thin film deposition process. The thickness of the dielectric layer is 1 nm - 5 nm, and its material can be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, yttrium oxide, lanthanum oxide or titanium oxide, etc. Subsequently, part of the dielectric layer is etched through a photolithographic mask to expose part of the source and drain. Then, the gate window is patterned by electron beam lithography, and then a metal layer Al is deposited between the drain 103 and the source 104 by electron beam evaporation to form a metal gate 105, and the metal gate Al is electrically contacted with the drain 103.

[0051] Figure 10 It is a schematic diagram of the graphene channel fusing after programming the storage cell in this embodiment. By applying a voltage, tunneling electrons are generated from the gate, breaking the covalent bonds of graphene, and small cracks appear between the channel under the gate and the source and drain. The graphene is burned out, and the source-drain resistance increases, showing a high resistance state (storing 0), thus realizing the one-time programming from the low resistance state to the high resistance state.

[0052] Embodiment 3

[0053] Another preparation method of a feedback type two-terminal fuse storage cell is proposed in this embodiment, and the specific steps are as follows:

[0054] The graphene channel 202, drain 203 and source 204 are formed on the substrate 201 according to the steps in Embodiment 2. Then as Figure 11 shown, the gate window is patterned by electron beam lithography, and then a metal layer Al is deposited between the drain 203 and the source 204 by electron beam evaporation to form a metal gate 205, and the metal gate Al is electrically contacted with the drain 203.

[0055] Furthermore, as Figure 12 shown, the structure formed in the above steps is annealed and oxidized at a temperature of 120°C - 150°C for 30 - 60 minutes. In this embodiment, it is baked at 150°C for 40 minutes to form a dense metal oxide film at the interface between the graphene channel 202 and the metal gate 205. Among them, the gate of the fuse storage cell is a metal Al gate. The metal Al is deposited on the graphene channel 202, and then the device is baked at 150°C for 40 minutes through annealing oxidation, and a dense aluminum oxide film can be generated on the outer surface of the metal gate 205 and the overlapping area between the metal gate 205 and the graphene channel 202. The aluminum oxide film between Al and graphene serves as the gate oxide layer of the fuse storage cell. Figure 13Schematic diagram of graphene channel fusing after programming a memory cell. The initial state of the device is the low-resistance state (storing 1). During programming, the tunneling current from the gate to the channel burns through the graphene, creating a small crack between the channel under the gate and the source-drain electrodes. The graphene is burned through, increasing the source-drain resistance and presenting the high-resistance state (storing 0), thus achieving a one-time programming from the low-resistance state to the high-resistance state.

[0056] In summary, compared with traditional two-terminal fuses, the feedback two-terminal fuse memory cell provided by the present invention can reduce the programming voltage and current, and reduce power consumption. Secondly, compared with three-terminal vertical fuses, the two-terminal vertical fuses are electrically simpler and easier to integrate.

[0057] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made based on the present invention, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection of the present invention.

Claims

1. A feedback two-terminal fuse memory cell, characterized in that it has a substrate, on which there is a graphene channel, and a drain and a source are respectively arranged at both ends of the graphene channel; there is a gate window between the drain and the source, at the drain end of the gate window there is a metal gate in electrical contact with the drain, there is a gate oxide layer between the metal gate and the graphene channel, the metal gate is a metal Al gate, and a dense aluminum oxide film is formed on the upper surface of the metal Al gate and the overlapping area between the metal Al gate and the graphene channel; by applying a voltage, tunneling electrons are generated from the gate, breaking the covalent bonds of graphene, small cracks appear between the channel under the gate and the source-drain electrodes, the graphene is burned out, and the source-drain resistance increases, showing a high-resistance state, thus realizing one-time programming from a low-resistance state to a high-resistance state.

2. The feedback type two-terminal fuse memory cell according to claim 1, characterized in that The graphene channel is a single-layer graphene or a graphene nanoribbon.

3. The feedback type two-terminal fuse memory cell according to claim 1, wherein The gate oxide layer is Al2O3.

4. The feedback type two-terminal fuse memory cell according to claim 1, characterized in that , the drain or the source is a single-layer or double-layer structure composed of Ti and Au.

5. The feedback type two-terminal fuse memory cell according to claim 1, characterized in that , the metal gate is perpendicular to the extension direction of the graphene channel.

6. A method for fabricating a feedback two-terminal fuse memory cell according to any one of claims 1-5, characterized in that, It includes the following steps: Provide a substrate and form a graphene channel on the substrate; Deposit a drain and a source at both ends of the graphene channel to form a gate window; Deposit a dielectric layer on the gate window and its drain and source, pattern the dielectric layer and etch it to expose part of the drain and the source; Form a metal gate at one end of the drain, the metal gate is in electrical contact with the drain, the metal gate is a metal Al gate, and a dense aluminum oxide film is formed on the upper surface of the metal Al gate and the overlapping area between the metal Al gate and the graphene channel; by applying a voltage, tunneling electrons are generated from the gate, breaking the covalent bonds of graphene, small cracks appear between the channel under the gate and the source-drain electrodes, the graphene is burned out, and the source-drain resistance increases, showing a high-resistance state, thus realizing one-time programming from a low-resistance state to a high-resistance state.

7. The preparation method of the feedback type two-terminal fuse memory cell according to claim 6, characterized in that, Form a graphene material on the substrate by mechanical exfoliation or CVD in-situ growth, and then pattern and etch the graphene material to form the graphene channel.

8. The preparation method of the feedback type two-terminal fuse memory cell according to claim 6, wherein, Pattern the gate window by electron beam lithography, and then deposit the gate metal Al by electron beam evaporation to form the metal gate.

9. A method for fabricating a feedback type two-terminal fuse memory cell as claimed in any one of claims 1-5, characterized in that, It includes the following steps: Provide a substrate and transfer a graphene channel on the substrate; Deposit a drain and a source at both ends of the graphene channel to form a gate window; Deposit a metal gate in electrical contact with the drain between the gate windows; Form an oxide layer on the surface of the metal gate by annealing oxidation, and at the same time form a gate oxide layer at the interface between the graphene channel and the metal gate.

10. The manufacturing method of the feedback two-terminal fuse memory cell according to claim 9, characterized in that, Form an oxide layer on the surface of the metal gate by annealing at a temperature of 120°C - 150°C for 30 - 60 minutes, and at the same time form the gate oxide layer at the interface between the graphene channel and the metal gate.

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