Semiconductor memory device having a composite dielectric film structure and method of forming the same

Abstract

The present disclosure relates generally to a semiconductor memory device having a composite dielectric film structure and a method of forming the same. A semiconductor memory device and a method of forming the same are disclosed. The semiconductor memory device includes a substrate including a memory region and a peripheral region; a transistor including a metal gate located in the peripheral region; a composite dielectric film structure located on the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein a density of the second dielectric layer is greater than a density of the first dielectric layer; and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection for the metal gate from etch damage, thereby improving device performance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor memory devices having a composite dielectric film structure and methods of forming the same. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth for the past several decades. During this period, the functionality and the number of transistors in ICs has generally increased while the geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] Super Flash technology enables designers to create cost-efficient and high-performance programmable system-on-chip (SOC) solutions by using split-gate flash memory cells. The aggressive scaling of the third generation embedded super flash (ESF3) enables the design of flash memory with high memory array density. SUMMARY

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a substrate including a memory region and a peripheral region; a transistor including a metal gate located in the peripheral region; a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, and a density of the second dielectric layer being greater than a density of the first dielectric layer; and at least one memory cell located in the memory region.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a substrate including a memory region and a peripheral region; a plurality of memory cells located in the memory region; a plurality of transistors located in the peripheral region; and a composite dielectric film structure including at least two layers of dielectric material extending over the plurality of transistors in the peripheral region, wherein a peripheral edge of the composite dielectric film structure is located within 300 nm of a boundary between the memory region and the peripheral region.

[0006] According to yet another embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided, including: forming memory cells in a memory region of a substrate; forming a transistor including a metal gate in a peripheral region of the substrate; forming a composite dielectric film structure over the metal gate of the transistor in the peripheral region of the substrate, wherein the composite dielectric film structure includes a first dielectric layer and a second dielectric layer over the first dielectric layer, and a density of the second dielectric layer is greater than a density of the first dielectric layer; and performing a wet etch to remove a metal material from the semiconductor device, wherein the composite dielectric film structure protects the metal gate of the transistor in the peripheral region from being etched. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a vertical cross-sectional view of a storage device according to various embodiments of the present disclosure.

[0009] Figure 2 This is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the present disclosure, used to form a memory device including a substrate, a first dielectric layer and a second dielectric layer, and a patterned mask.

[0010] Figure 3 This is a vertical cross-sectional view of an exemplary intermediate structure after an etching process that removes portions of the second dielectric layer, the first dielectric layer, and the substrate from the storage region, according to various embodiments of the present disclosure.

[0011] Figure 4 This is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the present disclosure, showing a layer of dielectric material deposited on the recessed surface of a substrate in a storage region.

[0012] Figure 5 This is a vertical cross-sectional view of an exemplary intermediate structure following an etching process that removes a portion of the second dielectric layer from the peripheral region and a portion of the dielectric material layer from the storage region, according to various embodiments of the present disclosure.

[0013] Figure 6 This is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the present disclosure, showing a second dielectric layer above a tunneling layer in the storage region and a portion of the peripheral region, and a patterned mask above the second dielectric layer in the storage region.

[0014] Figure 7 This is a vertical cross-sectional view of an exemplary intermediate structure after an etching process that removes a portion of the second dielectric layer in the peripheral region, according to various embodiments of the present disclosure.

[0015] Figure 8 This is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the present disclosure, showing multiple isolation features extending through the first dielectric layer and the second dielectric layer and into the substrate in the storage region and the peripheral region.

[0016] Figure 9is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a third dielectric material layer over an upper surface of a second dielectric layer and isolation features, a fourth dielectric material layer over an upper surface of the third dielectric material layer, and a patterned mask over an upper surface of the fourth dielectric material layer.

[0017] Figure 10 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, following an etch process that removes some portions of the fourth dielectric layer, the third dielectric layer, and the second dielectric layer from the storage region and exposes the isolation features and an upper surface of the tunnel layer in the storage region.

[0018] Figure 11 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a continuous floating gate layer over the tunnel layer and the first isolation feature in the storage region, and over the fourth dielectric layer and the second isolation feature in the peripheral region.

[0019] Figure 12 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, following a planarization process that removes some portions of the floating gate layer and the fourth dielectric material layer from over an upper surface of the third dielectric material layer.

[0020] Figure 13 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, following an etch process that recesses the floating gate layer and the first isolation feature in the storage region.

[0021] Figure 14 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, shown along a horizontal direction that is rotated 90° relative to the orientation shown in Figures 2-13 Figure 13 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure.

[0022] Figure 15 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a blocking layer, a control gate layer, a hard mask, and a patterned mask over the storage region and the peripheral region.

[0023] Figure 16 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a plurality of storage stacks over the floating gate layer in the storage region.

[0024] Figure 17 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a sidewall structure formed over a side surface of a storage stack.

[0025] Figure 18 ​is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove portions of the floating gate layer and the tunnel layer from the storage region according to various embodiments of the present disclosure.

[0026] Figure 19 is a vertical cross-sectional view of an exemplary intermediate structure showing the gate-to-gate dielectric layer formed over the side surfaces of the storage stacks according to various embodiments of the present disclosure.

[0027] Figure 20 is a vertical cross-sectional view of an exemplary intermediate structure showing the common source region formed between adjacent pairs of storage stacks by a masking implant process according to various embodiments of the present disclosure.

[0028] Figure 21 is a vertical cross-sectional view of an exemplary intermediate structure showing the gate-to-gate dielectric layer removed from the side surfaces of the storage stacks adjacent to the common source region according to various embodiments of the present disclosure.

[0029] Figure 22 is a vertical cross-sectional view of an exemplary intermediate structure showing the common source dielectric layer over the common source region and over the side surfaces of the storage stacks according to various embodiments of the present disclosure.

[0030] Figure 23 is a vertical cross-sectional view of an exemplary intermediate structure showing the select gate dielectric layer over the substrate in the storage region, the conductive material layer over the storage region and the peripheral region of the intermediate structure, and the BL coating over the conductive material layer according to various embodiments of the present disclosure.

[0031] Figure 24 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the BL coating from the intermediate structure and the conductive material layer from over the peripheral region, and to recess the conductive material layer within the storage region of the intermediate structure according to various embodiments of the present disclosure.

[0032] Figure 25 is a vertical cross-sectional view of an exemplary intermediate structure showing the hardmask layer over the storage region and the peripheral region of the intermediate structure according to various embodiments of the present disclosure.

[0033] Figure 26 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the hardmask layer from the peripheral region and from over the upper surfaces of the storage stacks in the storage region, and to remove portions of the hardmask layer and the conductive material layer between adjacent pairs of storage stacks according to various embodiments of the present disclosure.

[0034] Figure 27is a vertical cross-sectional view of an exemplary intermediate structure after an additional etch process to remove a dielectric material layer, and a portion of the dielectric material layer, from a peripheral region of the exemplary structure, in accordance with various embodiments of the present disclosure.

[0035] Figure 28 is a vertical cross-sectional view of an exemplary intermediate structure showing a BL coating over the exemplary intermediate structure, in accordance with various embodiments of the present disclosure.

[0036] Figure 29 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove a BL coating, a memory stack, and an additional portion of a hard mask layer from a memory region, in accordance with various embodiments of the present disclosure.

[0037] Figure 30 is a vertical cross-sectional view of an exemplary intermediate structure showing a liner layer over an exposed surface of the exemplary intermediate structure, in accordance with various embodiments of the present disclosure.

[0038] Figure 31 is a vertical cross-sectional view of an exemplary intermediate structure showing a cap layer formed over the liner layer and a BARC layer over the cap layer, in accordance with various embodiments of the present disclosure.

[0039] Figure 32 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the BARC layer and reduce a thickness of the cap layer over the exemplary intermediate structure, in accordance with various embodiments of the present disclosure.

[0040] Figure 33 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove a cap layer, a liner layer, a dielectric material layer, and a control gate layer from a peripheral region, in accordance with various embodiments of the present disclosure.

[0041] Figure 34 is a vertical cross-sectional view of an exemplary intermediate structure after an additional etch process to remove a barrier layer and a third dielectric layer from a peripheral region of the exemplary intermediate structure, in accordance with various embodiments of the present disclosure.

[0042] Figure 35 is a vertical cross-sectional view of an exemplary intermediate structure showing additional cap material over a memory region and a peripheral region, in accordance with various embodiments of the present disclosure.

[0043] Figure 36 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove a cap layer from a peripheral region, in accordance with various embodiments of the present disclosure.

[0044] Figure 37is a vertical cross-sectional view of an exemplary intermediate structure after an additional etch process to remove the second dielectric material layer from the peripheral region, in accordance with various embodiments of the present disclosure.

[0045] Figure 38 is a vertical cross-sectional view of an exemplary intermediate structure showing a masked ion implantation process performed in a first region of the peripheral region, in accordance with various embodiments of the present disclosure.

[0046] Figure 39 is a vertical cross-sectional view of an exemplary intermediate structure showing a masked ion implantation process performed in a second region of the peripheral region, in accordance with various embodiments of the present disclosure.

[0047] Figure 40 is a vertical cross-sectional view of an exemplary intermediate structure showing a gate dielectric material layer over the exemplary structure, a sacrificial gate material layer over the gate dielectric material layer, and a hardmask layer over the sacrificial gate material layer, in accordance with various embodiments of the present disclosure.

[0048] Figure 41 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the hardmask layer, a portion of the sacrificial gate material layer, from over the cap layer, in accordance with various embodiments of the present disclosure.

[0049] Figure 42 is a vertical cross-sectional view of an exemplary intermediate structure showing a plurality of gate stacks formed over the gate dielectric material layer in the peripheral region, in accordance with various embodiments of the present disclosure.

[0050] Figure 43 is a vertical cross-sectional view of an exemplary intermediate structure showing a gate stack side seal layer over side surfaces of the gate stacks, in accordance with various embodiments of the present disclosure.

[0051] Figure 44 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the gate dielectric material layer and the cap layer from the storage region, in accordance with various embodiments of the present disclosure.

[0052] Figure 45 is a vertical cross-sectional view of an exemplary intermediate structure schematically showing an ion implantation process to form source and drain regions of logic transistors to be subsequently formed in the peripheral region, in accordance with various embodiments of the present disclosure.

[0053] Figure 46 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove some portions of the gate dielectric material layer from the peripheral region, and to form a main sidewall spacer over the select gates in the storage region and over the gate stacks in the peripheral region, in accordance with various embodiments of the present disclosure.

[0054] Figure 47 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a metal silicide region on an exposed surface of a substrate.

[0055] Figure 48 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, following a planarization process that removes a hard mask and a remaining portion of a select gate hard mask layer from a storage region and removes a remaining portion of a hard mask layer from a gate stack in a peripheral region.

[0056] Figure 49 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a contact etch stop layer (CESL) formed conformally over the intermediate structure and an interlayer dielectric (ILD) layer formed over the CESL.

[0057] Figure 50 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, following a planarization process that removes an ILD layer and a CESL from over upper surfaces of control gates, select gates, and erase gates in a storage region and from over an upper surface of a sacrificial gate material layer in a peripheral region.

[0058] Figure 51 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a metal gate formed in a peripheral region.

[0059] Figure 52 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a first dielectric material layer over a peripheral region and over control gates of storage cells in a storage region.

[0060] Figure 53 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a second dielectric material layer over the first dielectric material layer in a peripheral region.

[0061] Figure 54 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing a metal silicide layer over upper surfaces of select gates and erase gates in a storage region.

[0062] Figure 55 is a vertical cross-sectional view of an exemplary intermediate structure according to various embodiments of the disclosure, showing an interlayer dielectric (ILD) layer over the intermediate structure, metal features over the ILD layer, and conductive vias extending between the metal features and storage cells and logic transistors.

[0063] Figure 1is a flowchart illustrating an overall method of fabricating a memory device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0064] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments where the first feature is formed directly in contact with the second feature, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature can not be directly in contact with the second feature. Furthermore, the present disclosure can refer to a device or apparatus including a plurality of elements using both male and female terminology. This terminology is equally applicable to devices or apparatuses of a similar type or intent having neither male nor female components. In addition, the present disclosure can refer to a plurality of elements as a single unit using male terminology. This terminology is equally applicable to devices or apparatuses of a similar type or intent having neither male nor female components.

[0065] Furthermore, spatially relative terms (for example, “beneath”, “below”, “lower”, “above”, “upper”, and the like) can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0066] The present disclosure relates to semiconductor devices, and in particular to semiconductor memory devices including memory cells and logic transistors formed on a common substrate.

[0067] Figure 1 A vertical cross-sectional view of a memory device 100 according to various embodiments of the present disclosure is shown. In some embodiments, the memory device 100 can be an ESF3 memory device, or a so-called “third generation SUPERFLASH” memory device 100. For example, the ESF3 memory device 100 can include an array of symmetric split gate memory cells SGMC1, SGMC2. Each split gate memory cell SGMC1, SGMC2 can include a source region CS, a drain region DR, and a channel region CR disposed therebetween. In the ESF3 architecture, the source region CS of each of the split gate memory cells SGMC1, SGMC2 can be a common source region CS shared with adjacent cells. Each split gate memory cell (e.g., SGMC1 and SGMC2) can have its own drain region DR. One of ordinary skill in the art will appreciate that the source region CS can also be designated as a drain region DR. Thus, in other embodiments, adjacent split gate memory cells can also share a common drain region DR.

[0068] Within each split gate cell SGMC1, SGMC2, a floating gate FG can be disposed over the channel region CR of the split gate cell SGMC1, SGMC2. Further, a control gate CG can be disposed over the floating gate FG. A select gate SG can be disposed to one side of the floating gate FG and the control gate CG (e.g., between the individual source / drain regions CS, DR of the ESF3 memory cell and the sidewalls of the floating gate FG and / or the control gate CG). An erase gate EG can be disposed over the common source / drain region CS between the split gate cells SGMC1 and SGMC2. At least one split gate cell SGMC1, SGMC2 can be configured to store a variable charge level on its floating gate FG, where the level of that charge corresponds to a data state stored in the split gate cell SGMC1, SGMC2 and can be stored in a non-volatile manner such that the stored charge / data persists upon power down.

[0069] A typical flash memory cell uses a floating gate FG to store a bit according to the presence or absence of charge. If the floating gate FG is not charged (i.e., neutral), the operation of the device is similar to a conventional MOSFET, e.g., a positive charge in the control gate CG creates a channel CR in the semiconductor material substrate 210 that carries current from the source CS to the drain region DR. However, in the case where the floating gate FG is negatively charged, that charge shields the channel region CR from the control gate CG to some extent and prevents a channel from forming between the source CS and the drain DR. The threshold V th voltage is the voltage applied to the control gate CG at which the transistor becomes conductive. The presence or absence of charge creates a more positive or more negative threshold voltage V th With reference to flash terminology, programming (putting an electron into the floating gate FG) means writing a 0, erasing (removing charge from the floating gate FG) means resetting the flash content to a 1; or in other words: a programmed cell stores a logical 0, an erased (also known as a flash) split gate storage cell SGMC1, SGMC2 stores a logical 1.

[0070] In various embodiments, the ESF3 memory device 100 as shown in Figure 2 may include an array of split gate storage cells SGMC1, SGMC2 within a storage region 212 of the device 100. In some embodiments, at least some of the split gate storage cells SGMC1, SGMC2 can share a common drain region DR with storage cells adjacent along a first horizontal direction (HD1). The select gate SG, which can also be referred to as a word line WL, can run along a second horizontal direction (HD2, see Figure 1) and extend between the split gate memory cells SGMC of the array. In embodiments, adjacent split gate memory cells SGMC along the second horizontal direction (HD2) can be separated from one another by an isolation feature (e.g., a shallow trench isolation (STI) feature).

[0071] Referring again to Figure 1 The memory device 100 according to various embodiments can also include a peripheral region 214. The peripheral region 214 can include a plurality of logic transistors LT1, LT2. Each of the logic transistors LT1, LT2 can include a metal gate MG disposed over a channel region CR of the logic transistor LT1, LT2, and source and drain regions SD on either side of the metal gate MG. The logic transistors LT1, LT2 in the peripheral region 214 can form logic devices of the memory device 100, e.g., memory selectors, power gates, and input / output elements.

[0072] Referring again to Figure 1 The composite dielectric film structure 101 can extend over each metal gate MG of the logic transistors LT1, LT2 within the peripheral region 214 of the memory device 100. The composite dielectric film structure 101 can include at least two layers of dielectric material 102, 103. In some embodiments, each of the layers of dielectric material 102, 103 can have a thickness of at least about 5 nm, e.g., between about 5 nm and about 30 nm (e.g., between about 5 nm and about 15 nm). The total thickness of the composite dielectric film structure 101 can be between about 10 nm and about 60 nm (e.g., between about 10 nm and about 45 nm), which can provide sufficient protection for the metal gates MG during fabrication of the memory device 100.

[0073] In various embodiments, the composite dielectric film structure 101 can include a first layer of dielectric material 102. The first layer of dielectric material 102 can be located over an upper surface of the metal gate MG of the logic transistor LT1, LT2. In some embodiments, the first layer of dielectric material 102 can directly contact the upper surface of the metal gate MG of the logic transistor LT1, LT2. The first layer of dielectric material 102 can be composed of a suitable dielectric material, e.g., an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the first layer of dielectric material 102 can be composed of silicon oxide formed using a tetraethyl orthosilicate (TEOS) precursor. In some embodiments, the first layer of dielectric material 102 can be a resist protective oxide (RPO) material. Other suitable dielectric materials are within the contemplation of the present disclosure. In some embodiments, the first layer of dielectric material 102 can have good adhesion properties, including good adhesion to the material(s) of the metal gate MG of the logic transistor LT1, LT2.

[0074] The composite dielectric film structure 101 can include a second dielectric material layer 103, which can be located above the first dielectric material layer 102. In some embodiments, the second dielectric material layer 103 can directly contact the first dielectric material layer 102. The second dielectric material layer 103 can have a different composition and / or different physical properties than the first dielectric material layer 102. In various embodiments, the second dielectric material layer 103 can have a greater density than the first dielectric material layer 102. For example, the second dielectric material layer 103 can have a density that is at least 10% greater, such as at least 50% greater, including at least 100% greater, than the density of the first dielectric material layer 102. In some embodiments, the second dielectric material layer 103 can have a lower etch rate (i.e., higher etch resistance) than the material of the first dielectric material layer 102.

[0075] The second dielectric material layer 103 can be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the second dielectric material layer 103 can be composed of a buffer oxide material, a silicon nitride material, a high temperature oxide (HTO) material, etc. Other suitable dielectric materials are within the contemplated scope of the present disclosure. In some embodiments, the composite dielectric film structure 101 can include one or more additional dielectric material layers, where the one or more additional layers can be located between the upper surface of the metal gate MG of the logic transistors LT1, LT2 and the first dielectric material layer 102, between the first dielectric material layer 102 and the second dielectric material layer 103, and / or above the second dielectric material layer 103.

[0076] Referring again to Figure 1In some embodiments, an isolation feature IF2 (e.g., a shallow trench isolation (STI) feature) can be located between the storage cells SGMC1, SGMC2 of the storage region 212 and the logic transistors LT1, LT2 of the peripheral region 214 of the memory device 100. A peripheral edge of the isolation feature IF2 can define a boundary 430 between the storage region 212 and the peripheral region 214 of the memory device 100. In various embodiments, a peripheral edge 431 of the composite dielectric film structure 101 can be within ±300 nm (e.g., ±200 nm, such as ±100 nm) of the boundary 430 between the storage region 212 and the peripheral region 214 of the memory device 100. By providing the peripheral edge 431 within ±300 nm of the boundary 430 between the storage region 212 and the peripheral region 214, the composite dielectric film structure 101 does not extend too far into the storage region 212 where it can interfere with subsequent processing steps for forming the storage cells SGMC1, SGMC2, while also ensuring that the dielectric film structure 101 extends sufficiently within the peripheral region 214 to protect the metal gates MG of the logic transistors LT. Thus, in various embodiments, the composite dielectric film structure 101 can not extend above the upper surfaces of the storage cells SGMC1, SGMC2 of the storage region 212. In some embodiments, a lower surface of the composite dielectric film structure 101 can be substantially coplanar with the upper surfaces of the storage cells SGMC1, SGMC2 of the storage region 212.

[0077] In various embodiments, an interlayer dielectric material (ILD) layer 412 can be located above the upper surfaces of the storage cells SGMC1, SGMC2 in the storage region 212 of the memory device 100, as well as above the upper surface of the composite dielectric film structure 101 in the peripheral region 214. A plurality of conductive vias 110 can extend through the interlayer dielectric material layer 412. In the storage region 212 of the memory device 100, the conductive vias 110 can be in electrical contact with the drain regions DR of the storage cells SGMC1, SGMC2, and can electrically connect the storage cells SGMC1, SGMC2 to the overlying metal feature(s) 112 of the memory device 100. In the peripheral region 214 of the memory device 100, the conductive vias 110 can extend through the composite dielectric film structure 101 and can be in electrical contact with the respective source and drain regions SD of the logic transistors LT1, LT2. The conductive vias 110 can electrically connect the logic transistors LT1, LT2 to the overlying metal feature(s) 112 of the memory device 100. In various embodiments, the composite dielectric film structure 101 can extend continuously between the conductive vias 110 within the peripheral region 214 of the memory device 100.

[0078] In some embodiments, the upper surface of semiconductor material substrate 210 used for separating gate storage cells SGMC1, SGMC2 located within storage region 212 of device 100 can be recessed relative to the upper surface of semiconductor material substrate 210 used for logic transistors LT1, LT2 located within peripheral region 214 of device 100.

[0079] In various embodiments, the composite dielectric film structure 101 in the peripheral region 214 of memory device 100 can provide enhanced protection for the logic transistors LT1, LT2 within the peripheral region. Specifically, the composite dielectric film structure 101 can protect the integrity of the metal gates MG of the logic transistors LT1, LT2. In some cases, processing steps during the fabrication of memory device 100 can generate metal precipitates from the metal material(s) (e.g., aluminum) used to form the metal gate MG structure of the logic transistors LT1, LT2. The presence of these metal precipitates can create weak spots, such as sidewall pits, in the dielectric material layer subsequently formed over the metal gate structure MG. During subsequent fabrication steps, such as a wet etch step after silicidation of the select gates SG and erase gates EG of the storage cells, some portions of the metal gate(s) MG can be inadvertently etched through the weak spots in the overlying dielectric layer. This can negatively impact the performance of memory device 100. In various embodiments, by providing the composite dielectric film structure 101 over the metal gates MG of the logic transistors LT1, LT2 in the peripheral region 214 of memory device 100, the metal gates MG can be better protected from etch damage, which can improve the performance and yield of memory device 100. In addition to memory devices, for example Figures 2 to 55 The ESF3 memory device 100 shown, as well as the composite dielectric film structure 101 shown and described herein, can also be used in other types of integrated circuit (IC) devices, including devices having metal gate structures that can include a composite dielectric film structure 101 over the gate structure(s) in order to avoid metal gate etch damage and / or metal gate peeling.

[0080] Figure 1 is a sequence of vertical cross-sectional views showing intermediate structures during a method of fabricating an ESF3 memory device 100, such as the one shown in Figure 2 is a sequence of vertical cross-sectional views showing intermediate structures during a method of fabricating an ESF3 memory device 100, such as the one shown in

[0081] Figure 2is a vertical cross-sectional view of an exemplary intermediate structure according to various aspects of the present disclosure, including a substrate 210, a first dielectric layer 220 and a second dielectric layer 230, and a patterned mask PR. Reference is made to Figure 2 , the substrate 210 is shown in a vertical cross-section along a horizontal direction HD2. Thus, Figure 1 the cross-sectional view shown is rotated 90° with respect to the direction of Figure 1 , Figure 2 is a vertical cross-sectional view of the memory device 100 along a horizontal direction HD1. In various embodiments, the substrate 210 can be a semiconductor material substrate, for example, a bulk silicon substrate, a germanium substrate, a composite substrate, or other suitable substrate. In some embodiments, the substrate 210 can include an epitaxial layer overlying a bulk semiconductor, a silicon germanium layer overlying a bulk silicon, a silicon layer overlying a bulk silicon germanium, or a semiconductor-on-insulator (SOI) structure. The substrate 210 can include a memory region 212 and a peripheral region 214. The peripheral region 214 can be positioned such that it surrounds the memory region 212.

[0082] Referring again to Figure 2 , a first dielectric layer 220 can be formed over the substrate 210. The first dielectric layer 220 can include, for example, a dielectric material, for example, silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, other non-conductive material, or a combination thereof. Other suitable dielectric materials are within the contemplated scope of the present disclosure.

[0083] A second dielectric material layer 230 can be formed over the first dielectric layer 220. The dielectric material layer 230 can include a suitable dielectric material, for example, silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, other non-conductive material, or a combination thereof. In one non-limiting embodiment, the first dielectric material layer 220 can include silicon oxide, and the second dielectric material layer 230 can include silicon nitride. In various embodiments, the thickness of the second dielectric material layer 230 can be greater than the thickness of the first layer 220.

[0084] The first dielectric material layer 220 and the second dielectric material layer 230 can be deposited using any suitable deposition process. Here, a "suitable deposition process" can include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high-density plasma CVD (HDPCVD) process, a low-pressure CVD process, a metal-organic CVD (MOCVD) process, a plasma-enhanced CVD (PECVD) process, a sputtering process, laser ablation, etc.

[0085] Referring again to Figure 3A patterned mask, e.g., a photoresist mask PR, can be formed over the second dielectric layer 230 in the peripheral region 214 of the intermediate structure. The patterned mask can be formed by depositing a layer of photoresist material over the second dielectric layer 230 and lithographically patterning the photoresist material to form the patterned mask PR covering the second dielectric layer 230 in the peripheral region 214 of the intermediate structure. The second dielectric layer 230 can be exposed by the patterned mask PR in the storage region 212 of the intermediate structure.

[0086] Figure 3 is a vertical cross-sectional view of an exemplary intermediate structure after an etching process that removes portions of the second dielectric layer 230, the first dielectric layer 220, and the substrate 210 from the storage region 212 of the intermediate structure. Reference is made to Figure 4 After the etching process, the upper surface of the substrate 210 in the storage region 212 can be recessed relative to the upper surface of the substrate 210 in the peripheral region 214. After the etching process, the patterned mask can be removed using a suitable process, e.g., by ashing or dissolving with a solvent.

[0087] Figure 5 is a vertical cross-sectional view of an exemplary intermediate structure showing a layer of dielectric material 220A deposited over the recessed surface of the substrate 210 in the storage region 212. In embodiments, the layer of dielectric material 220A deposited over the recessed surface of the substrate 210 can be the same dielectric material (e.g., silicon oxide) as the material of the first dielectric layer 220. The vertical height of the layer of dielectric material 220A can be greater than the distance by which the substrate 210 is recessed in the storage region 212. Thus, the side surface of the layer of dielectric material 220A can be in contact with the exposed side surface of the dielectric layer 220, such that the layers 220 and 220A can be continuous. The layer of dielectric material 220A can be deposited using a suitable deposition method as described above.

[0088] Figure 5 is a vertical cross-sectional view of an exemplary intermediate structure after an etching process that removes a portion of the second dielectric layer 230 from the peripheral region 214 and removes a portion of the layer of dielectric material 220A from the storage region 212. Reference is made to Figure 5 In various embodiments, the exemplary intermediate structure can be etched using an etching process that has a higher etching rate for the material of the layer of dielectric material 220A than for the material of the second dielectric material layer 230. Thus, as Figure 5As shown, the thickness of the dielectric material layer 220A removed from the storage region 212 can be greater than the thickness of the second dielectric material layer 230 removed from the peripheral region 214. In some embodiments, after this etch process, the thickness of the remaining dielectric material layer 220A in the storage region 212 can be approximately the same as the thickness of the first dielectric material layer 220 in the peripheral region 214. As shown, the dielectric material layer 220A in the storage region 212 can be continuous with the first dielectric material layer 220 in the peripheral region 214, and the layers 220A and 220 can also be collectively referred to as the tunnel layer 220. Figure 6 As shown, the dielectric material layer 220A in the storage region 212 can be continuous with the first dielectric material layer 220 in the peripheral region 214, and the layers 220A and 220 can also be collectively referred to as the tunnel layer 220.

[0089] Figure 6 is a vertical cross-sectional view of an exemplary intermediate structure showing the second dielectric layer 230 over the tunnel layer 220 in the storage region 212 and the peripheral region 214, and a patterned mask PR over the second dielectric layer 230 in the storage region 212, and a portion of the peripheral region 214. Reference is made to Figure 6 An additional dielectric material can be deposited over the second dielectric layer 230 in the peripheral region 214 and over the tunnel layer 220 in the storage region. The additional dielectric material can be the same material as the material of the second dielectric layer 230. Thus, the additional dielectric material can increase the thickness of the second dielectric layer 230 in the peripheral region 214, and can extend the second dielectric layer 230 into the storage region 212. In various embodiments, the additional dielectric material can comprise silicon nitride, and can be deposited using a suitable deposition method as described above.

[0090] Referring again to Figure 7 A patterned mask, e.g., a photoresist mask PR, can be formed over the second dielectric layer 230 in the storage region 212, and a portion of the peripheral region 214. The patterned mask can be formed by depositing a layer of photoresist material over the second dielectric layer 230, and lithographically patterning the photoresist material to form the patterned mask PR that covers the second dielectric layer 230 in the storage region 212, and a portion of the peripheral region 214. The second dielectric layer 230 can be exposed in the remaining portion of the peripheral region by the patterned mask PR.

[0091] Figure 7 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process that removes a portion of the second dielectric layer 230 in the peripheral region 214 of the intermediate structure. Reference is made to Figure 8After this etching process, the thickness of the second dielectric layer 230 in the peripheral region 214 can be reduced. In some embodiments, after this etching process, the thickness of the second dielectric layer 230 in the peripheral region 214 can be less than the thickness of the second dielectric layer 230 in the storage region 212. After this etching process, a suitable process can be used to remove the patterned mask, for example, by ashing or solvent dissolution.

[0092] Figure 8 This is a vertical cross-sectional view of an exemplary intermediate structure, illustrating multiple isolation features IF1, IF2 extending through the first dielectric layer 220 and the second dielectric layer 230 of the exemplary structure and into the substrate 210 in the storage region 212 and the peripheral region 214. Reference Figure 8 The isolation features IF1 and IF2 can be formed as follows: a photoresist layer is applied and patterned on the upper surface of the second dielectric layer 230. Figure 8 (Not shown), and an anisotropic etching process is performed to remove portions of the second dielectric layer 230, the first dielectric layer 220, and the substrate 210, forming multiple trenches that penetrate through the first and second dielectric layers 220, 230 and into the upper portion of the substrate 210. The photoresist layer can then be removed, for example, by ashing or solvent dissolution. Dielectric material can be deposited in the trenches, and a planarization process, such as chemical mechanical planarization (CMP), can be performed to remove excess dielectric material from above the upper surface of the second dielectric layer 230 and provide a substrate with... Figure 8 The diagram shows the intermediate structure of a flat upper surface. After the planarization process, the remaining portion of the trench filled with dielectric material can form isolation features IF1 and IF2, which can be shallow trench isolation (STI) structures. Each of isolation features IF1 and IF2 can be embedded within the second dielectric layer 230, the first dielectric layer / tunnel layer 220, and the substrate 210. In various embodiments, the dielectric material of isolation features IF1 and IF2 can include oxide materials and / or other suitable dielectric materials.

[0093] The first plurality of isolation features IF1 may be located in the storage region 212 and the peripheral region 214. Each of the first plurality of isolation features IF1 may extend along a first horizontal direction HD1 perpendicular to the second horizontal direction HD2. Therefore, the first plurality of isolation features IF1 may divide the storage region 212 and the peripheral region 214 into a plurality of active regions 232 and 234 extending along the first horizontal direction HD1, respectively. In some embodiments, the depth of the bottom surface of the isolation feature IF1 in the storage region 212 may be less than the depth of the bottom surface of the isolation feature IF1 in the peripheral region 214.

[0094] Refer again Figure 1The second isolation feature IF2 can be located between the storage region 212 and the peripheral region 214 of the example structure. As described above with reference to Figure 8 The peripheral edge of the second isolation feature IF2 adjacent to the storage region 212 can define a boundary 430 between the storage region 212 and the peripheral region 214. The second isolation feature IF2 can extend in a first horizontal direction HD1 that is perpendicular to the second horizontal direction HD2. In some embodiments, the second isolation feature IF2 can extend continuously around the entire storage region 212. As shown, the upper surface of the substrate 210 can be in contact with a first side of the second isolation feature IF2 in the peripheral region 214, and the upper surface of the substrate 210 can be in contact with a second side of the second isolation feature IF2 in the storage region 212, where the upper surface of the substrate 210 in the storage region 212 can be vertically recessed relative to the upper surface of the substrate 210 in the peripheral region 214. The lateral thickness (i.e., along HD2) of the second isolation feature IF2 can be greater than the lateral thickness of the first plurality of isolation features IF1. Figure 9

[0095] Figure 9 is a vertical cross-sectional view of the example intermediate structure showing the upper surface of the second dielectric layer 230 and a third dielectric material layer 240 over the isolation features IF1, IF2, a fourth dielectric material layer 241 over the upper surface of the third dielectric material layer 240, and a patterned mask PR over the upper surface of the fourth dielectric material layer 241. With reference to Figure 9 The third dielectric material layer 240 can be composed of the same dielectric material as the second dielectric material layer 230. In various embodiments, the third dielectric material layer 230 can be composed of silicon nitride. The fourth dielectric material layer 241 can be formed over the upper surface of the third dielectric material layer 240. The fourth dielectric material layer 241 can be composed of a different dielectric material than the material of the third dielectric material layer 240. In some embodiments, the fourth dielectric material layer 241 can be composed of an oxide material (e.g., silicon oxide), for example, a resist protective oxide (RPO) material. The third dielectric material layer 240 and the fourth dielectric material layer 241 can be deposited using suitable deposition methods as described above.

[0096] Referring again to Figure 9 A patterned mask, for example, a photoresist mask PR, can be formed over the fourth dielectric layer 241 in the peripheral region 214 of the intermediate structure. The patterned mask can be formed by depositing a layer of photoresist material over the fourth dielectric layer 241 and lithographically patterning the photoresist material to form the patterned mask PR covering the fourth dielectric layer 241 in the peripheral region 214 of the intermediate structure. As shown, the patterned mask PR can cover the fourth dielectric layer 241 in the peripheral region 214 of the intermediate structure, but not the fourth dielectric layer 241 in the storage region 212 of the intermediate structure. Figure 10 ​As shown, the edges of the mask PR can be located above the upper surfaces of the second isolation features IF2.

[0097] Figure 10 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process that removes portions of the fourth dielectric layer 241, the third dielectric layer 240, and the second dielectric layer 230 from the storage region 212, and exposes the upper surfaces of the isolation features IF1, IF2, and the tunnel layer 220 in the storage region 212. Reference is made to Figure 10 The exemplary structure can be etched through the patterned mask PR to remove the portions of the fourth dielectric layer 241, the third dielectric layer 240, and the second dielectric layer 230 exposed by the mask. The etch process can stop at the tunnel layer 220. The etch process can be a selective etch process that preferentially etches the materials of the fourth dielectric layer 241, the third dielectric layer 240, and the second dielectric layer 230 relative to the materials of the isolation features IF1, IF2, and the tunnel layer 220. In one non-limiting example, the etch process can include a first etch step that removes the fourth dielectric layer 241, which can be an oxide material, followed by a second etch step that preferentially etches the materials of the second and third dielectric material layers 230, 240, which can be nitride materials, relative to the materials of the tunnel layer 220 and the isolation features IF1, IF2, which can be composed of an oxide material. After the etch process, the first isolation features IF1 can protrude above the upper surface of the tunnel layer 220, as shown in Figure 10 In addition, the etch process can also remove the portions of the layers 240 and 241 exposed by the patterned mask PR from above the second isolation features IF2. Thus, after the etch process, portions of the upper surface and lateral side surfaces of the second isolation features IF2 can be exposed, as shown in Figure 11 After the etch process, the patterned mask PR can be removed using a suitable process, such as by ashing or dissolving with a solvent.

[0098] Figure 11 is a vertical cross-sectional view of an exemplary intermediate structure showing a continuous floating gate layer 243L above the tunnel layer 220 and the first isolation features IF1 in the storage region 212, and above the fourth dielectric layer 241 and the second isolation features IF2 in the peripheral region 214. Reference is made to Figure 12 In some embodiments, the continuous floating gate layer 243L can be composed of a semiconductor material, such as polysilicon. In other embodiments, the continuous floating gate layer 243L can include a metal, a metal alloy, single crystalline silicon, or a combination thereof. Other suitable materials for the continuous floating gate layer 243L are within the contemplated scope of the present disclosure. The continuous floating gate layer 243L can be deposited using a suitable deposition method as described above.

[0099] Figure 12 is a vertical cross-sectional view of an exemplary intermediate structure after a planarization process that removes some portions of the floating gate layer 243L and the fourth dielectric material layer 241 from above the upper surface of the third dielectric material layer 240. Referring to Figure 13 , the exemplary structure can undergo a planarization process, e.g., a chemical mechanical planarization (CMP) process. The planarization process can remove some portions of the floating gate layer 243L. The planarization process can also remove the remaining portions of the fourth dielectric material layer 241 to expose the upper surface of the third dielectric material layer 240 in the peripheral region 214. After the planarization process, the exemplary intermediate structure can include a planar top surface formed by the upper surface of the continuous floating gate layer 243L in the storage region 212 of the exemplary structure and the upper surface of the third dielectric material layer 240 in the peripheral region 214.

[0100] Figure 13 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process that recesses the floating gate layer 243 and the first isolation feature IF1 in the storage region 212. Referring to Figure 13 , the exemplary structure can undergo an etch process that removes the floating gate layer 243 from above the upper surfaces of the isolation features IF1, IF2 and recesses the height of the floating gate layer 243 within the storage region 212. The etch process can also remove some portions of the isolation features IF1 and IF2. In embodiments, the first isolation feature IF1 can etch at a higher etch rate than the floating gate layer 243, such that after the etch process, the upper surface of the floating gate layer 243 in the storage region 212 can be higher than the upper surface of the first isolation feature IF1. The etch process can also remove a portion of the second isolation feature IF2, such that the upper surface of the second isolation feature IF2 adjacent to the storage region 212 can be substantially coplanar with the upper surface of the first isolation feature IF1 and can be lower than the upper surface of the floating gate layer 243.

[0101] Referring again to Figure 13 , after the etch process, in the storage region 212, the floating gate layer 243 can include a plurality of discrete floating gate layers 243 separated by the first isolation feature IF1. Each of the discrete floating gate layers 243 can be located within an active region 232 of the storage region 212 and can extend continuously along the first horizontal direction HD1 (i.e., into and out of the page in Figure 14 , in each active region 232, the tunnel layer 220 can be located between the floating gate layer 243 and the upper surface of the substrate 210.

[0102] Figure 13 is a vertical cross-sectional view of the exemplary intermediate structure of Figure 14 illustrated along the horizontal direction HD1. Thus, Figures 2-13The cross-sectional view of the intermediate structure shown is relative to Figure 14 The orientation shown is rotated by 90°. Referring to Figure 14 The active region 232 of the storage region 212 is shown, including the tunnel layer 220 over the upper surface of the substrate 210, and the floating gate layer 243 over the tunnel layer 220. Figure 15 The active region 234 of the peripheral region 214 of the intermediate structure is also shown. The active regions 232 and 234 can be separated by the second isolation feature IF2. In some embodiments, the active region 234 of the peripheral region can include one or more first isolation features IF1. The one or more first isolation features IF1 can be located between some portions of the active region 234 that can subsequently have logic transistors formed thereon.

[0103] Figure 15 is a vertical cross-sectional view of the exemplary intermediate structure, showing the blocking layer 245, the control gate layer 247, the hard mask HM, and the patterned mask PR formed over the storage region 212 and the peripheral region 214 of the exemplary structure. Referring to Figure 15 The blocking layer 245 can be conformally deposited over the third dielectric layer 240 in the peripheral region 214 and over the floating gate layer 243 in the storage region 212. The blocking layer 245 can also be deposited over the side surfaces and the upper surface of the second isolation feature IF2.

[0104] In some embodiments, the blocking layer 245 and the tunnel layer 220 can be formed of the same material. In other embodiments, the blocking layer 245 and the tunnel layer 220 can be formed of different materials. That is, the blocking layer 245 can include, for example, a dielectric material, such as silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, other non-conductive material, or combinations thereof. In some embodiments, the blocking layer 245 can be composed of a multi-layer structure that can include different dielectric materials. Other suitable dielectric materials are within the contemplated scope of the present disclosure.

[0105] Referring again to Figure 15 The control gate layer 247 can be conformally deposited over the blocking layer 245. In some embodiments, the control gate layer 247 can be composed of a semiconductor material, such as polysilicon. In other embodiments, the control gate layer 247 can include a metal, a metal alloy, single-crystal silicon, or combinations thereof. Other suitable materials for the control gate layer 247 are within the contemplated scope of the present disclosure.

[0106] Referring again to Figure 15The hard mask HM can be conformally deposited over the control gate layer 247. In various embodiments, the hard mask HM can include a multi-layer structure with different dielectric material layers. In one non-limiting example, the hard mask HM can include a nitride-oxide-nitride ("NON") structure, and can include a layer 249 of nitride material (e.g., silicon nitride) deposited over the control gate layer 247, a layer 250 of oxide material (e.g., silicon oxide) deposited over the nitride layer 249, and another layer 251 of nitride material (e.g., silicon nitride) deposited over the oxide layer 250.

[0107] Referring again to Figure 16 A patterned mask, such as a photoresist mask PR, can be formed over the hard mask HM in the storage region 212 and the peripheral region 214 of the intermediate structure. The patterned mask PR can be formed by depositing a layer of photoresist material over the fourth dielectric layer 241, and lithographically patterning the photoresist material to form the patterned mask PR. In embodiments, the patterned mask PR can cover the entire peripheral region 214 of the intermediate structure. The patterned mask PR can cover some portions of the storage region 212 that can correspond to locations of storage cells that can be subsequently formed.

[0108] Figure 16 is a vertical cross-sectional view of an exemplary intermediate structure, showing a plurality of storage stacks MS1, MS2, MS3, MS4 over the floating gate layer 243 in the storage region 212 of the intermediate structure. Referring to Figure 17 An anisotropic etch process can be performed to remove some portions of the hard mask HM, the control gate layer 247, and the blocking layer 245 that are exposed by the patterned mask PR. The etch process can stop at the floating gate layer 243. After the etch process, a plurality of storage stacks MS1-MS4 can be located over the floating gate layer 243 in the storage region 212. Each storage stack MS1-MS4 can include the blocking layer 245 over the floating gate layer 243, the control gate CG over the blocking layer 245, and the hard mask HM over the control gate CG. After the etch process, the patterned mask PR can be removed using a suitable process, such as by ashing or dissolving with a solvent.

[0109] Figure 17 is a vertical cross-sectional view of an exemplary intermediate structure, showing a sidewall structure 270 formed over side surfaces of the storage stacks MS1-MS4. Referring to Figure 18The sidewall structure 270 may include one or more dielectric materials on the exposed side surfaces of the hard mask HM, control gate CG, and barrier layer 245 in each memory stack MS1-MS4. In some embodiments, the sidewall structure 270 may include a multilayer structure with different dielectric material layers. In a non-limiting example, the sidewall structure 270 may include an oxide-nitride-oxide (“ONO”) structure comprising a first oxide layer, a nitride layer above the first oxide layer, and a second oxide layer above the nitride layer. In embodiments, the sidewall structure 270 may be formed by conformally depositing one or more dielectric material layers (e.g., ONO layers) on an intermediate structure, including on the upper and side surfaces of the memory stacks MS1-MS4 in memory region 212 and on the upper surface of the floating gate layer 243, and on the exposed side surfaces of layers 240, 245, 247, 249, 250, and 251 in peripheral region 214 and on the upper surface of the hard mask HM. In some embodiments, an anisotropic etching process (e.g., reactive ion etching) can be used to remove the horizontally extending portions of the dielectric material layer(s), while leaving a sidewall structure 270 above the vertically extending surface. In some embodiments, the sidewall structure 270 may include an ONO layer, and the anisotropic etching process may remove a second oxide layer and a nitride layer of the ONO layer above the horizontally extending surface, leaving a first oxide layer 270a of the ONO layer above the horizontally extending surface of the intermediate structure.

[0110] Figure 18 This is a vertical cross-sectional view of an exemplary intermediate structure after an etching process that removes portions of the floating gate layer 243 and tunnel layer 220 from the storage region 212 of the intermediate structure. (See reference...) Figure 19 An anisotropic etching process can be used to remove the floating gate layer 243 and tunnel layer 220 between the individual memory stacks MS1-MS4. The etching process can also remove the first oxide layer 270a from the horizontally extending surface of the intermediate structure. The portions of the floating gate layer 243 and tunnel layer 220 located below the memory stacks MS1-MS4 can be protected from etching by the memory stacks MS1-MS4 during the self-aligned etching process. After the etching process, each memory stack MS1-MS4 in the memory region 212 may include the tunnel layer 220 above the substrate 210, the floating gate FG above the tunnel layer 220, the barrier layer 245 above the floating gate FG, the control gate CG above the barrier layer 245, and the hard mask HM above the control gate CG. The sidewall structure 270 may extend above the side surfaces of the hard mask HM, the control gate CG, and the barrier layer 245, and may contact the upper surface of the floating gate FG.

[0111] Figure 19is a vertical cross-sectional view of an exemplary intermediate structure showing a gate-to-gate dielectric layer 280 formed over the side surfaces of the memory stacks MS1-MS4. Reference is made to FIG. 1 for purposes of orientation. Figure 20 The gate-to-gate dielectric layer 280 can include one or more dielectric materials over the sidewall structures 270, and over exposed side surfaces of the floating gates FG and tunnel layers 220 in each of the memory stacks MS1-MS4. In some embodiments, the gate-to-gate dielectric layer 280 can be composed of an oxide material, such as high temperature oxide (HTO). Other suitable dielectric materials are within the contemplation of the present disclosure, including oxides, nitrides, multilayer structures (e.g., ONO structures), and combinations thereof.

[0112] In various embodiments, the gate-to-gate dielectric layer 280 can be formed in a similar manner as described above with respect to the sidewall structures 270. Specifically, a continuous gate-to-gate dielectric layer 280 can be conformally deposited over the intermediate structure, and a horizontally extending portion of the gate-to-gate dielectric layer 280 can be removed using an anisotropic etching process. After the etching process, the gate-to-gate dielectric layer 280 can remain over the vertically extending surfaces, including the side surfaces of the memory stacks MS1-MS4.

[0113] Figure 20 is a vertical cross-sectional view of an exemplary intermediate structure showing a common source region CR formed between adjacent pairs of memory stacks by a masked implantation process. Reference is made to FIG. 3 for purposes of orientation. Figure 21 A patterned mask, such as a photoresist mask PR, can be formed over the memory region 212 and the peripheral region 214 of the intermediate structure. The patterned mask can be formed by depositing a layer of photoresist material over the intermediate structure, and lithographically patterning the photoresist material to form the patterned mask PR. The patterned mask can include openings that expose portions of the substrate 210 between adjacent pairs of memory stacks MS1-MS4 within the memory region 212. An ion implantation process can be performed through the patterned mask PR to form the common source region CR in the substrate 210 between the adjacent pairs of memory stacks MS1-MS4.

[0114] Figure 21 is a vertical cross-sectional view of an exemplary intermediate structure showing removal of the gate-to-gate dielectric layer 280 from the side surfaces of the memory stacks MS1-MS4 adjacent to the common source region CR. Reference is made to FIG. 4 for purposes of orientation. Figure 22 The gate-to-gate dielectric layer 280 adjacent to the common source region CR can be removed along the side surfaces of the memory stacks MS1-MS4 using an etching process. The gate-to-gate dielectric layer 280 that is not adjacent to the common source region CR can remain on the side surfaces of the memory stacks MS1-MS4.

[0115] Figure 22is a vertical cross-sectional view of an exemplary intermediate structure showing a common source dielectric layer 280 over the common source region CR and over side surfaces of the memory stacks MS1-MS4. Reference is made to Figure 23 The common source dielectric layer 280 can be composed of a suitable dielectric material, e.g., an oxide material (e.g., silicon oxide). The common source dielectric layer 280 can be formed over the common source region CS using, e.g., surface oxidation, CVD, other suitable deposition techniques, etc. In some embodiments, the formation of the common source dielectric layer 280 can include depositing a layer of dielectric material and etching portions of the dielectric layer that are not between the memory stacks MS1, MS2 or MS3, MS4, such that the remaining portions of the dielectric layer form the common source dielectric layer 280 over the common source region CS and over the side surfaces of the memory stacks MS1-MS4.

[0116] Figure 23 is a vertical cross-sectional view of an exemplary intermediate structure showing a select gate dielectric layer 282 over the substrate 210 in the memory region 212, a layer of conductive material 283 over the memory region 212 and the peripheral region 214 of the intermediate structure, and a bottom layer (BL) coating 285 over the layer of conductive material 283. The BL coating 285 can be composed of a suitable material, e.g., an organic photoresist, which can provide a substantially planar upper surface over the exemplary intermediate structure. Reference is made to Figure 23 The select gate dielectric layer 282 can be formed over the surface of the substrate 210 between each pair of memory stacks MS1-MS4 sharing the common source region CR. The select gate dielectric layer 282 can be composed of a suitable dielectric material, e.g., an oxide material (e.g., silicon oxide). The select gate dielectric layer 282 can be formed between pairs of memory stacks MS1-MS4 using, e.g., surface oxidation, CVD, other suitable deposition techniques, etc. In some embodiments, the formation of the select gate dielectric layer 282 can include depositing a layer of dielectric material and etching portions of the dielectric layer that are not between pairs of memory stacks MS1-MS4 sharing the common source region CR, such that the remaining portions of the dielectric layer form the select gate dielectric layer 282 between pairs of memory stacks MS1-MS4 sharing the common source region CR.

[0117] Reference is again made to Figure 24A layer of conductive material 283 can be formed over the storage region 212 and the peripheral region 214 of the intermediate structure. The layer of conductive material 283 can be composed of a suitable conductive material, such as, for example, a doped polysilicon material. In other embodiments, the layer of conductive material 283 can include a metal, a metal alloy, doped amorphous silicon, or a combination thereof. Other suitable materials for the layer of conductive material 283 are within the intended scope of the present disclosure. The layer of conductive material 283 can be deposited using a suitable deposition process as described above. In various embodiments, a BL coating 285 can be deposited over an upper surface of the layer of conductive material 283.

[0118] Figure 24 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process that removes the BL coating 285 from the intermediate structure and removes the layer of conductive material 283 from over the peripheral region 214, and recesses the layer of conductive material 283 within the storage region 212 of the intermediate structure. Referring to Figure 25 , the exemplary structure can undergo an etch process that removes the entire BL coating 285. The etch process can also remove the layer of conductive material 283 from the peripheral region 214, and can remove some portions of the layer of conductive material 283 from the storage region 212, such that the storage stacks MS1-MS4 protrude above an upper surface of the layer of conductive material 283. In various embodiments, the height of the layer of conductive material 283 can be recessed such that the upper surface of the layer of conductive material 283 is approximately coplanar with an upper surface of the control gate CG within the storage stacks MS1-MS4. The layer of conductive material 283 can form the select gate SG and the erase gate EG of the storage cells formed in the storage region 212 of the exemplary structure.

[0119] Figure 25 is a vertical cross-sectional view of an exemplary intermediate structure showing a hard mask layer 287 over the storage region 212 and the peripheral region 214 of the intermediate structure. Referring to Figure 26 , the hard mask layer 287 can be composed of a dielectric material, such as, for example, a nitride material (e.g., silicon nitride). Other suitable dielectric materials are within the intended scope of the present disclosure. The hard mask layer 287 can protect and help define the select gate SG and the erase gate EG of the storage cells that will be subsequently formed in the storage region 212. The hard mask layer 287 can be conformally deposited using a suitable deposition method as described above.

[0120] Figure 26 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process that removes the hard mask layer 287 from over the peripheral region 214 and from the upper surfaces of the storage stacks MS1-MS4 in the storage region 212, and removes some portions of the hard mask layer 287 and the layer of conductive material 283 between adjacent pairs of storage stacks MS1-MS4. Referring to Figure 27The exemplary structure can undergo an etch process that can remove the hard mask layer 287 from the peripheral region 214 of the exemplary structure, and can also remove some portions of the hard mask layer 287 and the conductive material layer 283 from the memory region 212 of the exemplary structure. In the peripheral region 214, the etch process can remove the hard mask layer 287, and can remove a portion of the dielectric material layer 251. In the memory region 212, the etch process can remove the hard mask layer 287 from above the upper surfaces of the memory stacks MS1-MS4, and can also remove at least a portion of the uppermost layer (i.e., the dielectric material layer 251) of the hard mask HM of each memory stack MS1-MS4. After the etch process, a remaining portion of the hard mask layer 287 can be adjacent to the side surfaces of each memory stack MS1-MS4 and over a remaining portion of the conductive material layer 283. Between pairs of adjacent memory stacks MS1-MS4 that share a common source region CR, the hard mask layer 287 and the conductive material layer 283 can be completely removed to form a gap between the pairs of memory stacks MS1-MS4. In embodiments, the upper surface of the substrate 210 can be exposed in each gap.

[0121] Figure 27 is a vertical cross-sectional view of an exemplary intermediate structure after an additional etch process that removes the dielectric material layer 251 from the peripheral region 214 of the exemplary structure, as well as a portion of the dielectric material layer 250. Reference is made to Figure 27 The exemplary structure can undergo an additional etch process that can remove the remaining portion of the dielectric material layer 251, and can further remove a portion of the dielectric material layer 250 from the peripheral region 214. A mask (not shown in Figure 28 ) can cover the memory region 212 to protect the memory region 212 from being etched. In some embodiments, the mask can extend over a portion of the second isolation feature IF2, such that a small portion of the dielectric material layer 251 can remain over the second isolation feature IF2 after the etch process.

[0122] Figure 29 is a vertical cross-sectional view of an exemplary intermediate structure showing a BL coating 288 over the exemplary intermediate structure.

[0123] Figure 29 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process that removes the BL coating 288, the memory stacks MS1-MS4, and additional portions of the hard mask layer 287 from the memory region 212. Reference is made to Figure 30The etch process can remove the dielectric material layer 250 of the hard mask HM in each memory stack MS1-MS4. The etch process can also remove some portions of the hard mask layer 287, such that after the etch process, the dielectric material layer 249 of the hard mask HM defines the upper surface of each memory stack MS1-MS4, and the upper surface of the hard mask layer 287 is substantially coplanar with the upper surface of each memory stack MS1-MS4.

[0124] Figure 30 is a vertical cross-sectional view of the exemplary intermediate structure, showing a liner layer 291 over the exposed surfaces of the exemplary structure. Reference is made to Figure 31 The liner layer 291 can include a dielectric material, such as an oxide material, which can be conformally deposited over the exposed surfaces of the exemplary structure in the memory region 212 and the peripheral region 214. The liner layer 291 can be formed using a suitable deposition process as described above.

[0125] Figure 31 is a vertical cross-sectional view of the exemplary intermediate structure, showing a cap layer 293 formed over the liner layer 291, and a BARC layer 295 over the cap layer 293. Reference is made to Figure 32 In various embodiments, the cap layer 293 can protect the structures in the memory region 212 during subsequent processing steps to form logic transistors in the peripheral region 214. In some embodiments, the cap layer 293 can be composed of a semiconductor material, for example, amorphous silicon or polysilicon. Other suitable materials for the cap layer 293 are within the contemplated scope of the present disclosure. The cap layer 293 can be deposited using a suitable deposition process as described above.

[0126] Figure 32 is a vertical cross-sectional view of the exemplary intermediate structure after an etch process that removes the BARC layer 295 and reduces the thickness of the cap layer 293 over the exemplary intermediate structure. Reference is made to Figure 32 After the etch process, the cap layer 293 can have a substantially planar upper surface. A patterned mask PR can be formed over the upper surface of the cap layer 293. The patterned mask can be formed by depositing a photoresist material layer over the cap layer 293, and lithographically patterning the photoresist material to form the patterned mask PR. As Figure 33 The patterned mask PR can completely cover the memory region 212 and can partially extend into the peripheral region 214, as shown. In embodiments, a peripheral edge of the patterned mask PR can be over the second isolation feature IF2. The remaining portion of the peripheral region 214 can be exposed by the patterned mask PR.

[0127] Figure 33is a vertical cross-sectional view of the exemplary intermediate structure after an etch process to remove the cap layer 293, the liner layer 291, the dielectric material layer 250, the dielectric material layer 249, and the control gate layer 247 from the peripheral region 214 of the exemplary intermediate structure. Reference is made to FIG. 2A. Figure 34 An anisotropic etch process can be performed through the patterned mask PR to remove portions of the cap layer 293, the liner layer 291, the dielectric material layer 250, the dielectric material layer 249, and the control gate layer 247 from the peripheral region 214. In some embodiments, the etch process can stop at the blocking layer 245. The etch process can expose side surfaces of the cap layer 293, the liner layer 291, the dielectric material layer 249, and the control gate layer 247 over the second isolation feature IF2. After the etch process, the patterned mask PR can be removed using a suitable process, for example, by ashing or dissolving with a solvent.

[0128] Figure 34 is a vertical cross-sectional view of the exemplary intermediate structure after an additional etch process to remove the blocking layer 245 and the third dielectric layer 240 from the peripheral region 214 of the exemplary intermediate structure. Reference is made to FIG. 2A. Figure 35 An etch process, which can be a wet etch process (e.g., hydrofluoric acid etch), can be performed to remove the blocking layer 245 and the third dielectric layer 240 from the peripheral region 214 and expose the upper surface of the second dielectric material layer 230 and the second isolation feature IF2 in the peripheral region 214. The etch process can also recess the upper surface of the first isolation feature IF1 relative to the upper surface of the second dielectric material layer 230. The etch process can also recess portions of the liner layer 291 and the dielectric material layer 250 that are located over the second isolation feature IF2. During the etch process, the cap layer 293 can protect the storage region 212 from being etched.

[0129] Figure 35 is a vertical cross-sectional view of the exemplary intermediate structure showing additional cap material over the storage region 212 and the peripheral region 214. Reference is made to FIG. 2A. Figure 36 In embodiments, the additional cap material can be composed of the same material as the existing cap layer 293 or can be composed of a different material than the material of the existing cap layer 293. In some embodiments, the additional cap material can be a semiconductor material, for example, amorphous silicon or polysilicon. Other suitable materials are within the contemplated scope of the present disclosure. The additional cap material can be deposited using a suitable deposition process as described above. The additional cap material can increase the thickness of the cap layer 293 in the storage region 212 and can extend the cap layer 293 to cover the peripheral region 214 of the exemplary intermediate structure.

[0130] Figure 36is a vertical cross-sectional view of the exemplary intermediate structure after an etch process to remove the cap layer 293 from the peripheral region 214 of the exemplary intermediate structure. Reference is made to FIG. 3A. Figure 37 An etch process can be performed to remove portions of the cap layer 293 and expose the upper surfaces of the second dielectric layer 230 and the isolation features IF1, IF2 in the peripheral region 214. The etch process can also reduce the thickness of the cap layer 293 in the storage region 212. After the etch process, the cap layer 293 can include tapered sidewalls over the second isolation feature IF2.

[0131] Figure 37 is a vertical cross-sectional view of the exemplary intermediate structure after an additional etch process to remove the second dielectric material layer 230 from the peripheral region 214. Reference is made to FIG. 3A. Figure 38 An etch process, which can be a wet etch process (e.g., phosphoric acid etch), can be performed to remove the second dielectric material layer 230 from the peripheral region 214 and expose the upper surface of the first dielectric material layer / tunnel layer 220. After the etch process, the first and second isolation features IF1, IF2 can protrude above the upper surface of the first dielectric material layer / tunnel layer 220.

[0132] Figure 39 is a vertical cross-sectional view of the exemplary intermediate structure showing a masked ion implantation process performed in the first region 310 of the peripheral region 214. Figure 38 is a vertical cross-sectional view of the exemplary intermediate structure showing a masked ion implantation process performed in the second region 320 of the peripheral region 214. Reference is made to FIG. 3A. Figure 39 and Figure 40 The ion implantation process can be performed in the regions 310, 320 of the peripheral region 214 that can later form logic transistors through the patterned mask PR. In some embodiments, different types of logic transistors can be formed in different regions of the peripheral region 214. For example, in one non-limiting embodiment, a first logic transistor can be formed in the first region 310 of the peripheral region 214 and a second logic transistor, which can be a high voltage logic transistor, can be formed in the second region 320 of the peripheral region. After the implantation process(s), the patterned mask(s) PR can be removed by a suitable process, for example, by ashing or dissolving with a solvent.

[0133] Figure 40 is a vertical cross-sectional view of the exemplary intermediate structure showing a gate dielectric material layer 330 over the exemplary structure, a sacrificial gate material layer 340 over the gate dielectric material layer 330, and a hard mask layer 350 over the sacrificial gate material layer 340. Reference is made to FIG. 3A. Figure 38 In some embodiments, after the gate dielectric material layer 330 is formed over the exemplary structure, a gate dielectric material layer 330 can be formed over the first and second isolation features IF1, IF2 in the peripheral region 214. Figure 39 and Figure 40The first dielectric material layer / tunnel layer 220 can be removed (e.g., by etching) from the peripheral region 214, prior to or after the illustrated ion implantation step. In some embodiments, a planarization process, e.g., a CMP and / or etching process, can be performed such that the upper surfaces of the isolation features IF1, IF2 can be coplanar with the upper surface of the substrate 210 in the peripheral region 214. A gate dielectric material layer 330 can then be deposited over the example intermediate structure, including over the upper surface of the cap layer 293, over the tapered sidewalls of the cap layer 293, and over the upper surfaces of the isolation features IF1, IF2 and the substrate 210 in the peripheral region 214. The gate dielectric material layer 330 can include a suitable dielectric material, e.g., silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (Hf02), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide-aluminum oxide (Hf02-Al203), combinations thereof, and the like. Other suitable dielectric materials are within the contemplated scope of the present disclosure. The gate dielectric material layer 330 can be deposited using a suitable deposition process as described above.

[0134] In some embodiments, the thickness of the gate dielectric material layer 330 can vary in different regions of the peripheral region 214. In one non-limiting example, the thickness of the gate dielectric material layer 330 in a first region 310 of the peripheral region 214 (in which logic transistors can subsequently be formed) can be less than the thickness of the gate dielectric material layer 330 in a second region 320 of the peripheral region 214 (in which high voltage logic transistors can subsequently be formed). In some embodiments, the gate dielectric material layer 330 can have different compositions in different regions 310, 320 of the peripheral region 214.

[0135] Referring again to Figure 40 A sacrificial gate material layer 340 can be formed over the gate dielectric material layer 330. In various embodiments, the sacrificial gate material layer 340 can be used to fabricate dummy gate structures, which can subsequently be replaced by metal gates (e.g., using an RPG process). In some embodiments, the sacrificial gate material layer 340 can be composed of a semiconductor material, such as polysilicon. Other suitable materials are within the contemplated scope of the present disclosure. The sacrificial gate material layer 340 can be deposited using a suitable deposition process as described above.

[0136] Referring again to Figure 41A hardmask layer 350 can be formed over the sacrificial gate material layer 340. The hardmask layer 350 can be composed of a suitable dielectric material, such as a nitride or oxide material, or a combination thereof. The hardmask layer 350 can be deposited using a suitable deposition process as described above.

[0137] Figure 41 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the hardmask layer 350 and a portion of the sacrificial gate material layer 340 from over the cap layer 293. Reference is made to Figure 41 A patterned mask (not shown in Figure 42 ) can be formed over the hardmask layer 350 in the peripheral region 214. An etch process can be performed through the mask to remove the hardmask layer 350 and a portion of the sacrificial gate material layer 340 from over the cap layer 293. The mask can prevent the hardmask layer 350 and the sacrificial gate material layer 340 from being etched in the peripheral region 214.

[0138] Figure 42 is a vertical cross-sectional view of an exemplary intermediate structure showing a plurality of gate stacks GS1, GS2, and GS3 formed over the gate dielectric material layer 330 in the peripheral region 214 of the exemplary intermediate structure. Reference is made to Figure 15 The plurality of gate stacks GS1, GS2, GS3 can be formed in a similar manner as the plurality of memory stacks MS1-MS4 described above with reference to Figure 16 and Figure 42 . Specifically, a patterned mask, such as a photoresist mask PR (not shown in Figure 43 ) can be formed over the exemplary intermediate structure. The mask can be lithographically patterned such that the mask covers selected portions of the hardmask layer 350 that correspond to locations of gate stacks that can be subsequently formed in the peripheral region 214. An anisotropic etch process can be performed to remove portions of the hardmask layer 350 and the sacrificial gate material layer 340 that are exposed through the mask. The etch process can stop at the gate dielectric material layer 330. After the etch process, the plurality of gate stacks GS1-GS3 can be located over the gate dielectric material layer 330 in the peripheral region 214. Each gate stack GS1-GS3 can include the sacrificial gate material layer 340 over the gate dielectric material layer 330, and the hardmask layer 350 over the sacrificial gate material layer 340. After the etch process, the patterned mask PR can be removed using a suitable process, such as by ashing or dissolving with a solvent.

[0139] Figure 43 is a vertical cross-sectional view of an exemplary intermediate structure showing a gate stack side seal layer 351 over side surfaces of the gate stacks GS1-GS3. Reference is made to Figure 44The gate stack side seal layer 351 can include one or more dielectric materials over exposed side surfaces of the hardmask layer 350 and the sacrificial gate material layer 340 in each gate stack GS1-GS3. In one non-limiting embodiment, the gate stack side seal layer 351 can include a nitride material, e.g., silicon nitride. In embodiments, the gate stack side seal layer 351 can be formed by depositing a layer of dielectric material conformally over the intermediate structure, and performing an anisotropic etch process, e.g., a reactive ion etch process, to remove horizontally-extending portions of the layer(s) of dielectric material while leaving the gate stack side seal layer 351 over the side surfaces of the gate stacks GS1-GS3.

[0140] Figure 44 is a vertical cross-sectional view of an exemplary intermediate structure after an etch process to remove the gate dielectric material layer 330 and the cap layer 293 from the storage region 212 of the exemplary intermediate structure. Reference is made to Figure 30 An etch process can be performed to remove the gate dielectric material layer 330 and the cap layer 297. In some embodiments, the etch process can also remove the liner layer 291 (see Figure 45 ). During the etch process, the peripheral region 214 can be covered by a mask to prevent the peripheral region from being etched. The etch process can expose the upper surfaces of the storage stacks MS1-MS4, the upper and side surfaces of the select gate hardmask layer 287, the side surfaces of the conductive material layer 283, and the upper surface of the substrate 210 in the storage region 212. In some embodiments, after the etch process, an ion implantation process can be optionally performed to form active regions (e.g., drain regions) in the substrate 210 between adjacent pairs of storage stacks MS1-MS4.

[0141] Figure 45 is a vertical cross-sectional view of an exemplary intermediate structure schematically illustrating an ion implantation process for forming source and drain regions SD of a logic transistor to be subsequently formed in the peripheral region 214 of the exemplary intermediate structure. Reference is made to Figure 45 One or more ion implantation processes can be performed in the peripheral region 214 to form active regions (i.e., source and drain regions SD) in the substrate 210 adjacent to the gate structures GS1, GS2. In embodiments, the one or more ion implantation processes can be masked implantation processes that can be performed through a patterned mask (not shown in Figure 46 ).

[0142] Figure 46This is a vertical cross-sectional view of an exemplary intermediate structure after an etching process that removes portions of the gate dielectric material layer 330 from the peripheral region 214, forms the main sidewall spacer 297 over the select gate SG in the memory region 212, and forms the main sidewall spacer 353 over the gate stack GS in the peripheral region 214. (See reference...) Figure 46 An anisotropic etching process can be performed to remove the exposed portion of the gate dielectric material layer 330 from the peripheral region 214. The portion of the gate dielectric material 330 below the gate stacks GS1-GS3 can be protected from etching by the gate stacks GS1-GS3. After the etching process, discrete gate dielectric layers 330 can be located below each gate stack GS1-GS3.

[0143] Refer again Figure 46 Alternatively, an etching process can be used to expose the upper surface of the second isolation feature IF2. In an embodiment, the etching process can expose the upper surface of the second isolation feature IF2 in the central portion of the second isolation feature IF2. In the peripheral portion of the second isolation feature IF2, the overlay material may not be completely removed by the etching process, and a dummy (i.e., non-functional) structure may be formed on the surface of the second isolation feature IF2. Figure 46 As shown, for example, the gate stack GS3 that partially covers the second isolation feature IF2 can be partially etched during the etching process. The partially etched gate stack GS3 can form a dummy structure on the second isolation feature IF2. The second dummy structure, including a portion of the control gate layer 247, can be located on the peripheral region of the second isolation feature IF2 adjacent to the memory region 212.

[0144] Refer again Figure 47 A first plurality of main sidewall spacers 297 may be formed on the side surfaces of the select gate SG and the select gate hard mask layer 287 in the storage region 212, and a second plurality of main sidewall spacers 353 may be formed on the side surfaces of the gate stack GS in the peripheral region 214. The main sidewall spacers 297 and 353 may be made of suitable dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, high-k dielectrics, combinations thereof, etc. Other suitable dielectric materials are within the scope of this disclosure. The first plurality of main sidewall spacers 297 and the second plurality of main sidewall spacers 353 may be formed of the same(one or more) materials or different(one or more) materials. The main sidewall spacers 297 and 353 may be formed by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or LPCVD.

[0145] Figure 47 This is a vertical cross-sectional view of an exemplary intermediate structure, showing the metal silicide region 355 on the exposed surface of substrate 210. (Reference)Figure 48 A thin metal layer, e.g., Ti, Ni, W, etc., can be deposited on the exposed upper surface of the substrate 210 in the storage region 212 and the peripheral region 214. The metal can be heated to cause the metal to react with the substrate and form a metal silicide region 355. The metal silicide region 355 can be located over the active (i.e., source and drain) regions of the substrate 210 and can provide an electrical contact layer to the respective source and drain regions DR, SD of the exemplary structure.

[0146] Figure 48 is a vertical cross-sectional view of an exemplary intermediate structure after a planarization process to remove the hard mask HM and remaining portions of the select gate hard mask layer 287 from the storage region 212 and to remove remaining portions of the hard mask layer 350 from the gate stacks GS1-GS3 in the peripheral region 214. Reference is made to Figure 49 A planarization process, e.g., CMP and / or etching process, can be performed to remove remaining portions of the hard mask HM from the storage stacks MS1-MS4, to remove the select gate hard mask layer 287 from over the select gate SG and the erase gate EG, and to remove the hard mask layer 350 from the gate stacks GS1-GS3. After the planarization process, the upper surfaces of the control gate CG, the select gate SG, and the erase gate EG can be exposed in the storage region 212, and the upper surface of the sacrificial gate material layer 340 can be exposed in the peripheral region 214. In various embodiments, the upper surfaces of the control gate CG, the select gate SG, the erase gate EG, and the sacrificial gate material layer 340 can be substantially coplanar.

[0147] Figure 49 is a vertical cross-sectional view of an exemplary intermediate structure showing a contact etch stop layer (CESL) 357 formed conformally over the intermediate structure and an interlayer dielectric (ILD) layer 410 formed over the CESL 357. Reference is made to Figure 50 The CESL 357 and the ILD layer 410 can each be comprised of a suitable dielectric material, e.g., silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass (PSG), undoped silicate glass (USG), doped silicate glass, organosilicate glass, amorphous fluorocarbon, a porous variant thereof, or a combination thereof. Other dielectric materials are within the contemplated scope of the present disclosure. In various embodiments, the CESL 357 can be comprised of a different dielectric material than the ILD layer 410. In some embodiments, the CESL 357 can be an etch stop layer 410 having different etching properties (i.e., higher etch resistance) than the material of the ILD layer 410. In one non-limiting embodiment, the ILD layer 410 can comprise phosphosilicate glass (PSG) and the CESL 357 can comprise silicon nitride. The CESL 357 and the ILD layer 410 can each be deposited using a suitable deposition method as described above.

[0148] Figure 50 is a vertical cross-sectional view of an exemplary intermediate structure after a planarization process to remove the ILD layer 410 and the CESL 357 from over the upper surfaces of the control gate CG, the select gate SG, and the erase gate EG in the memory region 212 and from over the upper surface of the sacrificial gate material layer 340 in the peripheral region 214. Reference is made to Figure 50 A planarization process, e.g., a CMP and / or etch process, can be performed to remove portions of the ILD layer 410 and the CESL 357. After the planarization process, the upper surfaces of the control gate CG, the select gate SG, and the erase gate EG can be exposed in the memory region 212, and the upper surface of the sacrificial gate material layer 340 can be exposed in the peripheral region 214. In various embodiments, the upper surfaces of the control gate CG, the select gate SG, the erase gate EG, and the sacrificial gate material layer 340 can be substantially coplanar.

[0149] Figure 50 The structure of the memory cells MC1-MC4 within the memory region 212 of the exemplary structure is also shown. As described above, each functional memory cell MC in the memory region 212 can include a select gate SG, a floating gate FG, a control gate CG, and an erase gate EG that can be shared with adjacent memory cells MC. In some embodiments, at least some of the memory cells MC can be dummy (i.e., non-functional) memory cells, including at least some memory cells adjacent to the peripheral region 214. As shown, for example, the memory cell MC4 does not include a select gate SG and can be a dummy (i.e., non-functional) memory cell. Figure 51

[0150] Figure 51 is a vertical cross-sectional view of an exemplary intermediate structure showing the formation of metal gates MG1, MG2 in the peripheral region 214. Reference is made to Figure 51 An etch process can be performed to remove the sacrificial gate material layer 340 from the gate stacks GS1 and GS2 in the peripheral region 214. In various embodiments, this etch process can be through a patterned mask (e.g., a photoresist mask) that exposes the sacrificial gate material layer 340 in the peripheral region 214 and protects the gate stacks GS1 and GS2 in the memory region 212. In some embodiments, the etch process can be a wet etch process, e.g., a wet etch process that selectively etches the sacrificial gate material layer 340 relative to the gate stacks GS1 and GS2. Figure 51 ​The patterned mask can be removed after the etching process that removes the sacrificial gate material layer 340. A metal material layer can then be deposited to fill the openings formed in the gate stacks GS1, GS2, and any excess metal material can be removed from above the openings using a planarization process (e.g., a CMP process), leaving metal gates MG1, MG2 in the respective gate stacks GS1, GS2. The metal gates MG1, MG2 can be composed of a suitable metal material, such as aluminum (Al), tantalum (Ta), tungsten (W), titanium (Ti), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), alloys thereof, combinations thereof, etc. Other suitable metal materials are within the contemplated scope of the present disclosure. In some embodiments, each metal gate MG can be composed of the same material. Alternatively, different materials can be used in different gate stacks GS1, GS2 in the peripheral region 214.

[0151] Figure 51 Structures of logic transistors LT1, LT2 within the peripheral region 214 of the example structure are also shown. As described above, each functional logic transistor LT in the peripheral region can include a metal gate MG over a channel region CR of the substrate 210. A gate dielectric layer 330 can be disposed between the metal gate MG and the channel region CR. A source region and a drain region SD can be located on either side of the metal gate MG. The logic transistors LT1, LT2 in the peripheral region 214 can form logic devices, such as memory selectors, power gates, and input / output elements. As described above, different logic transistors LT in different regions of the peripheral region 214 can have different structures and / or perform different functions. For example, in the illustrated embodiment, the logic transistor LT1 in the region 310 can be a logic transistor, and the logic transistor LT2 in the region 320 can be a high-voltage logic transistor. Figure 51 In the illustrated embodiment, the logic transistor LT1 in the region 310 can be a logic transistor, and the logic transistor LT2 in the region 320 can be a high-voltage logic transistor.

[0152] In some embodiments, at least some of the gate structures in the peripheral region can be dummy (i.e., non-functional) gate structures, including at least some of the gate structures adjacent to the peripheral region 214. As described above, for example, the gate structure GS3 does not include a metal gate and can be a dummy (i.e., non-functional) gate structure. Figure 52 As shown, for example, the gate structure GS3 does not include a metal gate and can be a dummy (i.e., non-functional) gate structure.

[0153] Figure 52 is a vertical cross-sectional view of an example intermediate structure showing the first dielectric material layer 102 over the peripheral region 214 as well as over the control gates CG of the memory cells MC in the memory region 212. Reference is made to FIGS. 1-3 for structures not shown. Figure 52In some embodiments, a continuous first dielectric material layer 102 may be deposited over an exemplary intermediate structure, including over the upper surface of a logic transistor LT in the peripheral region 214 and over the upper surface of a memory cell MC in the memory region 212. In some embodiments, the first dielectric material layer 102 may be patterned to remove portions of the layer 102 in the memory region 212. For example, a patterned mask, such as a photoresist mask, may be formed over the continuous first dielectric material layer 102. Figure 53 (Not shown in the image). The mask can be photolithographically patterned such that it covers selected portions of the first dielectric material layer 102, including portions of the first dielectric material layer 102 covering the peripheral region 214 and portions of the first dielectric material layer 102 covering the control gate GC of the memory cell MC. An anisotropic etching process can be performed to remove the portions of the first dielectric material layer 102 exposed through the mask. The etching process can expose portions of the memory region 212 through the first dielectric material layer 102, including the upper surfaces of the select gate SG and erase gate EG of the memory cell MC. After the etching process, the mask can be removed using a suitable process, for example, by ashing or solvent dissolution.

[0154] The first dielectric material layer 102 may be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the first dielectric material layer 102 may be composed of silicon oxide formed using a tetraethyl orthosilicate (TEOS) precursor. In some embodiments, the first dielectric material layer 102 may be a resist-protected oxide (RPO) material. Other suitable dielectric materials are within the scope of this disclosure. In some embodiments, the first dielectric material layer 102 may have good adhesion properties, including good adhesion to one or more materials of the metal gate MG of logic transistors LT1, LT2. The first dielectric material layer 102 may be deposited using a suitable deposition method as described above.

[0155] Figure 53 This is a vertical cross-sectional view of an exemplary intermediate structure, showing a second dielectric material layer 103 above a first dielectric material layer 102 in the peripheral region 214. (Reference) Figure 53 A multilayer composite dielectric film structure 101 can be formed in the peripheral region 214 of the exemplary intermediate structure by depositing at least one additional dielectric material layer 103 over the first dielectric material layer 102. In some embodiments, a continuous second dielectric material layer 103 may be deposited over the exemplary intermediate structure. As described above, a patterned mask, such as a photoresist mask, can be formed over the continuous second dielectric material layer 103. Figure 54(Not shown in the image). A patterned mask can cover the second dielectric material layer 103 in the peripheral region 214 and expose the second dielectric material layer 103 in the storage region 212. An etching process can remove the second dielectric material layer 103 from the storage region 212, and the second dielectric material layer 103 can be located over the first dielectric material layer 102 in the peripheral region 214 to form a composite dielectric film structure 101 in the peripheral region 214. In an embodiment, the composite dielectric film structure 101 can extend continuously over the peripheral region 214, including over the metal gate MG of the logic transistor LT. After the etching process, the mask can be removed using a suitable process, for example, by ashing or solvent dissolution.

[0156] The second dielectric material layer 103 may be composed of a suitable dielectric material, such as an oxide or nitride material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). In some embodiments, the second dielectric material layer 103 may be composed of a buffer oxide material, a silicon nitride material, a high-temperature oxide (HTO) material, etc. Other suitable dielectric materials are within the scope of this disclosure. The second dielectric material layer 103 may have a different composition and / or different physical properties than the first dielectric material layer 102. In various embodiments, the density of the second dielectric material layer 103 may be greater than the density of the first dielectric material layer 102. For example, the density of the second dielectric material layer 103 may be at least 10%, for example, at least 50%, including at least 100%, greater than the density of the first dielectric material layer 102. In some embodiments, the second dielectric material layer 103 may have a lower etch rate (i.e., higher etch resistance) than the material of the first dielectric material layer 102. The second dielectric material layer 103 may be deposited using a suitable deposition method as described above.

[0157] Figure 54 This is a vertical cross-sectional view of an exemplary intermediate structure, showing the metal silicide layer 380 above the upper surfaces of the select gate SG and erase gate EG in memory region 212. (Reference) Figure 54A silicide process can be performed to form a metal silicide layer 380 over the upper surfaces of the select gate SG and erase gate EG of the memory cell MC in the memory region 212 of the exemplary intermediate structure. In various embodiments, a thin layer of metal material, such as Co, Ni, Ti, Ta, W, alloys thereof, etc., can be deposited over the exposed surfaces of the select gate SG and erase gate EG. The metal can be heated to react with the silicon material of the select gate SG and erase gate EG to form the metal silicide layer 380 over the upper surfaces of the select gate SG and erase gate EG. In a non-limiting example, the metal can be annealed at a temperature in the range of 750-1000°C for 1-2 hours. Alternatively, depending on the laser power, the metal can be laser-annealed for a few microseconds to a few seconds. During the silicide process, the control gate CG can be protected by a first dielectric material layer 102 such that the metal silicide layer does not form over the control gate CG.

[0158] After forming a metal silicide layer 380 over the selected gate SG and the erase gate EG, an etching process (e.g., wet etching) can be performed to remove any excess metal from the exemplary intermediate structure. During the etching process, the composite dielectric film structure 101 can protect the metal gate MG in the peripheral region 214 from being etched. As described above, the composite dielectric film structure 101 over the peripheral region 214 can provide improved protection for the metal gate MG. Specifically, due to the presence of... Figure 55 In the multilayer composite dielectric film structure 101 shown, weak points in the first dielectric material layer 102 (e.g., weak points due to the presence of metal deposits from the metal gate MG) may not cause etch damage to the underlying metal gate MG.

[0159] In various embodiments, the peripheral edge 431 of the composite dielectric film structure 101 may be located within ±300 nm (e.g., ±200 nm, e.g., ±100 nm) of the boundary 430 between the storage region 212 and the peripheral region 214. This prevents the composite dielectric film structure 101 from extending too far into the storage region 212, where it might interfere with the siliconization process as described above, or prevents the dielectric film structure 101 from not extending far enough within the peripheral region 214, which could result in insufficient protection of the metal gate MG of the logic transistor LT.

[0160] Figure 55 This is a vertical cross-sectional view of an exemplary intermediate structure, showing an interlayer dielectric (ILD) layer 412 above the intermediate structure, a metal feature 112 above the ILD layer 412, and a conductive via 110 extending between the metal feature 112 and the memory cell MC and the logic transistor LT. Reference Figure 55The ILD layer 412 may be composed of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass (PSG), undoped silicate glass (USG), doped silicate glass, organosilicon glass, amorphous fluorinated carbon, its porous variants, or combinations thereof. Other dielectric materials are within the scope of this disclosure. The ILD layer 412 may be deposited using a suitable deposition process as described above. In embodiments, a planarization process may be used to provide a flat upper surface for the ILD layer 412.

[0161] Refer again Figure 47 Conductive vias 110 can be formed by using an anisotropic etching process to create via openings through ILD layers 410 and 412 and through the composite dielectric film structure 101 in peripheral region 214. In memory region 212, the via openings can extend to the CESL 357 covering each drain region DR of the memory cell MC. In peripheral region 214, the via openings can extend to the CESL 357 covering each source and drain region SD of the logic transistor. The via openings can be extended through the CESL 357 by an etching process to expose contact regions 355 covering each of the respective source and drain regions DR, SD (see [link to image]). Figure 56 Then, the via opening can be filled with a conductive material such as Cu, Ni, Ti, W, Al, or their alloys to form a conductive via 110 that contacts the corresponding source and drain regions DR and SD.

[0162] Metallic features 112 (e.g., conductive lines) may be formed on the ILD layer 412 and may contact one or more conductive vias 110. In some embodiments, the metallic features 112 may be at least partially embedded within the ILD layer 412, such that the bottom surface of the metallic features 112 may be lower than the top surface of the ILD layer 412. In some embodiments, the distance between the bottom surface of the metallic features 112 embedded in the ILD layer 412 and the top surface of the ILD layer 412 may be ≤30 nm.

[0163] Figures 2-51 This is a flowchart illustrating a general method 500 for manufacturing a storage device 100 according to various embodiments of the present disclosure. (See also:) Figure 56 and Figures 2-51 In step 502 of method 500, memory cells MC can be formed in the memory region 212 of substrate 210. (See reference...) Figure 56 and Figures 52-54 In step 504 of method 500, a transistor LT including a metal gate MG can be formed in the peripheral region 214 of the substrate 210. (See reference...) Figure 56 and ​In step 506 of method 500, a composite dielectric film structure 101 may be formed on the metal gate MG of the transistor LT in the peripheral region 214 of the substrate 210. The composite dielectric film structure 101 may include a first dielectric layer 102 and a second dielectric layer 103 above the first dielectric layer 102, wherein the density of the second dielectric layer 103 may be greater than the density of the first dielectric layer 102.

[0164] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor device 100 includes a substrate 210 including a storage region 212 and a peripheral region 214; a transistor LT including a metal gate MG located in the peripheral region 214; a composite dielectric film structure 110 located above the metal gate MG of the transistor LT, the composite dielectric film structure 110 including a first dielectric layer 102 and a second dielectric layer 103 above the first dielectric layer 102, wherein the density of the second dielectric layer 103 is greater than the density of the first dielectric layer 102; and at least one memory cell MC located in the storage region 212.

[0165] In one embodiment, the first dielectric layer 102 is in contact with the upper surface of the metal gate MG of the transistor LT.

[0166] In another embodiment, each of the first dielectric layer 102 and the second dielectric layer 103 has a thickness between 5 nm and 30 nm.

[0167] In another embodiment, the first dielectric layer 102 is made of a dielectric material comprising at least one of silicon oxide formed using a tetraethyl orthosilicate (TEOS) precursor and a resist protective oxide (RPO) material.

[0168] In another embodiment, the second dielectric layer 103 is made of a dielectric material, which includes at least one of a buffer oxide material, a silicon nitride material, and a high-temperature oxide (HTO) material.

[0169] In another embodiment, the lower surface of the composite dielectric film structure 101 is coplanar with the upper surface of at least one memory cell MC.

[0170] In another embodiment, at least one memory cell MC includes a floating gate FG, a control gate CG located above the floating gate FG, and a selection gate SG located on a first side of the floating gate FG and the control gate CG, wherein the lower surface of the composite dielectric film structure 101 is coplanar with the upper surface of the control gate CG.

[0171] In another embodiment, at least one memory cell further includes an erase gate EG located on a second side of the floating gate FG and the control gate CG, wherein a metal silicide layer 380 is located on the upper surface of the select gate SG and the upper surface of the erase gate EG.

[0172] In another embodiment, the semiconductor device 100 includes a plurality of transistors LT, the plurality of transistors LT including a metal gate MG located in a peripheral region 214 and a plurality of memory cells MC located in a memory region 212, and a composite dielectric film structure 101 is located above the metal gate MG of the plurality of transistors LT in the peripheral region 214, and the composite dielectric film structure 101 is not located above the memory cells MC in the memory region 212.

[0173] An additional embodiment relates to a semiconductor device 100, comprising: a substrate 210 including a storage region 212 and a peripheral region 214; a plurality of storage cells MC located in the storage region 212; a plurality of transistors LT located in the peripheral region 214; and a composite dielectric film structure 101 including at least two dielectric material layers 102, 103 extending over the plurality of transistors LT in the peripheral region 214, wherein the peripheral edge 431 of the composite dielectric film structure 101 is located within 300 nm of the boundary 430 between the storage region 212 and the peripheral region 214.

[0174] In one embodiment, the boundary 430 between the storage region 212 and the peripheral region 214 is defined by the peripheral edge of the isolation feature IF2 located in the substrate 210.

[0175] In another embodiment, the upper surface of substrate 210 is recessed in storage region 212 relative to the upper surface of substrate 210 in peripheral region 214.

[0176] In another embodiment, the semiconductor device 100 further includes a plurality of conductive vias 110 extending through the composite dielectric film structure 101, wherein the composite dielectric film structure 101 extends continuously between the conductive vias 110 in the peripheral region 214.

[0177] In another embodiment, each of the transistors LT in the peripheral region 214 includes a metal gate MG, and the composite dielectric film structure 101 is located above the metal gate MG of the plurality of transistors LT in the peripheral region 214.

[0178] In another embodiment, the composite dielectric film structure 101 includes at least two dielectric material layers 102, 103 with different compositions and / or physical properties.

[0179] An additional embodiment relates to a method of manufacturing a semiconductor device 100, comprising: forming a memory cell MC in a memory region 212 of a substrate 210; forming a transistor LT including a metal gate MG in a peripheral region 212 of the substrate 210; forming a composite dielectric film structure 101 on the metal gate MG of the transistor LT in a peripheral region 214 of the substrate 210, wherein the composite dielectric film structure 101 includes a first dielectric layer 102 and a second dielectric layer 103 on the first dielectric layer 102, and the density of the second dielectric layer 103 is greater than the density of the first dielectric layer 102; and performing wet etching to remove metal material from the semiconductor device 100, wherein the composite dielectric film structure 101 protects the metal gate MG of the transistor LT in the peripheral region 214 from being etched.

[0180] In one embodiment, forming a composite dielectric film structure includes: forming a first dielectric layer 102 on the metal gate MG of a transistor LT in the peripheral region 214 and on the control gate CG of a memory cell MC in the storage region 212, and forming a second dielectric layer 103 on the first dielectric layer 102 in the peripheral region 214 to form a composite dielectric film structure 101, wherein the composite dielectric film structure 101 does not extend on the memory cell MC in the storage region 212 of the semiconductor device 100.

[0181] In another embodiment, the method further includes forming a metal silicide layer 380 over the upper surface of at least one of the select gate SG and the erase gate EG of the memory cell MC, wherein a portion of the first dielectric layer 102 is located over the control gate CG of the memory cell MC during the formation of the metal silicide layer 380.

[0182] In another embodiment, forming the metal silicide layer 380 includes: depositing a metal layer over at least one of the select gate SG and the erase gate EG of the memory cell MC, and heating the metal layer to form the metal silicide layer 380 over the upper surface of at least one of the select gate SG and the erase gate EG of the memory cell MG, wherein excess metal is removed from the semiconductor device 101 during wet etching.

[0183] In another embodiment, the method further includes forming a conductive via 110 that passes through the composite dielectric film structure 101 and makes electrical contact with the source or drain region SD of the transistor LT in the peripheral region 214.

[0184] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0185] Example 1 is a semiconductor device comprising: a substrate including a storage region and a peripheral region; a transistor including a metal gate located in the peripheral region; a composite dielectric film structure located above the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer above the first dielectric layer, wherein the density of the second dielectric layer is greater than the density of the first dielectric layer; and at least one storage cell located in the storage region.

[0186] Example 2 is the semiconductor device described in Example 1, wherein the first dielectric layer is in contact with the upper surface of the metal gate of the transistor.

[0187] Example 3 is the semiconductor device described in Example 1, wherein each of the first dielectric layer and the second dielectric layer has a thickness between 5 nm and 30 nm.

[0188] Example 4 is the semiconductor device described in Example 1, wherein the first dielectric layer comprises a dielectric material comprising at least one of the following: silicon oxide formed using a tetraethyl orthosilicate (TEOS) precursor, or a resist protective oxide (RPO) material.

[0189] Example 5 is the semiconductor device described in Example 1, wherein the second dielectric layer comprises a dielectric material, which comprises at least one of a buffer oxide material, a silicon nitride material, and a high-temperature oxide (HTO) material.

[0190] Example 6 is the semiconductor device described in Example 1, wherein the lower surface of the composite dielectric film structure is coplanar with the upper surface of the at least one memory cell.

[0191] Example 7 is the semiconductor device described in Example 6, wherein the at least one memory cell includes: a floating gate; a control gate located above the floating gate; and a selection gate located on a first side of the floating gate and the control gate, wherein the lower surface of the composite dielectric film structure is coplanar with the upper surface of the control gate.

[0192] Example 8 is the semiconductor device described in Example 7, wherein the at least one memory cell further includes an erase gate located on a second side of the floating gate and the control gate, wherein a metal silicide layer is located on the upper surface of the select gate and the upper surface of the erase gate.

[0193] Example 9 is the semiconductor device described in Example 1, wherein the semiconductor device includes a plurality of transistors, the plurality of transistors including a metal gate located in the peripheral region and a plurality of memory cells located in the memory region, and wherein the composite dielectric film structure is located above the metal gate of the plurality of transistors in the peripheral region, and the composite dielectric film structure is not located above the plurality of memory cells in the memory region.

[0194] Example 10 is a semiconductor device comprising: a substrate including a storage region and a peripheral region; a plurality of storage cells located in the storage region; a plurality of transistors located in the peripheral region; and a composite dielectric film structure including at least two dielectric material layers extending over the plurality of transistors in the peripheral region, wherein the peripheral edge of the composite dielectric film structure is located within 300 nm of the boundary between the storage region and the peripheral region.

[0195] Example 11 is the semiconductor device described in Example 10, wherein the boundary between the storage region and the peripheral region is defined by the peripheral edge of an isolation feature located in the substrate.

[0196] Example 12 is the semiconductor device described in Example 10, wherein the upper surface of the substrate is recessed in the storage region relative to the upper surface of the substrate in the peripheral region.

[0197] Example 13 is the semiconductor device described in Example 10, further comprising: a plurality of conductive vias extending through the composite dielectric film structure, wherein the composite dielectric film structure extends continuously between the conductive vias in the peripheral region.

[0198] Example 14 is the semiconductor device described in Example 10, wherein each of the transistors in the peripheral region includes a metal gate, and the composite dielectric film structure is located above the metal gates of the plurality of transistors in the peripheral region.

[0199] Example 15 is the semiconductor device described in Example 10, wherein the composite dielectric film structure comprises at least two dielectric material layers having different compositions and / or physical properties.

[0200] Example 16 is a method of manufacturing a semiconductor device, comprising: forming a memory cell in a memory region of a substrate; forming a transistor including a metal gate in a peripheral region of the substrate; forming a composite dielectric film structure over the metal gate of the transistor in the peripheral region of the substrate, wherein the composite dielectric film structure includes a first dielectric layer and a second dielectric layer over the first dielectric layer, and the density of the second dielectric layer is greater than the density of the first dielectric layer; and performing wet etching to remove metal material from the semiconductor device, wherein the composite dielectric film structure protects the metal gate of the transistor in the peripheral region from etching.

[0201] Example 17 is the method of Example 16, wherein forming the composite dielectric film structure includes: forming a first dielectric layer over a metal gate of a transistor in the peripheral region and over a control gate of a memory cell in the memory region; and forming a second dielectric layer over the first dielectric layer in the peripheral region to form the composite dielectric film structure, wherein the composite dielectric film structure does not extend over the memory cell in the memory region of the semiconductor device.

[0202] Example 18 is the method of Example 17, further comprising: forming a metal silicide layer over the upper surface of at least one of the select gate and the erase gate of the memory cell, wherein, during the formation of the metal silicide layer, a portion of the first dielectric layer is located over the control gate of the memory cell.

[0203] Example 19 is the method of Example 18, wherein forming the metal silicide layer includes: depositing a metal layer over at least one of the select gate and erase gate of the memory cell; and heating the metal layer to form the metal silicide layer over the upper surface of at least one of the select gate and erase gate of the memory cell, wherein excess metal is removed from the semiconductor device during the wet etching.

[0204] Example 20 is the method of Example 17, further comprising: forming a conductive via that passes through the composite dielectric film structure and makes electrical contact with the source or drain region of the transistor in the peripheral region.

Claims

1. A semiconductor device, comprising: The substrate includes the storage region and the peripheral region; A transistor, including a metal gate located in the peripheral region; A composite dielectric film structure is located above the metal gate of the transistor. The composite dielectric film structure includes a first dielectric layer and a second dielectric layer above the first dielectric layer, and the density of the second dielectric layer is greater than the density of the first dielectric layer. as well as At least one storage unit is located in the storage area; The lower surface of the composite dielectric film structure is coplanar with the upper surface of the at least one memory cell.

2. The semiconductor device according to claim 1, wherein, The first dielectric layer is in contact with the upper surface of the metal gate of the transistor.

3. The semiconductor device according to claim 1, wherein, Each of the first dielectric layer and the second dielectric layer has a thickness between 5 nm and 30 nm.

4. The semiconductor device according to claim 1, wherein, The first dielectric layer includes a dielectric material comprising at least one of the following: silicon oxide formed using a tetraethyl orthosilicate (TEOS) precursor, or a resist protective oxide (RPO) material.

5. The semiconductor device according to claim 1, wherein, The second dielectric layer includes a dielectric material, which includes at least one of a buffer oxide material, a silicon nitride material, and a high-temperature oxide (HTO) material.

6. The semiconductor device according to claim 1, wherein, The at least one storage unit includes: Floating gate; The control gate located above the floating gate; and A selection gate located on the first side of the floating gate and the control gate, wherein the lower surface of the composite dielectric film structure is coplanar with the upper surface of the control gate.

7. The semiconductor device according to claim 6, wherein, The at least one storage unit further includes: An erase gate is located on the second side of the floating gate and the control gate, wherein a metal silicide layer is located on the upper surface of the select gate and the upper surface of the erase gate.

8. The semiconductor device according to claim 1, wherein, The semiconductor device includes a plurality of transistors, the plurality of transistors including a metal gate located in the peripheral region and a plurality of memory cells located in the memory region, wherein the composite dielectric film structure is located above the metal gate of the plurality of transistors in the peripheral region and is not located above the plurality of memory cells in the memory region.

9. A semiconductor device, comprising: The substrate includes the storage region and the peripheral region; Multiple storage units are located in the storage area; Multiple transistors are located in the peripheral region; as well as A composite dielectric film structure includes at least two dielectric material layers extending over the plurality of transistors in the peripheral region, wherein the peripheral edge of the composite dielectric film structure is located within 300 nm of the boundary between the storage region and the peripheral region, and the lower surface of the composite dielectric film structure is coplanar with the upper surface of the plurality of storage cells.

10. The semiconductor device according to claim 9, wherein, The boundary between the storage region and the peripheral region is defined by the peripheral edge of an isolation feature located in the substrate.

11. The semiconductor device according to claim 9, wherein, The upper surface of the substrate is recessed in the storage region relative to the upper surface of the substrate in the peripheral region.

12. The semiconductor device according to claim 9, further comprising: Multiple conductive vias extend through the composite dielectric film structure, wherein the composite dielectric film structure extends continuously between the conductive vias in the peripheral region.

13. The semiconductor device according to claim 9, wherein, Each of the transistors in the peripheral region includes a metal gate, and the composite dielectric film structure is located above the metal gates of the plurality of transistors in the peripheral region.

14. The semiconductor device according to claim 9, wherein, The composite dielectric film structure comprises at least two dielectric material layers with different compositions and / or physical properties.

15. A method for manufacturing a semiconductor device, comprising: Memory cells are formed in the memory region of the substrate; A transistor including a metal gate is formed in the peripheral region of the substrate; A composite dielectric film structure is formed on the metal gate of a transistor in the peripheral region of the substrate. The composite dielectric film structure includes a first dielectric layer and a second dielectric layer above the first dielectric layer, wherein the density of the second dielectric layer is greater than the density of the first dielectric layer, and the lower surface of the composite dielectric film structure is coplanar with the upper surface of the memory cell. Wet etching is performed to remove metal material from the semiconductor device, wherein the composite dielectric film structure protects the metal gate of the transistor in the peripheral region from being etched.

16. The method according to claim 15, wherein, Forming the composite dielectric film structure includes: The first dielectric layer is formed on the metal gate of the transistor in the peripheral region and on the control gate of the memory cell in the memory region; and A second dielectric layer is formed on top of a first dielectric layer in the peripheral region to form the composite dielectric film structure, wherein the composite dielectric film structure does not extend over the memory cells in the memory region of the semiconductor device.

17. The method of claim 16, further comprising: A metal silicide layer is formed over the upper surface of at least one of the select gate and erase gate of the memory cell, wherein, during the formation of the metal silicide layer, a portion of the first dielectric layer is located over the control gate of the memory cell.

18. The method according to claim 17, wherein, Forming the metal silicide layer includes: Deposit a metal layer over at least one of the select gate and erase gate of the memory cell; and The metal layer is heated to form the metal silicide layer over the upper surface of at least one of the select gate and erase gate of the memory cell, wherein excess metal is removed from the semiconductor device during the wet etching process.

19. The method of claim 16, further comprising: A conductive via is formed, which passes through the composite dielectric film structure and makes electrical contact with the source or drain region of the transistor in the peripheral region.

Images