Display panel, preparation method thereof, display module and display device

Abstract

Embodiments of the present application disclose a display panel and a preparation method thereof, a display module and a display device. The display panel comprises a first substrate, a signal line, a second substrate and a fan-out line. The first substrate has a first side and a second side opposite in the thickness direction of the first substrate. The signal line is arranged on the first side of the first substrate. The second substrate is arranged on the second side of the first substrate. The fan-out line is arranged between the first substrate and the second substrate. A via hole is formed in the first substrate, and the signal line is coupled with the fan-out line at the via hole. In the display panel provided by the embodiments, the fan-out line is coupled with the signal line and located on the side of the first substrate away from the signal line, so that the fan-out line is more convenient to connect with a circuit board, and thus the display panel does not need to be provided with a bending area, the frame width of the display panel is reduced, and a narrower frame can be realized. Moreover, the requirement of the display panel on the flexibility of the first substrate is also reduced.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its manufacturing method, a display module, and a display device. Background Technology

[0002] In recent years, display devices with narrow bezels have received widespread acclaim from users. Currently, narrow bezels are typically achieved by bonding the circuit board to the display panel using a flexible chip-on-film (COF) film, and then bending the flexible COF to the back of the display panel. However, this method still results in a certain width of bezel remaining at the bonding end of the display panel. Summary of the Invention

[0003] This application provides a display panel and its manufacturing method, a display module, and a display device for reducing the bezel width of the display panel.

[0004] On one hand, a display panel is provided, including a first substrate, signal lines, a second substrate, and fan-out lines. The first substrate has a first side and a second side opposite to each other in the thickness direction of the first substrate. The signal lines are disposed on the first side of the first substrate. The second substrate is disposed on the second side of the first substrate. The fan-out lines are disposed between the first substrate and the second substrate. A via is formed in the first substrate, and the signal lines are coupled to the fan-out lines at the vias. Because the fan-out lines are coupled to the signal lines and located on the side of the first substrate opposite to the signal lines, the connection between the fan-out lines and the circuit board is more convenient. Therefore, the display panel does not need to have a bending area, the bezel width of the display panel is reduced, and a narrower bezel can be achieved. Furthermore, it also reduces the flexibility requirements of the first substrate for the display panel.

[0005] In some embodiments, a first opening is provided on the second substrate, the first opening exposing at least a portion of the fan-out line; or, the fan-out line is blocked by the second substrate.

[0006] In some embodiments, a portion of the signal line is embedded in a via and contacts a portion of the fan-out line that is exposed by the via.

[0007] In some embodiments, the display panel has a display area and a non-display area surrounding the display area; vias are located within the non-display area.

[0008] On the other hand, a display module is provided, including the aforementioned display panel and circuit board. The circuit board is disposed on the side of the second substrate of the display panel away from the first substrate and is coupled to a fan-out line in the display panel. Since the display module includes the aforementioned display panel, it has the same beneficial effects, which will not be described in detail here.

[0009] In some embodiments, a first opening is formed on the second substrate, the first opening exposing at least a portion of the fan-out line. At the first opening, the circuit board is coupled to the fan-out line.

[0010] In some embodiments, the circuit further includes an insulating protective layer and a first conductive adhesive film. The insulating protective layer covers the portion of the fan-out line exposed by the first opening. The first conductive adhesive film is bonded between the circuit board and the insulating protective layer. The first conductive adhesive film contains a plurality of first conductive particles, each of which has a plurality of first protrusions on its surface. At least a portion of the first protrusions of the first conductive particles penetrate the insulating protective layer and contact the portion of the fan-out line exposed by the first opening.

[0011] In some embodiments, the first protrusion has a pointed end at one end of the surface away from the first conductive particle.

[0012] In some embodiments, the second substrate isolates the fan-out line from the circuit board;

[0013] The display module also includes a second conductive adhesive film. The second conductive adhesive film is bonded between the circuit board and the second substrate; a plurality of second conductive particles are dispersed in the second conductive adhesive film, and each second conductive particle has a plurality of second protrusions on its surface, at least a portion of the second protrusions of the second conductive particle penetrating the second substrate and contacting the fan-out line.

[0014] In some embodiments, the second substrate includes opposing first and second surfaces, with the second surface being farther away from the first substrate than the first surface. A groove is provided on either the first or second surface of the second substrate. At the groove, at least a portion of the second protrusions of the second conductive particles penetrates the second substrate and contacts the fan-out line.

[0015] In some embodiments, the thickness of the second substrate is less than the thickness of the first substrate.

[0016] In some embodiments, a buffer is also included. The buffer is disposed between the second substrate and the circuit board, and is located around the coupling position of the circuit board and the fan-out line.

[0017] In another aspect, a display device is provided, including the aforementioned display module.

[0018] On another front, a method for manufacturing a display panel is provided, comprising:

[0019] Fan-out lines are formed on the second substrate;

[0020] A first substrate is formed on the side of the fan-out line away from the second substrate, and a via is formed on the first substrate;

[0021] Signal lines are formed on the side of the first substrate away from the second substrate; at vias, the signal lines are coupled to fan-out lines.

[0022] The manufacturing method of the display panel includes the corresponding technical features of the display panel mentioned above, and therefore has the same beneficial effects, so it will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1A A side view of a display panel according to some embodiments;

[0025] Figure 1B for Figure 1A The rear view of the display panel;

[0026] Figure 2 This is an equivalent circuit diagram of pixel driving circuits and signal lines in a display panel according to some embodiments;

[0027] Figure 3 This is a schematic diagram of the wiring connections for the display panel in some embodiments;

[0028] Figure 4 for Figure 3 A cross-sectional view at A1-A2;

[0029] Figure 5 for Figure 3 Another possible cross-sectional view at A1-A2;

[0030] Figure 6A This is a schematic diagram of the wiring connections for the display panel in some embodiments;

[0031] Figure 6B for Figure 6A Cross-sectional view at B1-B2;

[0032] Figure 7 for Figure 6A Another possible cross-sectional view at B1-B2;

[0033] Figure 8 This is a schematic diagram of the structure of a first conductive particle according to some embodiments;

[0034] Figure 9 for Figure 6A Another possible cross-sectional view at B1-B2;

[0035] Figure 10 for Figure 6A Another possible cross-sectional view at B1-B2;

[0036] Figure 11 for Figure 6A Another possible cross-sectional view at B1-B2;

[0037] Figure 12 for Figure 6A Another possible cross-sectional view at B1-B2;

[0038] Figure 13 This is a schematic diagram of the rear of a splicing display device according to some embodiments;

[0039] Figure 14 for Figure 13 A front view of the splicing display device;

[0040] Figure 15 A flowchart illustrating a method for manufacturing a display panel according to some embodiments;

[0041] Figure 16 This is a flowchart of a method for manufacturing a display module according to some embodiments;

[0042] Figure 17 This is a process diagram for setting a temporary protective film according to some embodiments;

[0043] Figure 18 This is a process diagram for penetrating a temporary protective film according to some embodiments.

[0044] Figure label:

[0045] 10. Display module;

[0046] 100, Display panel; 100A, Display side; 100B, Non-display side; SA, Non-display area; AA, Display area;

[0047] 200, Circuit board; 210, Second pin;

[0048] 300. Buffer components;

[0049] 400. Temporary protective film;

[0050] L1, First circuit layer; L2, Second circuit layer; L3, Light-emitting device layer; L4, Encapsulation layer; L5, Insulating protective layer;

[0051] 110, First substrate; 110A, First side; 110B, Second side;

[0052] 120, Signal line; 130, Second substrate; 130A, First surface; 130B, Second surface; 131, Groove; 140, Fan-out line; 141, First pin; 150, Via; 160, First opening;

[0053] 170. First conductive adhesive film;

[0054] 172. First conductive particle; 173. First protrusion; 174. Tip;

[0055] 180. Second conductive adhesive film;

[0056] 182. Second conductive particle; 183. Second protrusion;

[0057] 190. Third conductive adhesive film;

[0058] 192. The third conductive particle. Detailed Implementation

[0059] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0060] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0061] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0062] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0063] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0064] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0065] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0066] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0067] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0068] As used herein, “about,” “approximately,” or “approximately” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0069] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where the acceptable range of deviation for approximate parallelism can be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where the acceptable range of deviation for approximate perpendicularity can also be, for example, within 5°. “equal” includes absolute equality and approximate equality, where the acceptable range of deviation for approximate equality can be, for example, the difference between the two equals being less than or equal to 5% of either one.

[0070] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0071] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0072] Some embodiments of this disclosure provide a display device. The display device is a product with image display capabilities (including still images or moving images, where moving images can be video). For example, the display device can be any of the following: a monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following: a microdisplay, a VR device or AR device containing a microdisplay, etc.

[0073] The display device may include a display module. The display module is the main body of the display device and is configured to receive image data and display corresponding images based on the image data. The display device may also include a processor; the processor is coupled to the display module and configured to output image data to the display module. Furthermore, the display device may include a housing; the housing is fixedly connected to the display module and configured to protect the display module.

[0074] Figure 1A To display the side view of the module. Figure 1B To display the rear view of the module.

[0075] See Figure 1A and Figure 1B The display module 10 includes a display panel 100 and a circuit board 200 coupled to the display panel 100.

[0076] The circuit board 200 can be a rigid circuit board, such as a printed circuit board (PCB); it can also be a flexible circuit board, such as a flexible printed circuit board (FPC); or it can be a soft and hard combination plate.

[0077] The circuit board 200 is configured to transmit electrical signals to the display panel 100, and the circuit board 200 has a second pin 210 configured to be coupled to the display panel 100. In some possible implementations, the display module 10 also includes a display driver; the display driver is configured to provide electrical signals to the display panel 100, which are transmitted to the display panel 100 via the circuit board 200. The display driver may include at least one (e.g., one, or more) driver chip 500; wherein some or all of the driver chips 500 may be disposed on the circuit board 200, integrated with the circuit board 200 to form, for example, a chip on film (COF). Exemplarily, the display driver may include a source driver IC configured to provide data drive signals (also called data signals) to the display panel 100. The display driver may also include a timer control register (TCON) coupled to the source driver.

[0078] Display panel 100 is configured to receive electrical signals transmitted by circuit board 200 and display images under the drive of these electrical signals. Exemplarily, display panel 100 may be an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a Liquid Crystal Display (LCD), or a microLED (including miniLED or microLED, where LED is a light-emitting diode) display panel, etc. This document uses an OLED display panel as an example for illustration.

[0079] See also Figure 1A The display panel 100 has a display side 100A and a non-display side 100B. The display side 100A is the side of the display panel 100 capable of displaying images; when the human eye is on the display side 100A, the image displayed on the display panel 100 can be viewed. The non-display side 100B is opposite to the display side 100A. The circuit board 200 is located on the non-display side 100B of the display panel 100.

[0080] See also Figure 1B The display panel 100 has a display area AA and a non-display area SA located around the display area. The non-display area SA is located on at least one side outside the display area AA (e.g., one side; or, around the perimeter, including the top and bottom sides and the left and right sides). Figure 1BIn the diagram, the first direction X is the extension direction of one side of the display area AA, such as the extension direction of the long side; the second direction Y is the extension direction of the other side of the display area AA, such as the extension direction of the short side; and the third direction Z is the thickness direction of the display panel 100. Figure 1A The first direction X, the second direction Y, and the third direction Z can also be understood in this way.

[0081] Figure 2 This is an equivalent circuit diagram of the pixel driving circuit and signal lines in the display panel.

[0082] See Figure 2 The display panel 100 may have multiple sub-pixels P in the display area AA. Exemplarily, a sub-pixel P (e.g., each sub-pixel P) may include a light-emitting device EL and a pixel driving circuit EC coupled to the light-emitting device EL. The pixel driving circuit EC may include multiple transistors and at least one (e.g., one) capacitor. For example, the pixel driving circuit EC may be a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a capacitor, and the number before "C" indicates the number of capacitors. The layer containing the light-emitting device EL is the light-emitting device layer, and an encapsulation layer is also provided above the light-emitting device EL.

[0083] See also Figure 2 The display panel 100 may also include multiple signal lines that are coupled to the circuit board 200 and configured to receive electrical signals provided by the display driver.

[0084] The multiple signal lines in the display panel 100 can be classified into various types according to the different electrical signals they transmit.

[0085] For example, see Figure 2 A signal line can be coupled (e.g., directly connected) to the pixel driving circuit EC of a sub-pixel P to provide an electrical signal to the pixel driving circuit EC in that sub-pixel P, thereby driving the light-emitting device EL in that sub-pixel P to emit light. For example, as Figure 2 As shown, the various signal lines may include some or all of the following: gate line GL, data signal line DL, first power supply voltage line VS, second power supply voltage line VD, and light emission control signal line EM. Specifically, gate line GL is configured to provide a scan signal to the pixel driving circuit EC; data signal line DL is configured to provide a data signal to the pixel driving circuit EC; first power supply voltage line VS is configured to provide a constant first power supply voltage signal (ELVSS) to the pixel driving circuit EC; and second power supply voltage line VD is configured to provide a constant second power supply voltage signal (ELVDD) to the pixel driving circuit EC.

[0086] For example, see also Figure 2 A signal line can also be indirectly connected to the pixel driving circuit EC in a sub-pixel P. For example, the display panel 100 also includes a first gate driver GOA1 coupled to multiple gate lines G and a second gate driver GOA2 coupled to multiple light emission control signal lines EM. Some of the multiple signal lines mentioned above can be coupled to the first gate driver GOA1 and the second gate driver GOA2, and these signal lines can be collectively referred to as the input signal lines of the gate driver. The first gate driver GOA1 and the second gate driver GOA2 are configured to output corresponding scan signals to the multiple gate lines G in response to the electrical signals transmitted on these input signal lines. These input signal lines can include at least one of a trigger signal line STV and a clock signal line CLK. The trigger signal line STV is configured to input a trigger signal to the gate driver, and the clock signal line is configured to input a clock signal to the gate driver.

[0087] It should be noted that, in this article, a signal line refers to a wire that transmits the same signal. This signal line may be located in one conductive pattern layer or distributed in different conductive pattern layers. For example, a signal line may include at least two mutually coupled line segments, some of which are located in one conductive pattern layer and others in another conductive pattern layer.

[0088] In embodiments of this disclosure, the conductive patterned layer is a patterned layer with conductive properties, such as a patterned layer made of a conductive material. The "patterned layer" can be a layer structure containing a specific pattern formed by forming at least one film layer using the same film deposition process, and then performing a patterning process on this at least one film layer. Depending on the specific pattern, the patterning process may include multiple coating, exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights (or thicknesses).

[0089] Figure 3 Rear view of the wiring connections for the display panel (viewed from the non-display side). Figure 4 for Figure 3 The cross-sectional view at A1-A2.

[0090] See Figure 4 The display panel 100 includes a first substrate 110, a first circuit layer L1, a second substrate 130, and a second circuit layer L2. The first circuit layer L1, the first substrate 110, the second circuit layer L2, and the second substrate 130 are arranged sequentially in the third direction Z.

[0091] The first substrate 110 is configured to carry the first circuit layer L1. The first substrate 110 can be a rigid substrate or a flexible substrate. The rigid substrate includes, for example, at least one of a glass substrate, a PMMA (polymethyl methacrylate) substrate, a quartz substrate, and a metal substrate. The flexible substrate includes, for example, at least one of a PET (polyethylene terephthalate) substrate, a PEN (polyethylene naphthalate dimethyl methacrylate) substrate, and a PI (polyimide) substrate.

[0092] The first substrate 110 has a first side 110A and a second side 110B opposite each other in the thickness direction (i.e., the third direction Z) of the first substrate 110. The first side 110A is the side of the first substrate 110 that is pointed to by an arrow in the third direction Z, and the second side 110B is the side of the first substrate 110 that is pointed to in the opposite direction in the third direction Z. The first substrate 110 is provided with at least one (e.g., multiple) vias 150 that penetrate the first substrate 110.

[0093] See Figure 3 and Figure 4 The first circuit layer L1 is located on the first side 110A of the first substrate 110 and may include multiple signal lines 120; that is, multiple signal lines 120 are disposed on the first side 110A of the first substrate 110. Exemplarily, the first circuit layer L1 may include the pixel driving circuit EC described above and at least a portion (e.g., a portion, or all) of all the signal lines 120. Of all the signal lines 120 included in the first circuit layer L1, at least one (e.g., one, or multiple) signal line 120 is coupled to the second circuit layer L2; among these signal lines 120, one (e.g., each) signal line 120 may be coupled to the second circuit layer L2 through at least one (e.g., one, or multiple) via 150 on the first substrate 110. For example, the signal line 120 and the via 150 on the first substrate 110 have overlapping (i.e., at least partially overlapping) orthogonal projections on the first substrate 110. For example, the orthographic projection of the via 150 on the first substrate 110 is covered by the orthographic projection of the signal line 120 on the first substrate 110. Alternatively, in the orthographic projection of the via 150 on the first substrate 110, a portion is covered by the orthographic projection of the signal line 120 on the first substrate 110, while the remaining portion is not covered by the orthographic projection of the signal line 120 on the first substrate 110.

[0094] The second substrate 130 is disposed on the second side 110B of the first substrate 110. The material of the second substrate 130 may be the same as or different from that of the first substrate 110. The second substrate 130 may be configured to carry a second circuit layer L2.

[0095] The second circuit layer L2 is disposed on the second side 110B of the first substrate 110, specifically, between the first substrate 110 and the second substrate 130. The second circuit layer L2 includes at least one (e.g., multiple) fan-out lines 140. The fan-out lines 140 connect the circuit board 200 and the signal line 120, that is, they are transmission lines that transmit electrical signals from the circuit board 200 to the signal line 120.

[0096] For example, multiple fan-out lines 140 and multiple signal lines 120 can be coupled one-to-one. For instance, a data signal line 120DL is coupled to a fan-out line 140.

[0097] As another example, a fan-out line 140 may be coupled to at least two signal lines 120, in which case these signal lines 120 transmit the same electrical signal. For example, multiple second power supply voltage lines VD are coupled to a fan-out line 140.

[0098] A signal line 120 is coupled to a fan-out line 140 at at least one (e.g., one, or more) via 150 on the first substrate 110. For example, the signal line 120 is coupled to the fan-out line 140 through a via 150. In this case, the orthographic projections of the via 150, the fan-out line 140, and the signal line 120 on the first substrate 110 overlap (at least partially overlap, see the explanation above). For example, the orthographic projection of the via 150 on the first substrate 110 is covered by both the orthographic projection of the signal line 120 and the orthographic projection of the fan-out line 140 on the first substrate 110.

[0099] See also Figure 4 In some embodiments, a portion of the signal line 120 is embedded in the via 150 and contacts a portion of the fan-out line 140 exposed by the via 150.

[0100] Specifically, the fan-out line 140 in the second circuit layer L2 is located on the second side 110B of the first substrate 110, and the via 150 penetrates the first substrate 110. Viewed from the first substrate 110 towards the second circuit layer L2, a portion of the fan-out line 140 is exposed within the opening of the via 150; that is, the orthographic projection of this portion of the fan-out line 140 onto the first substrate 110 is covered by the orthographic projection of the via 150 onto the first substrate 110. A portion of the signal line 120 is embedded in the via 150 and extends towards the second side 110B of the first substrate 110, contacting the portion of the fan-out line 140 exposed in the via 150, thus forming a coupling. This structure can be adapted to a simpler manufacturing process for the display panel 100.

[0101] In one possible implementation, a second circuit layer L2, a first substrate 110, and a first circuit layer L1 may be sequentially formed on a second substrate 130. Exemplarily, the first circuit layer L1 may include a first conductive pattern layer and a second conductive pattern layer located on the side of the first conductive pattern layer away from the first substrate 110. In this case, the steps for forming the first circuit layer L1 may include: depositing a first conductive thin film on a first side 110A of the first substrate 110, and patterning the first conductive thin film to form a first conductive pattern layer; forming an insulating layer covering the first conductive pattern layer; depositing a second conductive thin film on the insulating layer, and patterning the second conductive thin film to form a second conductive pattern layer.

[0102] For example, a portion of the signal line 120 belongs to the first conductive pattern layer, and another portion belongs to the second conductive pattern layer. Based on this, during the formation of the first conductive pattern layer, the material of the first conductive film falls into the via 150 on the first substrate 110, thereby obtaining a line segment that is at least partially embedded in the via 150 after patterning.

[0103] For example, the entire signal line 120 belongs to the first conductive pattern layer; based on this, after the first conductive pattern layer is formed, the signal line 120 can be at least partially embedded in the via 150.

[0104] In this way, even if the second circuit layer L2 and the first circuit layer L1 are distributed on both sides of the first substrate 110, the first substrate 110 does not need to be flipped during the fabrication of the display panel 100.

[0105] Figure 5 for Figure 3 Another possible cross-sectional view at A1-A2.

[0106] See Figure 5In other embodiments, a portion of the fan-out line 140 is embedded in the via 150, contacting a portion of the signal line 120 exposed by the via 150. Similarly, the signal line 120 is located on a first side 110A of the first substrate 110, and the via 150 penetrates the first substrate 110. Viewed from the second substrate 130 toward the first circuit layer L1, a portion of the signal line 120 is exposed within the opening of the via 150. A portion of the fan-out line 140 is embedded in the via 150 and extends toward the first side 110A of the first substrate 110, contacting the portion of the signal line 120 exposed by the via 150, forming a coupling.

[0107] The fan-out line 140 can be a single-layer structure or a multi-layer structure. When the fan-out line 140 is a single-layer structure, the material of the fan-out line 140 can include metals, such as copper; when the fan-out line 140 is a multi-layer structure, the fan-out line 140 can be a metal stacked structure such as titanium / aluminum / titanium, molybdenum / aluminum / molybdenum, titanium / copper / titanium, etc.

[0108] For example, the second circuit layer L2 may include at least one (e.g., one, or more) conductive pattern layers. For instance, all fan-out lines 140 included in the second circuit layer L2 belong to the same conductive pattern layer. Alternatively, some fan-out lines 140 and others may belong to different conductive pattern layers. Furthermore, if a fan-out line 140 has a multilayer structure, then the conductive pattern layer to which that fan-out line 140 belongs may also have a multilayer structure.

[0109] See Figure 3 In the aforementioned display panel 100, since all the signal lines 120 coupled to the second circuit layer L2 are relatively dispersed, that is, the distance between adjacent signal lines 120 is relatively large; while the distance between two adjacent second pins 210 on the circuit board 200 is relatively small, the end of the multiple fan-out lines 140 connected to the signal lines 120 is relatively dispersed, while the end connected to the driver chip 500 is relatively clustered, so the overall distribution is fan-shaped.

[0110] In the related art, in the display panel 100, the signal line 120 and the fan-out line 140 coupled to the signal line 120 are located on the same side of a substrate, and the fan-out line 140 is located in the non-display area SA of the display panel 100, which increases the width of the bezel of the display panel 100. In order to reduce the width of the bezel of the display panel 100, the display panel 100 provides a bending area on the side of the fan-out line 140 away from the display area AA, by bending a portion of the fan-out line 140 to the back side of the substrate (non-display side 100B) to facilitate connection with the circuit board 200. However, in the display panel 100 provided in this embodiment, since the fan-out line 140 is coupled to the signal line 120 and is located on the side of the first substrate 110 away from the signal line 120, the connection between the fan-out line 140 and the circuit board 200 is more convenient. Therefore, the display panel 100 does not need to provide a bending area, the bezel width of the display panel 100 is reduced, and a narrower bezel can be achieved. Furthermore, it also reduces the flexibility requirements of the display panel 100 on the first substrate 110.

[0111] In some embodiments, at least one (e.g., one, or more) vias 150 on the first substrate 110 are located within the non-display area SA. For example, at least some (e.g., some, or all) of all the vias 150 used to couple the first circuit layer L1 and the second circuit layer L2 are located within the non-display area SA. In this way, the first circuit layer L1 of the display area AA is relatively flat, and the light-emitting device EL is disposed on the relatively flat first circuit layer L1, resulting in a stable structure and good display effect.

[0112] This application embodiment also provides a display module 10 including the above-described display panel 100.

[0113] Figure 6A A rear view of the wiring connections for the display module (viewed from the non-display side); Figure 6B for Figure 6A The cross-sectional view at B1-B2.

[0114] See Figure 6B The display module 10 also includes a circuit board 200. The circuit board 200 is disposed on the side of the second substrate 130 of the display panel 100 away from the first substrate 110. Figure 5 Below the second substrate 130, that is, on the opposite side of the side where the fan-out line 140 is located on the second substrate 130. And the circuit board 200 is coupled to the fan-out line 140 in the display panel 100.

[0115] Since the display module 10 includes the display panel 100 described above, it has the same beneficial effects, which will not be repeated here.

[0116] In order to couple the circuit board 200 with the fan-out line 140 in the display panel 100, in some embodiments, a first opening 160 is provided on the second substrate 130, the first opening 160 exposing at least a portion of the fan-out line 140, at which the circuit board 200 is coupled with the fan-out line 140.

[0117] To couple the circuit board 200 to the fan-out line 140 in the display panel 100, in some embodiments, at least one (e.g., one, or more) first opening 160 is provided on the second substrate 130. The first opening 160 exposes at least a portion of the fan-out line 140.

[0118] For example, there is one first opening 160. A relatively wide first opening 160 is formed on the side of the second substrate 130 away from the first substrate 110 by means of etching or the like. At least a portion of all fan-out lines 140 included in the second circuit layer L2 is located within the opening range of the first opening 160. The portion of the fan-out line 140 designed to couple with the circuit board 200 can be referred to as the first pin 141, that is, the first pins 141 of all fan-out lines 140 coupled to the circuit board 200 are exposed within the opening range of the first opening 160. (See the explanation above for this exposure).

[0119] For example, there are multiple first openings 160. Multiple narrow first openings 160 are formed on the side of the second substrate 130 away from the first substrate 110 by means of etching or other methods. The first pins 141 of all fan-out lines 140 contained in the second circuit layer L2 are exposed in a corresponding first opening 160.

[0120] The circuit board 200 is located on the side of the second substrate 130 away from the fan-out line 140. The second pin 210 of the circuit board 200 can be directly coupled to the first pin 141 of the fan-out line 140 through the first opening 160 or through other conductive medium, such as conductive film.

[0121] In the aforementioned display module 10, the first pin 141 of the fan-out line 140 is exposed in the first opening 160. Therefore, the first opening 160 has a certain positioning function. The circuit board 200 can align the first opening 160 with the first pin 141 of the fan-out line 140 for coupling. As a result, the manufacturing process of the aforementioned display module 10 is less difficult and the yield rate is higher.

[0122] See also Figure 6BTo increase the ease of coupling between the circuit board 200 and the fan-out line 140, and to enhance insulation performance, the display module 10 also includes at least one (e.g., one, or more) conductive adhesive film (which may be referred to as a third conductive adhesive film 190 to distinguish it from other conductive adhesive films described below), which is adhered between the circuit board 200 and the fan-out line 140. The circuit board 200 and the fan-out line 140 are coupled through the conductive adhesive film.

[0123] The third conductive film 190, such as anisotropic conductive film (ACF), mainly consists of two parts: a third adhesive (e.g., a resin-based third adhesive) and third conductive particles 192 dispersed within the third adhesive. The process of coupling the circuit board 200 and the fan-out line 140 is called bonding. After the third conductive film 190 is bonded between the circuit board 200 and the fan-out line 140, pressure and heat are applied to the third conductive film 190 from one side of the circuit board 200 using the bonding equipment's die head. The first pin 141 of the fan-out line 140 is more prominent than other parts (such as the first substrate 110 between the two first pins 141). Correspondingly, the second pin 210 of the circuit board 200 is more prominent than other parts of the circuit board 200. Therefore, the multiple third conductive particles 192 of the third conductive film 190 located between the first pin 141 of the fan-out line 140 and the second pin 210 of the circuit board 200 are subjected to greater compression. The multiple third conductive particles 192 are compressed together, causing the first pin 141 of the fan-out line 140 and the second pin 210 of the circuit board 200 to conduct and form a coupling. Therefore, the conduction direction of the third conductive film 190 is perpendicular to the plane where the third conductive film 190 is located (i.e., the third direction Z), and its resistance value in the conduction direction is significantly different from the resistance value of the plane where the third conductive film 190 is located. That is, the third conductive film 190 only conducts in the direction perpendicular to the plane where the third conductive film 190 is located. Furthermore, the third adhesive cures and fixes itself between the circuit board 200 and the fan-out line 140 after being heated. The third adhesive has functions such as moisture resistance, heat resistance, and insulation.

[0124] In some embodiments, the third adhesive is a low-temperature melting adhesive. For example, the heat distortion temperature of the third adhesive is <130°C, such as 130°C, 125°C, or 107°C. The low-temperature melting third adhesive can reduce the temperature used in the bonding process, thereby reducing the possibility of temperature damage to the display area AA during the bonding process.

[0125] The circuit board 200 and the fan-out line 140 are coupled through a third conductive adhesive film 190. The third conductive adhesive film 190 is attached between the circuit board 200 and the fan-out line 140, and the coupling is completed by heating and pressurizing. It is not necessary to align the second pin 210 on the circuit board 200 and the first pin 141 of the fan-out line 140 one by one before coupling, so the coupling efficiency is high. Moreover, the conduction direction characteristics of the third conductive adhesive film 190 can avoid short circuits between two adjacent first pins 141 or two second pins 210, so the stability and reliability of the display module 10 are high.

[0126] Figure 7 for Figure 6A Another possible cross-sectional view at B1-B2.

[0127] See Figure 7 In some embodiments, the display module 10 further includes an insulating protective layer L5. The insulating protective layer L5 covers the portion of the fan-out line 140 exposed by the first opening 160, i.e., covers the first pin 141 of the fan-out line 140. The insulating protective layer L5 is a layered structure made of insulating material. The insulating material may include materials such as PET (Polyethylene terephthalate), PEN (Polyethylene naphthalate dimethyl methacrylate), and PI (Polyimide). Since the insulating material has a certain degree of flexibility, the insulating protective layer L5 also has a certain degree of flexibility.

[0128] The first conductive adhesive film 170 is bonded between the circuit board 200 and the insulating protective layer L5, and is tightly adhered to the insulating protective layer L5. Multiple first conductive particles 172 are dispersed within the first conductive adhesive film 170. In addition to the first conductive particles 172, the first conductive adhesive film 170 also includes a first adhesive, with the first conductive particles 172 also dispersed within the first adhesive. The first adhesive can also be a low-temperature melting adhesive.

[0129] Figure 8 This is a schematic diagram of the structure of the first conductive particle 172.

[0130] See Figure 7 and Figure 8 A first conductive particle 172 has a plurality of first protrusions 173 on its surface. At least a portion of the first protrusions 173 of the first conductive particle 172 penetrates the insulating protective layer L5 and comes into contact with the portion of the fan-out line 140 exposed by the first opening 160.

[0131] The first protrusion 173 can be conical, spherical, cylindrical, or other shapes; the specific shape is not limited. The first protrusion 173 protrudes from the surface of the first conductive particle 172 and has a certain degree of penetration. The bonding process between the fan-out line 140 and the circuit board 200 can be as follows:

[0132] A conductive adhesive film is bonded between the circuit board 200 and the insulating protective layer L5. Pressure and heat are applied to the conductive adhesive film from one side of the circuit board 200. When the first conductive adhesive film 170 is subjected to pressure from the circuit board 200, the first protrusion 173 of the first conductive particles 172 near the insulating protective layer L5 can penetrate the first adhesive and then the insulating protective layer L5, thus contacting and coupling with the first pin 141 of the fan-out line 140. On the side near the circuit board 200, the first protrusion 173 of the first conductive particles 172 near the circuit board 200 can penetrate the first adhesive and contact and couple with the second pin 210 of the circuit board 200. Thus, a conductive connection is formed between the first pin 141 of the fan-out line 140 and the second pin 210 of the circuit board 200. The curing process of the first adhesive is not described in detail.

[0133] In the aforementioned display module 10, the insulating protective layer L5 covers the fan-out line 140, with only the portion corresponding to the first pin 141 being penetrated. This reduces the likelihood of short circuits between adjacent first pins 141, thereby improving the stability and reliability of the display module 10. Furthermore, the insulating protective layer L5 has a certain degree of flexibility, thus buffering the pressure transmitted by the first conductive adhesive film 170 to a certain extent, thereby providing some protection for the display area AA.

[0134] See Figure 7 and Figure 8 In some embodiments, the first protrusion 173 has a tip 174 at one end of its surface away from the first conductive particle 172. The tip 174 of the first protrusion 173 enhances its ability to penetrate the insulating protective layer L5. It can penetrate the insulating protective layer L5 even under relatively low pressure, thus reducing the pressure required for the bonding process and consequently reducing the likelihood of pressure damage to the display area AA, thereby protecting the display area AA. Furthermore, the thickness of the insulating protective layer L5 can be relatively thick, such as 3–5 μm. This further reduces the possibility of short circuits between adjacent first pins 141 while ensuring coupling between the first pin 141 of the fan-out line 140 and the second pin 210 of the circuit board 200, and enhances the protective performance of the insulating protective layer L5 for the display area AA.

[0135] Figure 9 for Figure 6A Another possible cross-sectional view at B1-B2.

[0136] See Figure 9To improve the coupling efficiency between the circuit board 200 and the fan-out line 140 in the display panel 100, in some embodiments, the second substrate 130 isolates the fan-out line 140 from the circuit board 200. The second substrate 130 does not have an opening in the portion corresponding to the first pin 141 of the fan-out line 140 (i.e., the portion covering the fan-out line 140), thus isolating the fan-out line 140 from the circuit board 200. Referring to the above description of the material of the second substrate 130, it can be seen that the material of the second substrate 130 is also an insulating material, and the second substrate 130 can also serve an insulating function.

[0137] The display module 10 also includes a second conductive adhesive film 180, which is bonded between the circuit board 200 and the second substrate 130. The second conductive adhesive film 180 contains a plurality of second conductive particles 182. Each second conductive particle 182 has a plurality of second protrusions 183 on its surface. At least a portion of the second protrusions 183 of the second conductive particles 182 penetrates the second substrate 130 and contacts the fan-out line 140. Similarly, the composition of the second conductive adhesive film 180 can be referenced to that of the first conductive adhesive film 170. The process of bonding the fan-out line 140 to the circuit board 200 via the second conductive adhesive film 180 is the same as the process of bonding the fan-out line 140 to the circuit board 200 via the first conductive adhesive film 170, except that the second protrusions 183 of the second conductive particles 182 penetrate the second substrate 130, which differs from the process of the first protrusions 173 of the first conductive particles 172 penetrating the insulating protective layer L5. Correspondingly, the structure of the second protrusion 183 of the second conductive particle 182 (such as the overall shape and the tip 174 structure) can refer to the structure of the second protrusion 183 of the second conductive particle 182.

[0138] In the aforementioned display module 10, the second substrate 130 covers the fan-out line 140, with only the portion corresponding to the first pin 141 being penetrated. This reduces the likelihood of short circuits between adjacent first pins 141, thereby improving the stability and reliability of the display module 10. Furthermore, the second substrate 130 can be a flexible substrate, thus buffering the pressure transmitted by the first conductive adhesive film 170 to a certain extent, providing some protection for the display area AA. In addition, the second substrate 130 does not have an opening at the portion corresponding to the first pin 141 of the fan-out line 140. The first pin 141 of the fan-out line 140 is coupled to the second pin 210 of the circuit board 200 via the second conductive adhesive film 180, eliminating the need for etching openings and thus improving bonding efficiency.

[0139] Figure 10 for Figure 6A Another possible cross-sectional view at B1-B2.

[0140] See Figure 10To facilitate penetration of the second substrate 130, in some embodiments, the second substrate 130 includes a first surface 130A and a second surface 130B opposite to each other, with the second surface 130B being farther away from the first substrate 110 than the first surface 130A. The second substrate 130 has a groove 131 on either the first surface 130A or the second surface 130B. The groove 131 of the second substrate 130 corresponds to the first pin 141 of the fan-out line 140, meaning that the orthographic projection of the first pin 141 of the fan-out line 140 onto the first substrate 110 is located within the orthographic projection range of the groove 131 of the second substrate 130 onto the first substrate 110 (the two overlap or the orthographic projection of the former is surrounded by the orthographic projection of the latter). When the groove 131 is provided on the second surface 130B, the groove 131 also has a certain positioning function, allowing the circuit board 200 to align the groove 131 with the first pin 141 of the fan-out line 140 for coupling. Therefore, the manufacturing process is less difficult and the yield rate is higher.

[0141] At the groove 131, at least a portion of the second protrusion 183 of the second conductive particle 182 penetrates the second substrate 130 and contacts the fan-out line 140. The second substrate 130 is relatively thin at the groove 131, such as 2-3 μm, so the second protrusion 183 of the second conductive particle 182 can penetrate the second substrate 130 more easily. In this way, the pressure used in the bonding process can also be reduced, thereby reducing the possibility of damage to the display area AA under pressure and protecting the display area AA.

[0142] See Figure 9 In other embodiments, the thickness of the second substrate 130 is less than the thickness of the first substrate 110. The second substrate 130 is generally thinner, for example, 2 to 3 μm thick, so that at least a portion of the second protrusions 183 of the second conductive particles 182 can penetrate the second substrate 130. The second substrate 130 does not require additional etching to form grooves 131 or openings, thus further improving bonding efficiency.

[0143] Figure 11 for Figure 6A Another possible cross-sectional view at B1-B2.

[0144] See Figure 11 In some embodiments, the display module 10 further includes a buffer 300. The buffer 300 may be made of high-temperature resistant foam. The buffer 300 is disposed between the second substrate 130 and the circuit board 200, and is located around the coupling position of the circuit board 200 and the fan-out line 140.

[0145] The coupling point between circuit board 200 and fan-out line 140 is the second pin 210 of circuit board 200. Buffer 300 is located around the second pin 210 of circuit board 200, partially or completely surrounding it. Taking the buffer 300 completely surrounding the second pin 210 as an example, this effectively adds a high-temperature resistant buffer ring around the second pin 210 of circuit board 200. Buffer 300 can absorb some of the heat and pressure generated by the bonding machine head, reducing its impact on areas outside the bonding area of ​​display panel 100 (such as display area AA), thereby further minimizing the impact of the bonding process on the display effect of display panel 100.

[0146] Figure 12 for Figure 6A Another possible cross-sectional view at B1-B2.

[0147] See Figure 12 In some embodiments, the encapsulation layer L4 can be three layers, including a first inorganic layer CVD1, a second inorganic layer CVD2, and an organic layer IJP disposed between them. The first inorganic layer CVD1 is closer to the light-emitting device layer L3 than the second inorganic layer CVD2. The first inorganic layer CVD1 and the second inorganic layer CVD2 can be formed by plasma chemical vapor deposition, and the organic layer IJP can be formed by inkjet printing.

[0148] See also Figure 12 In some embodiments, the display module 10 further includes at least one barrier dam Dam. The barrier dam Dam is located around the periphery of the encapsulation layer L4 and in the peripheral area SA. In some embodiments, the display module 10 includes a first barrier dam Dam1 and a second barrier dam Dam2. The first barrier dam Dam1 is closer to the display area AA than the second barrier dam Dam2.

[0149] Figure 13 This is a schematic diagram of the back of a splicing display device. Figure 14 for Figure 13 A front view of the splicing display device.

[0150] Some embodiments of this disclosure also provide a splicing display device (also known as a splicing screen), see [link to relevant documentation]. Figure 13 and Figure 14 This splicing display device includes multiple of the aforementioned display devices, which are spliced ​​together to achieve a near-borderless display screen. When multiple of the aforementioned display devices are present, "seamless multi-screen splicing" can be achieved, enabling the splicing screen to achieve a better visual effect than existing methods.

[0151] Figure 15 This is a flowchart of the method for manufacturing the display panel 100.

[0152] See Figure 15 Some embodiments of this disclosure provide a method for manufacturing a display panel 100, including:

[0153] Step S10: Form fan-out lines on the second substrate.

[0154] When the second substrate 130 is a flexible substrate (such as a PET substrate, PEN substrate, or PI substrate), the second substrate 130 can be formed on a rigid substrate, such as a glass substrate, a PMMA (Polymethyl methacrylate) substrate, a quartz substrate, or a metal substrate. Then, fan-out lines 140 are formed on the second substrate 130.

[0155] Step S20: A first substrate is formed on the side of the fan-out line away from the second substrate, and a via is formed on the first substrate.

[0156] Step S30: A signal line is formed on the side of the first substrate away from the second substrate; at the via, the signal line is coupled to the fan-out line.

[0157] Steps S20 and S30 can be found in the explanation of the structure of the display module 10, and will not be repeated here. The manufacturing method of the display panel 100 described above can achieve the same beneficial effects as the display panel 100 described above, and will not be repeated here.

[0158] After step S30 is completed, the second substrate 130 can be separated from the rigid substrate.

[0159] Figure 16 A flowchart illustrating the preparation method of module 10.

[0160] See Figure 16 Some embodiments of this disclosure provide a method for preparing a display module 10, which, in addition to steps S10 to S30, further includes:

[0161] Step S40: Bond the second substrate to the circuit board on the side away from the fan-out line.

[0162] Figure 17 The process diagram for setting up the temporary protective film 400. Figure 18 The process diagram for penetrating the temporary protective film 400.

[0163] See Figure 17 To provide temporary protection for the display panel 100 during bonding, a temporary protective film 400 can be provided on the side of the second substrate 130 away from the fan-out line 140 to prevent damage to the display panel 100 from the bonding equipment head or other components. See also Figure 18The temporary protective film 400 is relatively thin, making it easily penetrated by conductive particles during the bonding process without affecting the conductivity between the display panel 100 and the circuit board 200. The temporary protective film 400 can be made of PET. For specific bonding processes, please refer to the above description and will not be repeated here. Figure 10 Once the bonding process is complete, the temporary protective film 400 can be removed.

[0164] The manufacturing method of the display module 10 described above can achieve the same beneficial effects as the display panel 100 described above, and will not be repeated here. The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: A first substrate has a first side and a second side that are opposite each other in the thickness direction of the first substrate; The signal line is disposed on the first side of the first substrate; The second substrate is disposed on the second side of the first substrate; A fan-out line is disposed between the first substrate and the second substrate; Wherein, a via is formed on the first substrate, and the signal line is coupled to the fan-out line at the via; The second substrate has a first opening that exposes at least a portion of the fan-out line. The first opening is configured to embed a portion of the circuit board to achieve the connection between the fan-out line and the circuit board. Alternatively, the second substrate has a groove that corresponds to at least a portion of the fan-out line. The groove is configured to embed a portion of the circuit board to achieve the connection between the fan-out line and the circuit board. The second substrate is configured to carry the fan-out line, which is close to the surface of the first substrate and higher than the surface of the second substrate close to the first substrate.

2. The display panel according to claim 1, characterized in that, A portion of the signal line is embedded in the via and contacts a portion of the fan-out line exposed by the via.

3. The display panel according to any one of claims 1 to 2, characterized in that, The display panel has a display area and a non-display area located around the display area; the via is located within the non-display area.

4. A display module, characterized in that, include: The display panel according to any one of claims 1 to 3; as well as A circuit board is disposed on the side of the second substrate of the display panel away from the first substrate and is coupled to the fan-out line in the display panel.

5. The display module according to claim 4, characterized in that, The second substrate has a first opening, which exposes at least a portion of the fan-out line; At the first opening, the circuit board is coupled to the fan-out line.

6. The display module according to claim 5, characterized in that, Also includes: An insulating protective layer covering the portion of the fan-out line exposed by the first opening; and A first conductive adhesive film is bonded between the circuit board and the insulating protective layer. A plurality of first conductive particles are dispersed in the first conductive adhesive film. Each first conductive particle has a plurality of first protrusions on its surface. At least a portion of the first protrusions of the first conductive particles penetrate the insulating protective layer and contact the portion of the fan-out line exposed by the first opening.

7. The display module according to claim 6, characterized in that, The first protrusion has a pointed end at one end of the surface away from the first conductive particle.

8. The display module according to claim 4, characterized in that, The second substrate has a groove, which corresponds to at least a portion of the fan-out line; The display module also includes: A second conductive adhesive film is bonded between the circuit board and the second substrate; a plurality of second conductive particles are dispersed in the second conductive adhesive film, and a plurality of second protrusions are provided on the surface of the second conductive particles; The second substrate includes opposing first and second surfaces, the second surface being farther away from the first substrate than the first surface; the second substrate has a groove on the first surface or the second surface; at the groove, at least a portion of the second protrusion of the second conductive particle penetrates the second substrate and contacts the fan-out line.

9. The display module according to claim 4, characterized in that, Also includes: A buffer is disposed between the second substrate and the circuit board, and is located around the coupling position of the circuit board and the fan-out line.

10. A display device, characterized in that, include: The display module according to any one of claims 4 to 9.

11. A method for manufacturing a display panel, characterized in that, include: Fan-out lines are formed on the second substrate; The second substrate is configured to carry the fan-out line; A first substrate is formed on the side of the fan-out line away from the second substrate, and a via is formed on the first substrate; the fan-out line is close to the surface of the first substrate and higher than the surface of the second substrate close to the first substrate; A signal line is formed on the side of the first substrate away from the second substrate; At the via, the signal line is coupled to the fan-out line; A first opening is formed on the second substrate, the first opening exposing at least a portion of the fan-out line, the first opening being configured to embed a portion of a circuit board to achieve connection between the fan-out line and the circuit board; or, a groove is formed on the second substrate, the groove corresponding to at least a portion of the fan-out line, the groove being configured to embed a portion of a circuit board to achieve connection between the fan-out line and the circuit board.

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