Linked List Processing Method, Apparatus, Accelerator, Circuit Board, Device, and Storage Medium

Abstract

The present application provides a linked list processing method, apparatus, accelerator, circuit board, device, and storage medium. The method includes: receiving multiple linked list read requests from a host into a preset command submission queue, where the command submission queue is configured with a preset number of accommodation spaces for caching the multiple linked list read requests; according to the reception order of each linked list read request, sequentially reading the linked list data corresponding to each linked list read request from a memory and sequentially executing the multiple pieces of linked list data, where the linked list data includes at least one command list; after one piece of linked list data is executed, releasing the corresponding accommodation space of the executed linked list data in the command submission queue to receive the next linked list read request from the host. The present application reduces the interaction power consumption between the CPU and the computing accelerator, and the command prefetch module saves chip resources by sharing the command list memory.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a linked list processing method, apparatus, accelerator, circuit board, device, and storage medium. Background Art

[0002] A Graphics Processing Unit (GPU), also known as a display core, visual processor, or display chip, is a microprocessor specifically designed to perform image and graphics-related operations on personal computers, workstations, game consoles, and some mobile devices (such as tablets, smartphones, etc.). In recent years, with the development of deep learning technologies, GPUs and artificial intelligence dedicated acceleration chips have been widely used. A GPU or an artificial intelligence acceleration chip usually serves as a computing accelerator for the host CPU (Central Processing Unit). The host CPU generates commands and allocates resources, and together with the CPU, completes data processing tasks. Generally, the CPU is located on the motherboard, while the computing accelerator is on a separate circuit board, and the two are connected through a PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) bus. This separated design poses many challenges to the computing system, such as the need for efficient communication between the CPU and the computing accelerator, and the need for efficient data exchange between separated memories.

[0003] Commands sent by the host CPU to the computing accelerator are usually stored in a memory in the form of a command list. This memory may be a host-side memory or an accelerator-side memory. Each command list is usually designed as a circular buffer structure. The circular buffer structure manages the command list through write and read pointers: when software on the host CPU side adds a command, the write pointer is updated. After the computing accelerator reads a command, the read pointer is updated. The computing accelerator needs to check the write pointer of the circular structure to determine whether a new command has been generated, and the software on the host side needs to check the read pointer of the circular structure to determine whether new commands can continue to be added to the command storage. Moreover, the host can only submit one command list to the computing accelerator at a time. It has to wait until the computing accelerator notifies the host that the previous command list has been read before the host can continue to submit the next command list, which easily causes an ineffective waiting gap for the computing accelerator and low efficiency. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a linked list processing method, apparatus, accelerator, circuit board, device, and storage medium. By using a multi-linked list structure to manage command lists, the interaction frequency between the CPU and the computing accelerator can be reduced, the memory access power consumption can be reduced, the ineffective waiting time of the computing accelerator can be reduced, the data interaction gap between the host and the computing accelerator can be reduced, and the system performance can be improved.

[0005] By pre-checking whether the last entry is a link command, the read latency of the new command list can be reduced, achieving the saving of chip resources without the need to add additional caches.

[0006] In a first aspect of the embodiments of the present application, a command linked list processing method is provided, including: receiving multiple linked list read requests from a host into a preset command submission queue, where the command submission queue is configured with a preset number of accommodation spaces for caching the multiple linked list read requests; according to the reception order of each linked list read request, sequentially reading the linked list data corresponding to each linked list read request from a memory and sequentially executing the multiple linked list data, where the linked list data includes at least one command list; after one linked list data is executed, releasing the corresponding accommodation space of the executed linked list data in the command submission queue to receive the next linked list read request from the host.

[0007] In one embodiment, the receiving multiple linked list read requests from a host into a preset command submission queue includes: when detecting one linked list read request from the host, if the number of existing linked list read requests in the command submission queue is less than the preset number, receiving the current linked list read request into the command submission queue.

[0008] In one embodiment, the sequentially reading the linked list data corresponding to each linked list read request from a memory according to the reception order of each linked list read request includes:

[0009] For each linked list read request, when detecting the command read request of the command submission queue, obtaining the command list to be processed from the specified memory according to the command read request, where the command list includes multiple entries, and each entry stores a command to be processed; checking whether the last entry stored in the command list is a link command; if the last entry stored in the command list is a link command, obtaining a new command list from the specified memory according to the link command.

[0010] In one embodiment, when a command read request of the command submission queue is detected, obtaining a list of commands to be processed from a specified memory according to the command read request includes: when a command read request of the command submission queue is detected, in response to the command read request, parsing the storage address and length information of the list of commands to be processed from the command submission queue; according to the storage address and the length information, sending an access request to a specified memory, and caching the command list data returned by the memory in a preset cache, and updating the write pointer of the preset cache.

[0011] In one embodiment, according to the storage address and the length information, sending an access request to a specified memory, and caching the command list data returned by the memory in a preset cache includes: according to the length information, allocating corresponding storage space from the preset cache for the command read request, sending an access request to a specified memory according to the storage address, and caching the command list data returned by the memory in the allocated storage space.

[0012] In one embodiment, checking whether the last entry stored in the command list is a link command includes: when the write pointer of the preset cache is different from the first read pointer of the preset cache, checking each entry of the command list in the preset cache until the last entry of the command list is found, and determining whether the command stored in the last entry of the command list is a link command.

[0013] In one embodiment, checking whether the last entry stored in the command list is a link command includes: when the write pointer of the preset cache is different from the first read pointer of the preset cache, reading the command list in the preset cache, calculating the position of the last entry of the command list according to the length information of the command list, and determining whether the command at the position of the last entry is a link command.

[0014] In one embodiment, sequentially executing a plurality of the linked list data includes: for each of the linked list data, when the write pointer of the preset cache is different from the second read pointer of the preset cache, decoding the commands to be processed in the preset cache, and executing the decoded commands to be processed, and releasing the corresponding resources of the commands to be processed in the preset cache.

[0015] In one embodiment, after the execution of one piece of linked list data is completed, releasing the corresponding accommodation space of the executed linked list data in the command submission queue includes: for each piece of linked list data, when the to-be-processed command decoded is an end command, after all commands in the current linked list data are executed, releasing the corresponding accommodation space of the corresponding linked list read request in the command submission queue.

[0016] In a second aspect of the embodiments of the present application, a command linked list processing device is provided, including: a receiving module, configured to receive multiple linked list read requests from a host into a preset command submission queue, where the command submission queue is configured with a preset number of accommodation spaces for caching the multiple linked list read requests; a first processing module, configured to sequentially read the linked list data corresponding to each linked list read request from a memory according to the receiving order of each linked list read request, and sequentially execute the multiple pieces of linked list data, where the linked list data includes: at least one command list; a second processing module, configured to, after the execution of one piece of linked list data is completed, release the corresponding accommodation space of the executed linked list data in the command submission queue to receive the next linked list read request from the host.

[0017] In one embodiment, the receiving module is configured to: when detecting one linked list read request from a host, if the number of existing linked list read requests in the command submission queue is less than the preset number, receive the current linked list read request into the command submission queue.

[0018] In one embodiment, the first processing module is configured to: for each linked list read request, when detecting a command read request in the command submission queue, obtain a to-be-processed command list from a specified memory according to the command read request, where the command list is in a linked list structure, the command list includes multiple entries, and each entry stores a to-be-processed command; check whether the last entry stored in the command list is a link command; if the last entry stored in the command list is a link command, obtain a new command list from the specified memory according to the link command.

[0019] In one embodiment, the first processing module is further configured to: when detecting a command read request in the command submission queue, in response to the command read request, parse the storage address and length information of the to-be-processed command list from the command submission queue; according to the storage address and the length information, send an access request to a specified memory, cache the command list data returned by the memory into a preset cache, and update the write pointer of the preset cache.

[0020] In one embodiment, the first processing module is further configured to: allocate a corresponding storage space for the command read request from the preset cache according to the length information, send an access request to a specified memory according to the storage address, and cache the command list data returned by the memory in the allocated storage space.

[0021] In one embodiment, the first processing module is further configured to: when the write pointer of the preset cache is different from the first read pointer of the preset cache, check each entry of the command list in the preset cache until the last entry of the command list is found, and determine whether the command stored in the last entry of the command list is a link command.

[0022] In one embodiment, the first processing module is further configured to: when the write pointer of the preset cache is different from the first read pointer of the preset cache, read the command list in the preset cache, calculate the position of the last entry of the command list according to the length information of the command list, and determine whether the command at the position of the last entry is a link command.

[0023] In one embodiment, the first processing module is further configured to: for each of the linked list data, when the write pointer of the preset cache is different from the second read pointer of the preset cache, decode the pending command in the preset cache, execute the decoded pending command, and release the corresponding resources of the pending command in the preset cache.

[0024] In one embodiment, the second processing module is configured to: for each of the linked list data, when the decoded pending command is an end command, after all the commands in the current linked list data are executed, release the corresponding accommodation space of the linked list read request in the command submission queue.

[0025] A third aspect of the embodiments of the present application provides a computing accelerator, including: a command submission queue for receiving a plurality of linked list read requests from a host, wherein the command submission queue is configured with a preset number of accommodation spaces for caching the plurality of linked list read requests; a command reading module for, when detecting a command read request from the command submission queue, obtaining a command list to be processed from a specified memory according to the command read request, wherein the command list includes a plurality of entries, and each entry stores an instruction to be processed; a command caching module configured with a write pointer for caching the command list data returned by the memory and updating the write pointer of the command caching module; a command pre-parsing module configured with a first read pointer for the command caching module, for, when the first read pointer is different from the write pointer, reading the command list data from the command caching module, checking whether the last entry stored in the command list is a link command, and for, if the last entry stored in the command list is a link command, notifying the command reading module to obtain a new command list from the specified memory according to the link command.

[0026] In one embodiment, it further includes: a command decoding module configured with a second read pointer for the command caching module, for, when the second read pointer is different from the write pointer, reading the command list data from the command caching module and decoding the command list to obtain the commands to be processed stored in each entry of the command list; an execution module for executing the commands to be processed.

[0027] A fourth aspect of the embodiments of the present application provides a circuit board, on which is deployed: the computing accelerator according to the third aspect of the embodiments of the present application and any one of its embodiments.

[0028] A fifth aspect of the embodiments of the present application provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the method according to the first aspect of the embodiments of the present application and any one of its embodiments.

[0029] A sixth aspect of the embodiments of the present application provides a non-transitory computer-readable storage medium for an electronic device, including: a program, which, when run by the electronic device, causes the electronic device to execute the method according to the first aspect of the embodiments of the present application and any one of its embodiments.

[0030] The linked list processing method, apparatus, accelerator, circuit board, device, and storage medium provided by this application manage multiple linked list read requests from the host by configuring the accommodation space of the command submission queue, and then sequentially read the linked list data corresponding to each linked list read request from the memory and execute it. When a linked list data is executed, the occupied resources of the linked list read request corresponding to the linked list data in the command submission queue will be released, so as to receive the next linked list read request from the host. In this way, as long as there is free accommodation space in the command submission queue, the host can submit linked list read requests, and the computing accelerator will continue to execute other linked list read requests in the command submission queue in sequence, realizing the ping-pong processing of multiple linked list read requests, reducing the waiting gap after a linked list is processed, and improving the utilization rate of system resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the following will briefly introduce the drawings required to be used in the embodiments of this application. It should be understood that the following drawings only show some embodiments of this application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0032] Figure 1 Schematic diagram of an electronic device according to an embodiment of this application;

[0033] Figure 2A Schematic diagram of a data exchange system according to an embodiment of this application;

[0034] Figure 2B Schematic diagram of the structure of a command list according to an embodiment of this application;

[0035] Figure 2C Schematic diagram of the structure of a computing accelerator according to an embodiment of this application;

[0036] Figure 3 Schematic diagram of the flowchart of the command linked list processing method according to an embodiment of this application;

[0037] Figure 4 Schematic diagram of the flowchart of the command linked list processing method according to an embodiment of this application;

[0038] Figure 5 Schematic diagram of the flowchart of the command linked list processing method according to an embodiment of this application;

[0039] Figure 6 Schematic diagram of a command linked list processing apparatus according to an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In the description of the present application, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0041] To clearly describe the solution of this embodiment, the nouns involved are defined as follows:

[0042] CPU: Central Processing Unit, the central processing unit, which is the operation and control core of a computer system and the execution unit of software programs.

[0043] GPU: Graphics Processing Unit, a graphics processing unit, a microprocessor that specializes in performing image and graphics-related operations on personal computers, workstations, game consoles, and some mobile devices (such as tablets, smartphones, etc.), and can be used as a computing accelerator for the CPU.

[0044] As Figure 1 shown, this embodiment provides an electronic device 100, including: at least one processor 110 and a memory 120. Figure 1 Taking one processor as an example. The processor 110 and the memory 120 are connected through a bus 10. The memory 120 stores instructions executable by the processor 110. The instructions are executed by the processor 110 so that the electronic device 100 can execute all or part of the processes of the methods in the following embodiments, thereby reducing the interaction frequency between the CPU and the computing accelerator, reducing power consumption, and reducing the read latency of the command list, and improving data processing efficiency.

[0045] In one embodiment, the electronic device 100 may be a mobile phone, a tablet computer, a laptop computer, a desktop computer, or a large computing system composed of multiple computers.

[0046] As Figure 2A shown, it is a schematic diagram of a data exchange system 200 provided by an embodiment of the present application, including a host 20 and a computing accelerator 30. Among them, commands are generated by the CPU of the host 20 and resources are allocated to the computing accelerator 30. The computing accelerator 30 and the CPU of the host 20 together complete data processing tasks. The computing accelerator 30 may be a GPU processor. In an actual scenario, the CPU of the host 20 may be located on the motherboard, while the computing accelerator 30 may be on a separate circuit board, and the two can be connected through a PCIe bus. This separated design poses many challenges to the computing system, such as the need for efficient communication between the CPU and the computing accelerator 30, and the need for efficient data exchange between the separated memories. To reduce the invalid memory access during the data interaction between the two and improve the data interaction efficiency, this embodiment provides a command list management scheme.

[0047] As shown Figure 2B in the figure, it is a schematic structural diagram of a command list provided by an embodiment of the present application. The command list of this embodiment adopts a linked list structure: that is, a linked list can include multiple command lists, and these command lists are connected in series through link commands. Figure 2B It shows a linked list containing 3 command lists (taking command list 0, command list 1, and command list 3 as examples). Each command list can include multiple entries, and each entry of the command list stores several commands that the computing accelerator 30 needs to execute. For example, the first entry in command list 0 stores the command 0 to be processed, and the second entry stores the command 1 to be processed. The last entry of each command list is either a link command or an end command.

[0048] For example Figure 2B in it, the last entry of command list 0 stores the link command pointing to command list 1, the last entry of command list 1 stores the link command pointing to command list 2, and the last entry of command list 3 stores the end command.

[0049] Link command: When there is a new command list that needs to be appended at the host 20 side, the link command can be used to indicate the address and length of the next command list in the memory. When the computing accelerator 30 parses the link command, it will read the new command list from the memory according to this link command, and then continue to parse and execute the new command list.

[0050] End command: When there is no new command list generated at the host 20 side, the last entry of the last command list in the linked list will be set as the end command. When the computing accelerator 30 parses the end command and all the command lists in the current linked list have been executed, it can enter the sleep state.

[0051] Adopting the linked list structure can avoid the frequent interaction of the storage pointers of the command lists between the host 20 CPU and the computing accelerator 30. Moreover, the host 20 CPU software does not need to allocate a large and continuous storage resource for the command list. A large command list can be composed of some small and scattered command lists, thereby saving resources and reducing energy consumption.

[0052] In the interaction process between the host 20 and the computing accelerator 30 in this embodiment, a management method of multiple linked lists can be adopted, and each linked list is independent of each other. When a new computing task is generated, the CPU of the host 20 will create a new linked list in the memory and notify the computing accelerator 30 of the generation of a new linked list by writing to a register. If the computing accelerator 30 is in a sleep state, it will start the execution of the new linked list. If the computing accelerator 30 is in a working state, it can save the address of the new linked list in the memory (for example, it can be the head address), and will execute them in the submission order of the linked list. This method is simple to implement and has high real-time performance.

[0053] In one embodiment, the last entry of the linked list can also be set as a wait command instead of an end command. This requires the computing accelerator 30 to repeatedly read the memory and check whether this entry has been updated by the CPU of the host 20 to a link command, so as to determine whether a new command list is generated.

[0054] Based on the command list of the linked list structure, during the reading process, only when the computing accelerator 30 parses the last entry of the command list can it know the storage address of the next command list. At this time, when a request to read the command list is issued, it will cause a gap in the execution of the command by the computing accelerator 30 in the actual scenario, thus wasting hardware computing resources. To avoid this problem, this embodiment also provides a computing accelerator 30 for prefetching the command list of the linked list structure.

[0055] As Figure 2C shown, a computing accelerator 30 provided by an embodiment of the present application includes: a command reading module 31, a command submission queue 32, a command cache module 33, a command pre-parser module 34, a command decoding module 35, and an execution module 36. Each module in the computing accelerator 30 is directly or indirectly connected. Among them:

[0056] The command submission queue 32 is used to receive multiple linked list read requests from the host. Among them, the command submission queue 32 is configured with a preset number of accommodation spaces, and the preset number of accommodation spaces is used to cache multiple linked list read requests. Optionally, one accommodation space is used to cache one linked list read request. The control information of multiple linked lists submitted by the CPU of the host 20 can be stored through the command submission queue 32. The command reading module 31 is used to obtain the command list to be processed from the specified memory according to the command read request when detecting a command read request from the command submission queue 32. The command list can be a linked list structure as Figure 2B shown. The command list includes multiple entries, and each entry stores a command to be processed. For a detailed description, see Figure 2A the corresponding description.

[0057] The command cache module 33 is configured with a write pointer for caching command list data returned by the memory and updating the write pointer of the command cache module 33. When the memory returns command data to the command cache module 33, the write pointer of the command cache module 33 is updated. When the write pointer differs from the command pre-parser module 34's first read pointer for the command cache module 33, the command pre-parser module 34 is notified that a new command is available for pre-decoding. When the write pointer differs from the command decoding module 35's second read pointer, the command decoding module 35 is notified that a new command is available for decoding in the command cache.

[0058] The command pre-parsing module 34 is configured with a first read pointer for the command cache module 33. When the first read pointer differs from the write pointer, the command pre-parsing module 34 reads the command list data from the command cache module 33. It also checks whether the last entry in the command list stores a link command. If it is determined that the last entry in the command list stores a link command, the command pre-parsing module 34 notifies the command reading module 31 to retrieve a new command list from a designated memory based on the link command. After reading each entry from the command cache module 33, the command pre-parsing module 34 does not release the corresponding entry's cache space; instead, it updates its first read pointer.

[0059] The command decoding module 35 is configured with a second read pointer for the command buffer module 33. When the second read pointer differs from the write pointer, it reads the command list data from the command buffer module 33 and decodes the command list to obtain the pending command stored in each entry in the command list. The pending command is then sent to the execution modules 36 of the computing accelerator 30. The execution modules 36 are configured to execute the pending command.

[0060] The command decoding module 35 releases the cache space for the corresponding command entry only after it reads the command list entry in the command cache module 33. This allows the command pre-parsing module 34 and the command decoding module 35 to share a cache unit, eliminating the need for an additional cache to store pre-decoded commands and saving chip area.

[0061] In one embodiment, the computing accelerator 30 may further include: a selector 37 for arbitrating the read pointers of the command decoding module 35 and the command pre-parsing module 34. The operation processes of the command decoding module 35 and the command pre-parsing module 34 do not interfere with each other. When it comes to actual application scenarios, the arbitration method of the read pointers of the two can be selected according to the actual scenario requirements. Usually, the speed of the command decoding module 35 in processing commands is slower than that of the pre-parsing module 34. Therefore, in order to ensure that the commands are normally decoded and executed, the arbitration rule can be set that the priority of the command decoding module 35 is higher than that of the pre-parsing module 34. Assuming that the command decoding module 35 executes relatively fast, a scheme with equal priorities of the two can be adopted. In this way, the computing accelerator 30 can be applied to different scenarios, adding flexibility to the scheme.

[0062] The above computing accelerator 30 configures a prefetch hardware structure including a double-pointer command cache module 33 for the command list in the linked list structure, so that the command pre-parsing module 34 and the command decoding module can share the command cache module 33, saving the chip area. The computing accelerator 30 can be implemented by programmable circuits or by non-programmable circuit modules. In this embodiment, it is preferably implemented by non-programmable circuit modules to achieve higher efficiency.

[0063] In one application scenario, the computing accelerator 30 provided by the embodiments of the present application can be a component of an independent electronic device 100 (which can be, but is not limited to, the GPU processor of the device). In another application scenario, the computing accelerator 30 can also be in the form of an independent device or apparatus. For example, an electronic device 100 is used as the computing accelerator 30 in the data exchange system 200 to execute the method provided by the embodiments of the present application.

[0064] The embodiments of the present application also provide a circuit board on which the following is deployed: as Figure 2C shown in the computing accelerator 30, so it has all the beneficial effects of the computing accelerator 30 and will not be elaborated here. The circuit board can deploy a chip structure and a circuit structure containing Figure 2C the computing accelerator 30 shown.

[0065] The command linked list processing method of the embodiments of the present application will be further described in detail below with reference to the drawings and text.

[0066] Please refer to Figure 3 , which is the command linked list processing method 300 of an embodiment of the present application. This method can be executed by the computing accelerator 30 provided by the embodiments of the present application or by the electronic device 100. In some application scenarios, this method can be executed by Figure 1 the electronic device 100 shown as the computing accelerator 30 and can be applied to the above Figures 2A - 2CIn the data interaction scenario, the interaction frequency between the CPU and the computing accelerator 30 is reduced, the power consumption is reduced, and the read latency between multiple linked lists is reduced, thereby improving the data processing efficiency. As Figure 3 shown, the method includes:

[0067] Step 301: Receive multiple linked list read requests from the host into a preset command submission queue 32.

[0068] In this step, when there is a data processing task between the host 20 and the computing accelerator 30, the software on the CPU side of the host 20 can notify the computing accelerator 30 that there is a new command linked list to be executed by writing to a register. The notification information mainly includes the address and length of the linked list in the specified memory, and this information will be stored in the command submission queue 32 of the computing accelerator 30. The command submission queue 32 is configured with a preset number of storage spaces, and the preset number of storage spaces is used to cache multiple linked list read requests. Optionally, one storage space can be used to cache one linked list read request. The host 20 can submit multiple linked lists. The host 20 can pre-agree with the accelerator on the number of linked lists that the command submission queue 32 can carry. For example, the preset number can be 5. Then when the host 20 has a computing task, it submits a linked list read request. If there is another task, it can continue to submit a linked list read request. Two adjacent linked list read requests can be non-consecutive or consecutive in time. Until there are 5 linked list read requests in the command submission queue 32, the computing accelerator 30 stops receiving linked list read requests from the host 20.

[0069] In one embodiment, step 301 may specifically include: when detecting a linked list read request from the host 20, if the number of existing linked list read requests in the command submission queue 32 is less than the preset number, then receive the current linked list read request into the command submission queue 32. Otherwise, it means that the command submission queue 32 is full, and the computing accelerator 30 stops receiving linked list read requests from the host 20 to avoid data blockage. The preset number can be set based on actual requirements.

[0070] Step 302: According to the reception order of each linked list read request, sequentially read the linked list data corresponding to each linked list read request from the memory, and sequentially execute multiple linked list data.

[0071] In this step, there can be multiple linked list read requests in the command submission queue 32. Each linked list data includes: at least one Figure 2B as shown command list. It can be understood that Figure 2B the structure shown is only for illustration. The computing accelerator 30 can process these linked list read requests submitted by the host 20 in sequence to make the data interaction process proceed orderly.

[0072] Step 303: After a linked list data is executed, release the corresponding accommodation space of the executed linked list data in the command submission queue 32 to receive the next linked list read request from the host 20.

[0073] In this step, after a linked list data is executed, in order to save the cache resources of the command submission queue 32, the occupied accommodation space of the linked list read request corresponding to the linked list data will be released, so as to vacate a position for the subsequent host 20 to submit a linked list read request, improving resource utilization.

[0074] Among them, after releasing the corresponding accommodation space of the executed linked list data in the command submission queue 32 in step S303, step S304 can be executed.

[0075] Step 304: Send a notification message to the host 20.

[0076] In this step, the host 20 can be notified by sending an interrupt, so that the host 20 can continue to submit the next linked list read request according to the notification message. In this way, as long as there is free accommodation space in the command submission queue 32, the host 20 can submit a linked list read request, while the computing accelerator 30 continues to execute other linked list read requests in the command submission queue 32 in order, realizing the ping-pong processing of multiple linked list read requests, reducing the waiting gap after a linked list is processed, and improving the system resource utilization. By providing the command linked list processing method in the embodiments of the present application, the processing efficiency of the computing accelerator and the host processor for jointly processing tasks can be improved, the overall memory access power consumption can be reduced, the reading latency of multiple command lists and multiple command linked lists when the computing accelerator cooperates with the host processor to process tasks can be reduced, the data interaction gap can be reduced, and the overall system processing efficiency can be improved.

[0077] Please refer to Figure 4 , which is the command linked list processing method 400 according to an embodiment of the present application. This method can be executed by the computing accelerator 30 provided in the embodiments of the present application, or can be executed by the electronic device 100. In some application scenarios, this method can be executed by Figure 1 the electronic device 100 shown as the computing accelerator 30, and can be applied to the data interaction scenario in the above Figures 2A - 2C to reduce the interaction frequency between the CPU and the computing accelerator 30, reduce the power consumption, and reduce the reading latency between multiple linked lists, improving the data processing efficiency. As Figure 4 shown, this method includes the following steps:

[0078] Step 401: Receive multiple linked list read requests from the host into the preset command submission queue 32. For details, please refer to the description of step 301 in the above embodiments.

[0079] Step 402: For each linked list read request, when a command read request from the command submission queue 32 is detected, obtain the command list to be processed from the specified memory according to the command read request.

[0080] In this step, the command list is in a linked list structure. The command list includes multiple entries, and each entry stores a command to be processed. For the specific structure, refer to the corresponding description above. Figure 2B The command read request can be issued by the command submission queue 32. When the command reading module 31 of the computing accelerator 30 receives the command read request, if there is no command list being executed currently, it responds to the read request, obtains the command list data to be processed from the specified memory, caches the command list data returned by the memory into a preset cache, and updates the write pointer of the preset cache. Here, the preset cache can be implemented by the Figure 2C command cache module 33 in.

[0081] Step 403: Check whether the last entry stored in the command list is a link command. If so, proceed to Step 404.

[0082] In this step, during the process of reading the command list, only when the computing accelerator 30 parses the last entry of the command list can it know the storage address of the next command list. At this time, if a request to read the command list is issued again, it will cause a gap in the execution of commands by the computing accelerator 30 in the actual scenario. To avoid the above-mentioned gap in command execution, the commands in the command list can be checked one by one in advance to check whether the last entry of the current command list is a link command. If it is, proceed to Step 404, and the new command list or command entry can be checked continuously. This check step can be executed by the command pre-parsing module 34 of the computing accelerator 30. Since only the entries of the command list are checked and no actual decoding process is performed, this step is faster than the actual command decoding process.

[0083] In one embodiment, step 403 may specifically include: when the write pointer of the preset cache is different from the first read pointer, check each entry of the command list in the preset cache until the last entry of the command list is found, and determine whether the last entry of the command list stores a link command. The command types of multiple entries in the command list in the preset cache can be scanned, and based on the scanning result, it is determined whether the last entry is a link command. When the checked entry is an end command, it indicates that all command lists of the linked list have been read. The computing accelerator 30 calculates an interrupt indicating that the linked list reading is complete and sends it to the host 20 CPU, notifying the host 20 CPU to release the storage resources of the linked list. It should be noted that since checking the type of the last entry does not mean decoding and executing the command content of the last entry, the content in the preset cache that has been checked but not yet truly decoded and executed in the linked list can continue to be retained. When the command corresponding to the parsed entry is neither a link command nor an end command, it can be directly skipped, and only the first read pointer of the command cache module 33 by the command pre-parsing module 34 is updated.

[0084] Step 404: Obtain a new command list from the specified memory according to the link command.

[0085] In this step, if the last entry of the command list stores a link command, it indicates that there is still a new command list to be read in the current linked list. Then, a new command list can be obtained from the specified memory according to the information in the link command. This process is not interfered by the decoding process, and it is not necessary to wait until the entries in the command list are completely decoded before reading the new command list. In this way, the gap in the execution of commands by the computing accelerator 30 as described above is avoided, the reading delay of the command list is reduced, and the command interaction efficiency is improved.

[0086] Step 405: For each linked list data, when the write pointer of the preset cache is different from the second read pointer of the preset cache, decode the pending commands in the preset cache and execute the decoded pending commands, and release the corresponding resources of the pending commands in the preset cache. [[ID=|10]]

[0087] In this step, for a linked list data being processed, when the write pointer of the preset cache is different from the second read pointer of the preset cache, it indicates that there is a new pending command list or a new command entry in the preset cache that has not been decoded. The computing accelerator 30 decodes each entry in the cached command list and executes the obtained pending commands one by one. For the pending commands that have been executed, their corresponding resources in the preset cache can be released. When the parsed entry is a link command, it will be directly skipped because this command has been processed in steps 403 and 404. When the parsed entry is a pending command that needs to be executed by a functional module, it will be sent to the corresponding execution module 36 in the computing accelerator 30 for execution. This step can be performed by the aboveFigure 2C It is executed by the command decoding module 35 of the computing accelerator 30 in the middle.

[0088] It should be noted that step 405 and steps 403 - 404 can be independent of each other. When a command list is obtained, the computing accelerator 30 can execute steps 403 - 404 and step 405 simultaneously. However, in steps 403 - 404, the query process does not need to decode the commands of all entries, so it will be completed relatively quickly. When the last entry decoded in step 405 is a link command, this link command has been processed during the query process in steps 403 - 404, and step 405 can directly skip it to avoid the generation of gaps.

[0089] Step 406: For each linked list data, when the decoded command to be processed is an end command, after all the commands in the current linked list data are executed, release the corresponding accommodation space of the linked list read request in the command submission queue to receive the next linked list read request from the host 20.

[0090] In this step, for a linked list data being processed, when the parsed entry is an end command, the computing accelerator 30 can wait for the execution of other commands in the current linked list data to complete, and then release the corresponding accommodation space of the linked list read request in the command submission queue, so that the computing accelerator can free up the accommodation space in the command submission queue to receive other linked list read requests sent by the host 20, making reasonable use of resources.

[0091] Step 407: Send a notification message to the host 20. For details, refer to the description of step 304 in the above embodiment.

[0092] For the above command linked list processing method, for each linked list read request, when obtaining the command list to be processed, by pre - checking whether the last entry of the cached command list is a link command, when it is found to be a link command, directly read a new command list from the memory according to the link command address, without completely decoding all the commands corresponding to the cached entries, reducing the read latency for the new command list, achieving the saving of chip resources without adding additional caches, and the linked list structure can reduce the interaction frequency between the CPU and the computing accelerator 30, reducing power consumption.

[0093] Please refer to Figure 5 , which is the command linked list processing method 500 of an embodiment of the present application. This method can be executed by the computing accelerator 30 provided by the embodiment of the present application, or can be executed by the electronic device 100. In some application scenarios, this method can be executed by Figure 1 the electronic device 100 shown as the computing accelerator 30, and can be applied to the above Figures 2A - 2CIn the data interaction scenario, the interaction frequency between the CPU and the computing accelerator 30 is reduced, the power consumption is reduced, the reading latency of the command list is reduced, and the data processing efficiency is improved. As Figure 5 shown, the method includes the following steps:

[0094] Step 501: Receive multiple linked list read requests from the host into a preset command submission queue 32. For details, refer to the description of step 301 in the above embodiment.

[0095] Step 502: When detecting a command read request for the command submission queue 32, in response to the command read request, parse out the storage address and length information of the command list to be processed from the command submission queue 32.

[0096] In this step, when a new computing task is generated, the host 20 CPU will create a new linked list in the memory and notify the computing accelerator 30 of the generation of a new linked list by writing to a register. In some embodiments, for a computing task, multiple linked lists can also be created. The notification information mainly includes the address and length of the linked list in the specified memory, and this information will be stored in the command submission queue 32 of the computing accelerator 30. For a currently processing linked list read request, when the command reading module 31 of the computing accelerator 30 receives the command read request from the command submission queue 32, if there is no command list currently being executed, it responds to the read request of the command submission queue 32, extracts the linked list information at the head of the submission queue, and calculates the storage address and length information of the command list.

[0097] Step 503: According to the storage address and length information, send an access request to the specified memory, cache the command list data returned by the memory into a preset cache, and update the write pointer of the preset cache.

[0098] In this step, the storage address is the storage address of the command list specified by the host 20 in the memory. The computing accelerator 30 needs to send an access request to the memory resource pointed to by this storage address, and cache the command list data returned by the memory in the command cache module 33, and update the write pointer of the command cache module 33.

[0099] In an embodiment, step 503 may specifically include: According to the length information, allocate corresponding storage space from the preset cache for the command read request, send an access request to the specified memory according to the storage address, and cache the command list data returned by the memory in the allocated storage space.

[0100] In an actual scenario, the preset cache can be implemented by the command cache module 33. Due to the access limitations of the data bus or memory, the read operation of a command list can be split into multiple read request commands. Before sending each read request command to the memory, the command reading module 31 can send a storage space allocation request to the command cache module 33 for each read request to ensure that the cache module has enough space to receive the command data returned by the memory. This can prevent the command cache module 33 from backpressuring the command data returned by the memory due to lack of reception space, thereby avoiding blocking the data bus.

[0101] Step 504: When the write pointer of the preset cache is different from the first read pointer of the preset cache, read the command list in the preset cache, calculate the position of the last entry in the command list according to the length information of the command list, and determine whether the command at the position of the last entry is a linked command. If so, go to Step 506.

[0102] In this step, when the write pointer of the preset cache is different from the first read pointer of the preset cache, it means that a new command list has been cached. Read the command list in the preset cache. The command pre-parsing module 34 of the accelerator 30 can directly calculate the position of the last entry in the current command list according to the length information of the current command list. When the write pointer of the command cache module 33 reaches this position, read the command cache module 33 and determine whether the command at this position is a linked command. If it is, go to Step 506; otherwise, go to Step 505. This way, it is not necessary to parse and check each entry, which can reduce the bandwidth for reading the command cache and save power consumption.

[0103] In an embodiment, assume that the position value of the first read pointer of the current command pre-parsing module 34 is A, and the command corresponding to this position is a linked command of a command list. The length value of the command list is L. The calculation method of the position value S of the read pointer of the linked command of the next command list is as follows:

[0104] When the position value A of the first read pointer is greater than the depth value H of the command cache module 33, start from the zero address and calculate S using the following formula. In this expression, " / " represents division to get the quotient, and "%" represents taking the remainder:

[0105] S = A + H * (L / H) + L % H

[0106] When the length value L of the command list is less than the depth value H of the command cache module 33, calculate S using the following formula:

[0107] S = A + L

[0108] Step 505: Determine whether the command at the position of the last entry is an end command. If so, go to Step 508; otherwise, return to Step 502.

[0109] In this step, if it is an end command, the host 20 can be notified that the linked list has been executed and resources can be released. If it is neither a link command nor an end command, it is directly skipped and step 502 is returned.

[0110] Step 506: Obtain a new command list from the specified memory according to the link command. For details, refer to the description of step 404 in the above embodiment.

[0111] Step 507: For each linked list data, when the write pointer of the preset cache is different from the second read pointer of the preset cache, decode the pending commands in the preset cache and execute the decoded pending commands, and release the corresponding resources of the pending commands in the preset cache. For details, refer to the description of step 405 in the above embodiment.

[0112] Step 508: For each linked list data, when the decoded pending command is an end command, after all the commands in the current linked list data are executed, release the corresponding accommodation space of the corresponding linked list read request in the command submission queue to receive the next linked list read request from the host 20. For details, refer to the description of step 406 in the above embodiment.

[0113] Step 509: Send a notification message to the host 20. For details, refer to the description of step 407 or step 304 in the above embodiment.

[0114] The above command linked list processing method can reduce the invalid memory access between the host 20 and the computing accelerator 30. By pre-querying the command list, the command reading delay is reduced and the data interaction efficiency is improved.

[0115] Please refer to Figure 6 which is the command linked list processing device 600 according to an embodiment of the present application. This device can be applied to Figure 1 the electronic device 100 shown in Figures 2A - 2C or applied to the computing accelerator 30, and can be applied to the data interaction scenario in the above

[0116] The receiving module 601 is configured to receive multiple linked list read requests from the host into a preset command submission queue. The command submission queue is configured with a preset number of accommodation spaces, and one accommodation space is used to cache one linked list read request;

[0117] The first processing module 602 is configured to sequentially read the linked list data corresponding to each linked list read request from the memory according to the reception order of each linked list read request, and sequentially execute multiple pieces of linked list data, where the linked list data includes: at least one command list;

[0118] The second processing module 603 is configured to, after a piece of linked list data is executed, release the corresponding accommodation space of the executed linked list data in the command submission queue;

[0119] The sending module 604 is configured to send a notification message to the host to receive the next linked list read request from the host.

[0120] In one embodiment, the receiving module 601 is configured to: when detecting a linked list read request from the host, if the number of existing linked list read requests in the command submission queue is less than a preset number, receive the current linked list read request into the command submission queue.

[0121] In one embodiment, the first processing module 602 is configured to: for each linked list read request, when detecting a command read request in the command submission queue, obtain a command list to be processed from a specified memory according to the command read request, where the command list is in a linked list structure, the command list includes multiple entries, and each entry stores a command to be processed; check whether the last entry stored in the command list is a link command; if the last entry stored in the command list is a link command, obtain a new command list from the specified memory according to the link command.

[0122] In one embodiment, the first processing module 602 is further configured to: when detecting a command read request in the command submission queue, in response to the command read request, parse the storage address and length information of the command list to be processed from the command submission queue; according to the storage address and length information, send an access request to a specified memory, cache the command list data returned by the memory into a preset cache, and update the write pointer of the preset cache.

[0123] In one embodiment, the first processing module 602 is further configured to: according to the length information, allocate a corresponding storage space in the preset cache for the command read request, send an access request to a specified memory according to the storage address, and cache the command list data returned by the memory in the allocated storage space.

[0124] In one embodiment, the first processing module 602 is further configured to: when the write pointer of the preset cache is different from the first read pointer of the preset cache, check each entry of the command list in the preset cache until the last entry of the command list is found, and determine whether the last entry of the command list stores a link command.

[0125] In one embodiment, the first processing module 602 is further configured to: when the write pointer of the preset buffer is different from the first read pointer of the preset buffer, read the command list in the preset buffer, calculate the position of the last entry in the command list according to the length information of the command list, and determine whether the command at the position of the last entry is a link command.

[0126] In one embodiment, the first processing module 602 is further configured to: for each linked list data, when the write pointer of the preset buffer is different from the second read pointer of the preset buffer, decode the pending command in the preset buffer and execute the decoded pending command, and release the corresponding resources of the pending command in the preset buffer.

[0127] In one embodiment, the second processing module 603 is configured to: for each linked list data, when the decoded pending command is an end command, after all the commands in the current linked list data are executed, release the corresponding accommodation space of the corresponding linked list read request in the command submission queue.

[0128] For the detailed description of the above command linked list processing device 600, please refer to the description of the relevant method steps in the above embodiments.

[0129] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, including: a program, which when running on an electronic device enables the electronic device to execute all or part of the processes of the methods in the above embodiments. Wherein, the storage medium can be a disk, an optical disc, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc. The storage medium can also include a combination of the above types of memories.

[0130] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for processing a command linked list, characterized in that, Including: Receiving multiple linked list read requests from a host into a preset command submission queue, wherein the command submission queue is configured with a preset number of accommodation spaces for caching the multiple linked list read requests; According to the receiving order of each of the linked list read requests, sequentially reading the linked list data corresponding to each of the linked list read requests from a memory and sequentially executing the multiple pieces of linked list data, the linked list data including at least one command list; After one piece of linked list data is executed, releasing the corresponding accommodation space of the executed linked list data in the command submission queue to receive the next linked list read request from the host; The sequentially reading the linked list data corresponding to each of the linked list read requests from the memory according to the receiving order of each of the linked list read requests includes: for each of the linked list read requests, when detecting a command read request of the command submission queue, in response to the command read request, parsing out the storage address and length information corresponding to the command list to be processed from the command submission queue; according to the storage address and the length information, sending an access request to a specified memory and caching the command list data returned by the memory into a preset cache, updating the write pointer of the preset cache, wherein the command list is in a linked list structure, the command list includes multiple entries, and each of the entries stores a command to be processed; checking whether the last entry stored in the command list is a link command; if the last entry stored in the command list is a link command, obtaining a new command list from the specified memory according to the link command.

2. The method according to claim 1, characterized in that, The receiving multiple linked list read requests from a host into a preset command submission queue includes: When detecting one of the linked list read requests from a host, if the number of the existing linked list read requests in the command submission queue is less than the preset number, receiving the current linked list read request into the command submission queue.

3. The method according to claim 1, characterized in that, The sending an access request to a specified memory according to the storage address and the length information and caching the command list data returned by the memory into a preset cache includes: Allocating a corresponding storage space from the preset cache for the command read request according to the length information; Sending an access request to a specified memory according to the storage address and caching the command list data returned by the memory in the allocated storage space.

4. The method according to claim 1, wherein The checking whether the last entry stored in the command list is a link command includes: When the write pointer of the preset cache is different from the first read pointer of the preset cache, checking each entry of the command list in the preset cache until the last entry of the command list is found, and judging whether the last entry of the command list stores a link command.

5. The method according to claim 1, characterized in that, The checking whether the last entry stored in the command list is a link command includes: When the write pointer of the preset cache is different from the first read pointer of the preset cache, read the command list in the preset cache, calculate the position of the last entry of the command list according to the length information of the command list, and determine whether the command at the position of the last entry is a link command.

6. The method according to claim 1, wherein The sequential execution of multiple pieces of linked list data includes: For each piece of linked list data, when the write pointer of the preset cache is different from the second read pointer of the preset cache, decode the pending command in the preset cache, execute the decoded pending command, and release the corresponding resources of the pending command in the preset cache.

7. The method according to claim 6, wherein The releasing of the corresponding accommodation space in the command submission queue for the executed linked list data after the execution of one piece of linked list data includes: For each piece of linked list data, when the decoded pending command is an end command, after all the commands in the current linked list data are executed, release the corresponding accommodation space of the corresponding linked list read request in the command submission queue.

8. A command linked list processing device, characterized in that Includes: A receiving module, configured to receive multiple linked list read requests from a host into a preset command submission queue, where the command submission queue is configured with a preset number of accommodation spaces for caching the multiple linked list read requests; A first processing module, configured to sequentially read the linked list data corresponding to each linked list read request from a memory according to the reception order of each linked list read request, and sequentially execute multiple pieces of linked list data, where the linked list data includes: at least one command list; A second processing module, configured to release the corresponding accommodation space in the command submission queue for the executed linked list data after the execution of one piece of linked list data, so as to receive the next linked list read request from the host; The first processing module is specifically configured to: for each linked list read request, when detecting a command read request of the command submission queue, in response to the command read request, parse the storage address and length information corresponding to the pending command list from the command submission queue; according to the storage address and the length information, send an access request to a specified memory, and cache the command list data returned by the memory into a preset cache, update the write pointer of the preset cache, where the command list is in a linked list structure, the command list includes multiple entries, and each entry stores a pending command; check whether the last entry stored in the command list is a link command; if the last entry stored in the command list is a link command, obtain a new command list from a specified memory according to the link command.

9. A computing accelerator, characterized in that, Includes: A command submission queue, configured to receive multiple linked list read requests from a host, where the command submission queue is configured with a preset number of accommodation spaces for caching the multiple linked list read requests; A command reading module, configured to obtain a list of commands to be processed from a specified memory according to a command read request when a command read request from the command submission queue is detected, wherein the command list is in a linked list structure, the command list includes a plurality of entries, and each entry stores a command to be processed; A command caching module, configured with a write pointer, for caching the command list data returned by the memory and updating the write pointer of the command caching module; A command pre-parsing module, configured with a first read pointer to the command caching module, for reading the command list data from the command caching module when the first read pointer is different from the write pointer, checking whether the last entry stored in the command list is a linked command, and for notifying the command reading module to obtain a new command list from the specified memory according to the linked command if the last entry stored in the command list is a linked command.

10. The computing accelerator according to claim 9, wherein Further comprising: A command decoding module, configured with a second read pointer to the command caching module, for reading the command list data from the command caching module when the second read pointer is different from the write pointer and decoding the command list to obtain the commands to be processed stored in each entry of the command list; An execution module, for executing the commands to be processed.

11. A circuit board, characterized in that, The computing accelerator according to any one of claims 9 to 10 is deployed on the circuit board.

12. An electronic device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the method according to any one of claims 1 to 7.

13. A non-transitory computer-readable storage medium, characterized in that, Comprising: a program, which when run by an electronic device, causes the electronic device to execute the method according to any one of claims 1 to 7.

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