Chip design method, device, equipment, and storage medium

Abstract

The present application provides a chip design method and apparatus, equipment, and storage medium; wherein, the method includes: determining a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions; searching a library for a second chip unit that meets replacement conditions; wherein, the replacement conditions include a layout that is the same as the chip unit to be replaced and has inherent electrical characteristics that are better than the chip unit to be replaced; replacing the first chip unit to be replaced with the second chip unit.

Description

Technical Field

[0001] The present application relates to electronic technology, and is related to but not limited to chip design methods and devices, equipment, and storage media. Background Art

[0002] As integrated circuit manufacturing processes enter the nanometer level, the speed and integration of chips continue to increase. Ultra-large-scale high-performance computing chips often integrate billions of transistors, which brings new problems and challenges to chip design. Summary of the invention

[0003] In view of this, the chip design method, device, equipment, and storage medium provided in the present application can achieve the purpose of optimizing the dynamic electrical parameters of the chip unit without adding additional windings or units, thereby improving the overall performance of the chip.

[0004] According to one aspect of an embodiment of the present application, a chip design method is provided, comprising: determining a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions; searching a library for a second chip unit that meets a first replacement condition; wherein the first replacement condition includes a layout that is the same as that of the first chip unit and has inherent electrical characteristics that are better than those of the first chip unit; and replacing the first chip unit with the second chip unit.

[0005] According to another aspect of an embodiment of the present application, a chip design method is provided, comprising: determining a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions; determining a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time; searching a fourth chip unit that meets a second replacement condition from a library; wherein the second replacement condition includes a layout that is the same as that of the third chip unit and has inherent electrical characteristics that are better than those of the third chip unit; replacing the third chip unit with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit.

[0006] According to one aspect of an embodiment of the present application, a chip design device is provided, including: a first determination module, configured to determine a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions; a first search module, configured to search a library for a second chip unit that meets a first replacement condition; wherein the first replacement condition includes a layout that is the same as the first chip unit and an inherent electrical characteristic that is better than the first chip unit; and a first replacement module, configured to replace the first chip unit with the second chip unit.

[0007] According to another aspect of an embodiment of the present application, a chip design device is provided, comprising: a second determination module, configured to determine a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions; a third determination module, configured to determine a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time; a second search module, configured to search a fourth chip unit that meets a second replacement condition from a library; wherein the second replacement condition includes a layout pattern that is the same as that of the third chip unit and an inherent electrical characteristic that is better than that of the third chip unit; and a second replacement module, configured to replace the third chip unit with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit.

[0008] According to one aspect of an embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, the method described in the embodiment of the present application is implemented.

[0009] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method provided in the embodiment of the present application is implemented.

[0010] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0013] Figure 1 A schematic diagram of the implementation flow of the chip design method provided in the embodiment of the present application;

[0014] Figure 2 A structural schematic diagram of an equivalent circuit for dynamic operation of a first chip unit;

[0015] Figure 3A schematic diagram of the implementation flow of another chip design method provided in an embodiment of the present application;

[0016] Figure 4 A structural schematic diagram of an equivalent circuit for dynamic operation of a first chip unit;

[0017] Figure 5 A schematic diagram of an implementation flow of another chip design method provided in an embodiment of the present application;

[0018] Figure 6 A schematic diagram of the implementation flow of another chip design method provided in an embodiment of the present application;

[0019] Figure 7 A schematic diagram of the structure of a chip design device provided in an embodiment of the present application;

[0020] Figure 8 A schematic diagram of the structure of another chip design device provided in an embodiment of the present application;

[0021] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0024] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] The embodiment of the present application provides a chip design method, which is applied to electronic devices. During the implementation process, the electronic devices can be various types of devices with information processing capabilities, for example, the electronic devices can include personal computers, laptops, tablet computers, mobile phones, etc. The functions implemented by the method can be implemented by calling program codes by a processor in the electronic device. Of course, the program codes can be stored in a computer storage medium. It can be seen that the electronic device at least includes a processor and a storage medium.

[0026] Figure 1A schematic diagram of the implementation flow of the chip design method provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, the method may include the following steps 101 to 103:

[0027] Step 101 : determining a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions.

[0028] The so-called dynamic electrical parameters refer to electrical parameters that change due to the working state of the chip itself or the working state of the chip unit connected to it. In the embodiment of the present application, there is no restriction on the type of dynamic electrical parameters. In short, they are parameters that affect the performance of the chip, such as the working speed. In some embodiments, the dynamic electrical parameters include at least one of the following: dynamic voltage drop, peak power, and glitch power.

[0029] Different types of dynamic electrical parameters have different corresponding chip design conditions. In some embodiments, the dynamic electrical parameters include dynamic voltage drop, and the corresponding chip design condition is that the dynamic voltage drop is greater than a first threshold value, and the unit of the first threshold value is the unit of dynamic voltage drop, which is used to detect whether there is a problem with the dynamic voltage drop of the chip unit. Similarly, in other embodiments, the dynamic electrical parameters include peak power, and the corresponding chip design condition is that the peak power is greater than a second threshold value, and the unit of the second threshold value is the unit of peak power, which is used to detect whether there is a problem with the peak power of the chip unit. In some other embodiments, the dynamic electrical parameters include fault power, and the corresponding chip design condition is that the fault power is greater than a third threshold value, and the unit of the third threshold value is the unit of fault power, which is used to detect whether there is a problem with the fault power of the chip unit.

[0030] Step 102, searching the library for a second chip unit that meets a first replacement condition; wherein the first replacement condition includes having a layout that is the same as that of the first chip unit and having inherent electrical characteristics that are better than those of the first chip unit.

[0031] In some embodiments, the layout is the same as the first chip unit, including: the components and the connection relationship of the corresponding components are the same as the first chip unit, and the bottom layer doping is different from the first chip unit. That is, the circuit structure and unit function of the two chip units are the same, only the bottom layer doping is different; in this way, the first chip unit is replaced by the second chip unit with the same layout and better inherent electrical characteristics, so as to achieve the purpose of optimizing the dynamic electrical parameters of the first chip unit without adding additional windings or units, so that the iteration time of the recheck (signoff) in the chip design stage can be greatly saved, and the optimization efficiency of the chip design can be improved.

[0032] The so-called inherent electrical characteristics refer to characteristic parameters that do not change with the change of the working state of the chip unit itself or the chip unit connected to it. The quality of the inherent electrical characteristics directly affects the size of the dynamic electrical parameters of the unit. In the embodiments of the present application, there is no limitation on the inherent electrical characteristics, as long as they can affect the dynamic electrical parameters of the chip unit connected to it. In some embodiments, the inherent electrical characteristics include delay and / or threshold voltage; the inherent electrical characteristics are better than the first chip unit, including: the delay and / or threshold voltage is greater than the first chip unit.

[0033] Step 103: Replace the first chip unit to be replaced with the second chip unit, thereby achieving the purpose of optimizing the dynamic electrical parameters of the first chip unit.

[0034] It is understandable that the quality of the inherent electrical characteristics directly affects the size of the dynamic electrical parameters of the unit. For example, the greater the delay or the greater the threshold voltage, the smaller the current of the branch where the unit is located, and the corresponding dynamic electrical parameters are also better. For example, Figure 2 FIG. 1 is a schematic diagram of a structure of an equivalent circuit of a first chip unit (labeled as inst1) in dynamic operation, taking the dynamic electrical parameters including the dynamic voltage drop as an example. Figure 2 As shown, the dynamic voltage drop on inst1 is determined by I total , the resistor network RC1 and the resistor network RC2 jointly determine that reducing I1 can reduce I total , thereby optimizing the dynamic voltage drop on inst1. Therefore, inst1 can be replaced with a second chip unit with a larger threshold voltage or larger delay but the same layout to reduce I1, thereby reducing I total , thereby reducing the dynamic voltage drop across inst1. In this way, the dynamic voltage drop on inst1 can be improved without re-layout and re-routing.

[0035] In an embodiment of the present application, a first chip unit whose dynamic electrical parameters do not meet the chip design conditions in the designed chip structure is found; a second chip unit whose layout is the same as the first chip unit but whose inherent electrical characteristics are better than the first chip unit is found from the library; the first chip unit to be replaced is replaced with the second chip unit; in this way, the purpose of optimizing the dynamic electrical parameters is achieved without adding additional windings or units, thereby improving the overall performance of the chip.

[0036] The present application embodiment further provides a chip design method, Figure 3 A schematic diagram of the implementation flow of another chip design method provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the method includes the following steps 301 to 312:

[0037] Step 301, determining a first chip unit in the designed chip structure whose dynamic electrical parameters do not meet the chip design conditions;

[0038] Step 302 , searching the library for a second chip unit that meets the first replacement condition; if the second chip unit is found, executing step 303 ; if the second chip unit is not found, executing step 308 .

[0039] The first replacement condition includes: the layout is the same as the first chip unit and the inherent electrical characteristics are better than the first chip unit.

[0040] Further, in some embodiments, the first replacement condition includes that the layout is the same as the first chip unit and the inherent electrical characteristics are optimal. Accordingly, the second chip unit found is a chip unit with the same layout as the first chip unit and the inherent electrical characteristics are better than those of the first chip unit. For example, the second chip unit is a chip unit with the largest delay or the largest threshold voltage among the multiple chip units.

[0041] Step 303, replacing the first chip unit to be replaced with the second chip unit; then, proceeding to step 304;

[0042] Step 304, determine whether the dynamic electrical parameters of the second chip unit meet the chip design conditions; if not, execute step 305; if so, end the optimization of the dynamic electrical parameters of the second chip unit, continue to find the next chip unit whose dynamic electrical parameters do not meet the chip design conditions, and use the same method to optimize it.

[0043] It can be understood that after the first chip unit is replaced by the second chip unit, it is still necessary to determine whether the dynamic electrical parameters of the second chip unit meet the chip design conditions; if not, it is further optimized through the following steps 305 and 306, so as to further improve the chip performance without adding additional windings or units.

[0044] Step 305: Determine a third chip unit that is connected to the second chip unit and has an overlapping working time.

[0045] It can be understood that the so-called intersection of working time means that the working time of two chip units at least partially overlaps. In some embodiments, the connection relationship is a parallel relationship or a series relationship.

[0046] Step 306, performing a replacement operation on the third chip unit; the replacement operation includes searching a library for a fourth chip unit that meets a second replacement condition, and step 307;

[0047] The second replacement condition includes: the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit.

[0048] In some embodiments, Figure 3 As shown, if there is no fourth chip unit satisfying the second replacement condition in the library, then enter step 311, continue to search for a fifth chip unit that is connected to the second chip unit and has an intersection in working time, and then find a chip unit from the library that can replace the fifth chip unit, thereby optimizing the dynamic electrical parameters of the second chip unit.

[0049] Step 307 , replacing the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the second chip unit, that is, achieving the purpose of optimizing the dynamic electrical parameters of the second chip unit; then, entering step 310 .

[0050] For example, Figure 4 Schematic diagram of the structure of the equivalent circuit of the first chip unit (marked as inst1), taking the dynamic electrical parameters including the dynamic voltage drop as an example, the third chip unit (marked as inst2) is a chip unit having a connection relationship with the first chip unit or the second chip unit after replacement, such as Figure 4 As shown, the voltage drop on inst1 is determined by I total , the resistor network RC1 and the resistor network RC2 jointly determine that reducing I1 or I2 can reduce I total Therefore, in addition to replacing the first chip unit (inst1) with the second chip unit, the third chip unit (inst2) connected thereto can also be replaced with a fourth chip unit with a larger threshold voltage or a larger delay but the same layout to reduce I2, thereby further reducing I total , thereby reducing the dynamic voltage drop across inst1. In this way, the dynamic voltage drop across inst1 can be further improved without re-layout and re-routing.

[0051] Step 308: Determine a third chip unit that is connected to the first chip unit and has an overlapping working time.

[0052] The so-called intersection of working time means that the working time (ie time window) of two units is at least partially overlapped. In some embodiments, the connection relationship is a parallel relationship or a series relationship.

[0053] Step 309, performing a replacement operation on the third chip unit; the replacement operation includes: searching for a fourth chip unit that meets the second replacement condition from the library, and replacing the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit; then, entering step 310;

[0054] The second replacement condition includes: the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit.

[0055] In some embodiments, Figure 3 As shown, if the fourth chip unit that meets the second replacement condition is not found in the library, step 311 is also entered to continue searching for a fifth chip unit that is connected to the first chip unit and has an intersection in working time, and then a chip unit that can replace the fifth chip unit is searched from the library, thereby optimizing the dynamic electrical parameters of the second chip unit.

[0056] For the principles of step 308 and step 309, please refer to the above Figure 4 The equivalent circuit diagram is shown for understanding.

[0057] It can be understood that for a first chip unit whose dynamic electrical parameters do not meet the chip design conditions, if there is no second chip unit in the library that can replace the chip unit, the dynamic electrical parameters of the first chip unit are continuously optimized through steps 308 and 309, that is, a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time is found, and a replacement operation is performed on the third chip unit; in this way, even if there is no second chip unit in the library that can replace the first chip unit, the purpose of optimizing the dynamic electrical parameters of the first chip unit can be achieved, thereby enhancing the flexibility of optimizing the dynamic electrical parameters of the first chip unit without adding additional windings or units.

[0058] Step 310, determining whether the dynamic electrical parameters of the target chip unit (ie, the first chip unit or the second chip unit) meet the chip design conditions; if yes, then end; otherwise, execute step 311;

[0059] Step 311, continue to determine a fifth chip unit that has a connection relationship with the target chip unit and has an intersection in working time; wherein the target chip unit is the first chip unit or the second chip unit;

[0060] Step 312, performing a replacement operation on the fifth chip unit until the dynamic electrical parameters of the target chip unit meet the chip design conditions; wherein the fifth chip unit is different from the fourth chip unit; the replacement operation in step 312 includes: searching for a sixth chip unit that meets a third replacement condition from a library, and replacing the fifth chip unit with the sixth chip unit, thereby affecting the dynamic electrical parameters of the target chip unit; wherein the third replacement condition includes: the layout is the same as that of the fifth chip unit and the inherent electrical characteristics are better than those of the fifth chip unit.

[0061] In an embodiment of the present application, for a first chip unit whose dynamic electrical parameters do not meet the chip design conditions, optimization is continuously performed through the above steps until the dynamic electrical parameters of the first chip unit or a second chip unit replacing the chip unit meet the chip design conditions, and then the optimization of the dynamic electrical parameters at the position of the first chip unit is completed; in this way, without adding additional windings or units, the maximum degree of optimization is achieved, thereby maximizing the chip performance.

[0062] The present application embodiment further provides a chip design method, Figure 5 A schematic diagram of the implementation flow of another chip design method provided in the embodiment of the present application is shown as follows: Figure 5 As shown, the following steps 501 to 504 may be included:

[0063] Step 501, determining a first chip unit in the designed chip structure whose dynamic electrical parameters do not meet the chip design conditions;

[0064] Step 502, determining a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time;

[0065] Step 503, searching the library for a fourth chip unit that meets a second replacement condition; wherein the second replacement condition includes that the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit;

[0066] Step 504: Replace the third chip unit to be replaced with the fourth chip unit, thereby affecting (ie, optimizing) the dynamic electrical parameters of the first chip unit.

[0067] In some embodiments, if there is no fourth chip unit satisfying the second replacement condition in the library, step 311 and step 312 are performed, thereby achieving the purpose of optimizing the dynamic electrical parameters of the first chip unit.

[0068] In some embodiments, after executing step 504, it is determined whether the dynamic electrical parameters of the first chip unit meet the chip design conditions. If not, the solutions of steps 311 and 312 are executed to maximize the optimization of the dynamic electrical parameters of the first chip unit.

[0069] It should be noted that for Figure 5 The described embodiment is similar to the description of the other method embodiments mentioned above. For the technical details not disclosed in this embodiment, please refer to the description of the other method embodiments mentioned above for understanding.

[0070] In some embodiments, the inherent electrical characteristics are better than the chip unit to be replaced, including: the delay and / or threshold voltage are greater than the chip unit to be replaced; the layout is the same as the chip unit to be replaced, including: the connection relationship between components and corresponding components is the same as that of the chip unit to be replaced, while the bottom layer doping is different from that of the chip unit to be replaced.

[0071] As the process size shrinks, the integration density of chips increases, and the operating frequency increases. This brings new problems and challenges to the dynamic voltage drop of chips. Dynamic voltage drop will affect the working speed of the chip, and in severe cases, it may even cause functional errors, so it must be taken seriously.

[0072] In some embodiments, the main methods for optimizing dynamic voltage drop are: increasing the density of the power network, manually reducing the density of local chip cells, and adding decoupling cells (decap) around cells with relatively large voltage drop.

[0073] However, these methods for optimizing dynamic voltage drop require changing the layout and wiring of the module (block) in order to achieve the purpose of reducing the dynamic voltage drop, which will lead to an increase in the module area; during the engineer's manual optimization stage (eco), the iteration time of PPA signoff will be greatly prolonged, so the overall efficiency is relatively low.

[0074] Based on this, an exemplary application of an embodiment of the present application in a practical application scenario will be described below.

[0075] Figure 4 This is the equivalent circuit diagram of a cell (labeled as inst1) in the chip during dynamic operation. inst2 is a cell that is physically placed close to inst1. During dynamic operation, the TW (timing window) of inst1 and inst2 overlaps. The voltage drop on inst1 is determined by I total It is determined by the resistor network RC1 and the resistor network RC2, so reducing I1 or I2 can reduce I total, thereby optimizing the dynamic voltage drop on inst1.

[0076] In the embodiment of the present application, the cell is replaced (swap), and the current cell is replaced with another cell with a larger threshold voltage or a longer channel length but the same layout (layout), so that the delay value of one of the insts becomes larger, so as to reduce I1 or I2, thereby reducing I total , thereby reducing the voltage drop on inst1. This can improve the dynamic voltage drop on inst1 without re-layout and re-routing.

[0077] This solution optimizes the specific process of dynamic voltage drop, such as Figure 6 As shown, it includes the following steps 601 to 607:

[0078] Step 601, select a cell with a dynamic voltage drop problem and mark it as inst1 (e.g. Figure 4 shown);

[0079] Step 602, determine whether inst1 can be replaced; if it can be replaced, execute step 603; otherwise, execute step 606;

[0080] The judgment criteria for replacement are: there is a cell with the same layout as inst1 in the library, and the delay or threshold voltage of the cell is larger than that of inst1.

[0081] Step 603: If there is a cell in the library with the same layout as inst1 (referred to as inst3 for convenience of description), and the delay or threshold voltage of inst3 is larger than that of inst1, then inst1 can be replaced with inst3. After the direct replacement, the dynamic voltage drop at the position can be alleviated. Then proceed to step 604.

[0082] For example Figure 6 As shown in FIG. 1 , the replacement strategy is to replace the ulvt type cell with the lvt type cell; another example is to replace the Ivt type cell with the svt type cell; another example is to replace the H8 type cell with the H11 type cell. In these examples, the physical parameters of the cell before and after the replacement are the same, but the electrical parameters are different.

[0083] Step 604, it can be determined whether the dynamic voltage drop of inst3 after replacement meets the requirement; if not, execute step 605; if so, end;

[0084] Step 605 , the same operation may be performed by continuing to find neighboring cells whose time windows at least partially overlap. After that, the dynamic voltage drop of inst3 is evaluated, and the process ends if the dynamic voltage drop of inst3 meets the requirement.

[0085] Step 606: If inst1 cannot be replaced, find other cells (labeled as inst2) around it whose time window at least partially overlaps with it.

[0086] Step 607, based on the above judgment criteria for replacement, determine whether inst2 can be replaced; if there is room for replacement, replace it to achieve optimization of dynamic voltage drop, and then determine whether the dynamic voltage drop after replacement meets the requirements, if not, continue to find cells with at least partial overlap in time windows around it to perform the same operation; if the dynamic voltage drop meets the requirements, end.

[0087] Repeat the above steps until the dynamic voltage drop meets the requirements.

[0088] In an embodiment of the present application, only the threshold voltage or channel length of a specific cell group is changed, which will not affect the physical layout and wiring. The purpose of optimizing the dynamic voltage drop can be achieved without adding additional windings or units. The main current is changed by increasing the threshold voltage or increasing the channel length, and the layout of the replaced cell remains unchanged, so there is no need to re-layout and rewire, and the dynamic voltage drop on the cell can be optimized. The method is simple and feasible, and can greatly save the iteration time of signoff in the eco stage, thereby improving the optimization efficiency of the dynamic voltage drop. In addition, there is no need to add additional units and wiring, and the overall performance (PPA) of the design can be guaranteed while optimizing the voltage drop.

[0089] This technical solution is applicable in both the layout and routing stage (PnR) and the engineer manual optimization stage (eco). This solution can not only be used to improve dynamic voltage drop, but also is applicable to the optimization of peak power and fault power.

[0090] It should be noted that although the steps of the method in the present application are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.; or, steps in different embodiments may be combined into a new technical solution.

[0091] Based on the foregoing embodiments, an embodiment of the present application provides a chip design device, and the modules included in the device can be implemented by a processor; during the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0092] Figure 7 A schematic diagram of the structure of a chip design device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the chip design device 70 includes:

[0093] A first determination module 701 is configured to determine a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet chip design conditions;

[0094] A first search module 702 is configured to search the library for a second chip unit that meets a first replacement condition; wherein the first replacement condition includes a layout that is the same as the first chip unit and an inherent electrical characteristic that is better than the first chip unit;

[0095] The first replacement module 703 is configured to replace the first chip unit to be replaced with the second chip unit.

[0096] In some embodiments, the first determination module 701 is further configured to determine a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time based on determining that a second chip unit that meets the first replacement condition is not found in the library; the first replacement module 703 is further configured to search the library for a fourth chip unit that meets the second replacement condition, and replace the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit; wherein the second replacement condition includes: the layout pattern is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit.

[0097] In some embodiments, the first determination module 701 is further configured to, after replacing the first chip unit with the second chip unit, determine a third chip unit that has a connection relationship with the second chip unit and has an intersection in working time based on determining that the dynamic electrical parameters of the second chip unit do not meet the chip design conditions; the first replacement module 703 is further configured to search the library for a fourth chip unit that meets the second replacement condition, and replace the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the second chip unit; wherein the second replacement condition includes: the layout is the same as the third chip unit and the inherent electrical characteristics are better than the third chip unit.

[0098] In some embodiments, the first determination module 701 is further configured to, after replacing the third chip unit with the fourth chip unit, continue to determine a fifth chip unit that has a connection relationship with the target chip unit and has an intersection in working time based on determining that the dynamic electrical parameters of the target chip unit do not meet the chip design conditions; wherein the target chip unit is the first chip unit or the second chip unit; the first replacement module 703 is further configured to perform a replacement operation on the fifth chip unit until the dynamic electrical parameters of the target chip unit meet the chip design conditions; wherein the fifth chip unit is different from the fourth chip unit; the replacement operation includes: searching for a sixth chip unit that meets the third replacement condition from the library, and replacing the fifth chip unit with the sixth chip unit, thereby affecting the dynamic electrical parameters of the target chip unit; wherein the third replacement condition includes: the layout is the same as the fifth chip unit and the inherent electrical characteristics are better than the fifth chip unit.

[0099] The present application embodiment further provides a chip design device, Figure 8 A schematic diagram of the structure of another chip design device provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the chip design device 80 includes:

[0100] A second determination module 801 is configured to determine a first chip unit in a designed chip structure whose dynamic electrical parameters do not meet a chip design condition;

[0101] A third determination module 802 is configured to determine a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time;

[0102] The second search module 803 is configured to search the library for a fourth chip unit that meets a second replacement condition; wherein the second replacement condition includes: the layout is the same as the third chip unit and the inherent electrical characteristics are better than the third chip unit; wherein the second replacement condition includes: the layout is the same as the third chip unit and the inherent electrical characteristics are better than the third chip unit;

[0103] The second replacement module 804 is configured to replace the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit.

[0104] In some embodiments, the third determination module 802 is further configured to, after replacing the third chip unit with the fourth chip unit, continue to determine a fifth chip unit that has a connection relationship with the first chip unit and has an intersection in working time based on determining that the dynamic electrical parameters of the first chip unit do not meet the chip design conditions; the second replacement module 804 is further configured to perform the replacement operation on the fifth chip unit until the dynamic electrical parameters of the first chip unit meet the chip design conditions; wherein, the fifth chip unit is different from the fourth chip unit.

[0105] In some embodiments, the third determination module 803 is further configured to, if a fourth chip unit that meets the replacement conditions is not found in the library, continue to determine a fifth chip unit that has a connection relationship with the first chip unit and has an intersection in working time; the second replacement module 804 is further configured to perform the replacement operation on the fifth chip unit until the dynamic electrical parameters of the first chip unit meet the chip design conditions; wherein the fifth chip unit is different from the fourth chip unit.

[0106] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0107] It should be noted that the division of modules in the chip design device provided in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or it can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. It can also be implemented in the form of a combination of software and hardware.

[0108] It should be noted that in the embodiment of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable an electronic device to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific combination of hardware and software.

[0109] An embodiment of the present application provides an electronic device, Fig. 9 A schematic diagram of a hardware entity of an electronic device provided in an embodiment of the present application, such as Fig. 9 As shown, the electronic device 90 includes a memory 901 and a processor 902, wherein the memory 901 stores a computer program that can be run on the processor 902, and the processor 902 implements the steps in the method provided in the above embodiment when executing the program.

[0110] It should be noted that the memory 901 is configured to store instructions and applications executable by the processor 902, and can also cache data to be processed or already processed by the processor 902 and various modules in the electronic device 90 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0111] An embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the method provided in the above embodiment are implemented.

[0112] An embodiment of the present application provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps of the method provided in the above method embodiment.

[0113] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium, storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0114] It should be understood that "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in one embodiment" or "in some embodiments" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The above description of each embodiment tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. For the sake of brevity, this article will not repeat them.

[0115] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist at the same time, and object B exists alone.

[0116] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or modules can be electrical, mechanical or other forms.

[0118] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules; they may be located in one place or distributed on multiple network units; some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0119] In addition, all functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may be a separate unit, or two or more modules may be integrated into one unit; the above-mentioned integrated modules may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0120] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0121] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling an electronic device to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0122] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0123] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0124] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0125] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip design method, characterized in that: The method comprises: Determine a first chip unit in the designed chip structure whose dynamic electrical parameters do not meet the chip design conditions; Searching for a second chip unit that meets a first replacement condition from the library; wherein the first replacement condition includes: having the same layout as the first chip unit and having inherent electrical characteristics that are better than the first chip unit; replacing the first chip unit with the second chip unit; The method further comprises: Based on the determination that the second chip unit satisfying the first replacement condition is not found in the library, a third chip unit having a connection relationship with the first chip unit and having an intersection in working time is determined; a fourth chip unit satisfying the second replacement condition is searched from the library, and the third chip unit is replaced by the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit; Alternatively, after replacing the first chip unit with the second chip unit, based on determining that the dynamic electrical parameters of the second chip unit do not meet the chip design conditions, a third chip unit having a connection relationship with the second chip unit and having an intersection in working time is determined; a fourth chip unit meeting the second replacement condition is searched from the library, and the third chip unit is replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the second chip unit; The second replacement condition includes: the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit.

2. The method according to claim 1, characterized in that The method further comprises: After replacing the third chip unit with the fourth chip unit, based on determining that the dynamic electrical parameters of the target chip unit do not meet the chip design conditions, continue to determine a fifth chip unit that has a connection relationship with the target chip unit and has an intersection in working time; wherein the target chip unit is the first chip unit or the second chip unit; Performing a replacement operation on the fifth chip unit until the dynamic electrical parameters of the target chip unit meet the chip design conditions; wherein the fifth chip unit is different from the fourth chip unit; the replacement operation includes: searching for a sixth chip unit that meets the third replacement condition from a library, and replacing the fifth chip unit with the sixth chip unit, thereby affecting the dynamic electrical parameters of the target chip unit; The third replacement condition includes: the layout is the same as that of the fifth chip unit and the inherent electrical characteristics are better than those of the fifth chip unit.

3. The method according to claim 1 or 2, characterized in that: The inherent electrical characteristics are better than the chip unit to be replaced, including: delay and / or threshold voltage is greater than the chip unit to be replaced; The layout is the same as that of the chip unit to be replaced, including: components and connection relationships of corresponding components are the same as those of the chip unit to be replaced, while bottom layer doping is different from that of the chip unit to be replaced.

4. A chip design method, characterized in that: The method comprises: Determine a first chip unit in the designed chip structure whose dynamic electrical parameters do not meet the chip design conditions; Determine a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time; Searching the library for a fourth chip unit that meets a second replacement condition; wherein the second replacement condition includes that the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit; The third chip unit is replaced by the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit.

5. A chip design device, characterized in that: include: A first determination module is configured to determine a first chip unit in the designed chip structure whose dynamic electrical parameters do not meet the chip design conditions; A first search module is configured to search the library for a second chip unit that meets a first replacement condition; wherein the first replacement condition includes that the layout is the same as that of the first chip unit and the inherent electrical characteristics are better than those of the first chip unit; a first replacement module, configured to replace the first chip unit with the second chip unit; The first determination module is further configured to determine a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time based on determining that the second chip unit that meets the first replacement condition is not found in the library; the first replacement module is further configured to search for a fourth chip unit that meets the second replacement condition from the library, and replace the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit; Alternatively, the first determination module is further configured to, after replacing the first chip unit with the second chip unit, determine a third chip unit that has a connection relationship with the second chip unit and has an intersection in working time based on determining that the dynamic electrical parameters of the second chip unit do not meet the chip design conditions; the first replacement module is further configured to search for a fourth chip unit that meets the second replacement condition from the library, and replace the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameters of the second chip unit; The second replacement condition includes: the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit.

6. A chip design device, characterized in that: include: A second determination module is configured to determine a first chip unit in the designed chip structure whose dynamic electrical parameters do not meet the chip design conditions; A third determination module is configured to determine a third chip unit that has a connection relationship with the first chip unit and has an intersection in working time; A second search module is configured to search the library for a fourth chip unit that meets a second replacement condition; wherein the second replacement condition includes that the layout is the same as that of the third chip unit and the inherent electrical characteristics are better than those of the third chip unit; The second replacement module is configured to replace the third chip unit with the fourth chip unit, thereby affecting the dynamic electrical parameters of the first chip unit.

7. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 3 is implemented, or when the processor executes the program, the method according to claim 4 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 3 is implemented; or when the computer program is executed by a processor, the method according to claim 4 is implemented.

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