Test chip pad arrangement method, design method and system, and test chip

Abstract

The application provides a pad arrangement method of a test chip, which comprises the following steps: arranging a plurality of pad groups on the test chip in a manner that two pad groups are arranged in a staggered manner in a first direction, so as to form a plurality of pad sequences along the first direction; and forming optional areas of pads in the pad sequences on both sides of the pad sequences, so as to realize the layout of the optional areas of the pads and form test paths by connecting the pads with test object pins in the optional areas of the pads. By arranging the pads in the staggered manner, more optional areas can be arranged in the whole chip; and more devices to be tested can be connected to the test chip while supporting single-row independent testing or double-row parallel testing. The application also provides a test chip design method, a test chip design system and a test chip, which have corresponding advantages.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and particularly relates to a method for arranging pads for a test chip, a test chip design method and system, and a corresponding test chip. Background Technology

[0002] Due to the extremely high cost of advanced process tape-out, it is desirable to plan as many optional areas as possible for direct-connect testing in a single tape-out, thereby reducing the area cost of each test structure. Therefore, a pad placement strategy that optimizes area utilization is crucial. The specifications of the probe card outside the chip will constrain the shape, size, and distribution of the pads inside the chip, and ultimately determine the number and location of optional areas.

[0003] Depending on the chip test structure and testing requirements, one approach to pad distribution involves using a metal layer higher than the internal interconnect metal layer, arranged directly above the test structure in an area array. This area array pad design takes into account that the on-chip direct-connect test chip removes all the rear metal sections and vias of the original product chip, allowing the entire chip area to be used for metal layer pads without causing short circuits to internal connections.

[0004] like Figure 1 As shown, in this array, the preset spacing values ​​between adjacent pads in the row and column directions can be denoted as pitchX and pitchY, respectively; the preset dimensions of the pads in the row and column directions can be denoted as sizeX and sizeY, respectively. In traditional designs, to ensure sufficient spacing between probes and avoid accidental short circuits, the distance between pads is not less than the side length of the pad itself.

[0005] In one test chip pad layout scheme employing an area array design, each pad group consists of two rows of pads, forming several selectable areas for devices under test (DUTs) on both sides of each row. The ratio of the number of pads to the number of DUTs depends on the number of connection ports required for testing each type of DUT. Based on the chip size, these pad groups are densely packed across the chip surface to complete the layout of all selectable areas. When using a single-row probe card, only one row of pads in the same probe group will contact the probe at any given time; when using a double-row probe card, both rows of pads in the same probe group will contact the probe simultaneously, accelerating the testing speed by 100%. However, existing methods still have drawbacks. One drawback is that the pad spacing is constrained by the probe spacing, and the spacing space is only used for trace routing, not for selecting DUTs. This drawback limits the number of selectable areas that can be arranged across the entire chip and also limits the selection of device instances within each selectable area.

[0006] With the development of chip test structure and test requirement, the design method of test chip is required to be improved.

[0007] Chip products are diversified, and the design maturity and process sensitivity of each chip are different, and even there can be great difference, so in the process of chip introduction, many problems that are not found or not paid attention to in the process development stage will occur, resulting in the disconnection between process development and product introduction. Under the traditional test chip process, the user can only test the test structure in the test chip to infer the state of the corresponding device in the product chip. However, with the continuous evolution of the process node, the difference between the device in the product chip and the test structure in the test chip due to the different physical environments gradually emerges. It is necessary to study how to use the real product chip to design the built-in test chip method, so as to realize the test of the key device in the product chip in the real physical environment. This has great significance for the improvement of chip product yield. SUMMARY

[0008] The present application is to solve all or part of the problems of the prior art, and the present application provides a test chip pad arrangement method. The present application also provides a test chip design method and system based on the pad arrangement method of the present application, which is suitable for designing a built-in test chip using a real product chip. The present application also provides a test chip designed by the test chip design method of the present application.

[0009] The test chip pad arrangement method provided by the present application comprises: arranging a plurality of pad groups on a test chip in a manner that two pad groups are arranged in a staggered manner in a first direction to form a plurality of pad sequences along the first direction; determining optional areas of pads in the pad sequence on both sides of the pad sequence, respectively, for connecting the pins of the test objects in the optional areas of the pads to form test paths; wherein the pad group is a pad array; the first direction refers to the row direction or the column direction of the pad array in the pad group. It should be noted that whether the optional area is on the two sides of the row or the two sides of the column needs to be determined in combination with the staggered pad groups, and can only be one-to-one correspondence. If the pads are staggered in the row direction, the optional area is on both sides of a row of pad sequences, and if the pads are staggered in the column direction, the optional area is on both sides of a column of pad sequences. By determining the optional areas of the pads in the pad sequence on both sides of the pad sequence along the first direction, the layout of the optional areas of the pads is realized. By the pad arrangement method of the present application, the pad spacing can be reduced to the maximum extent under the premise of avoiding probe short circuit, so as to arrange more optional areas in the whole chip.

[0010] The test chip is used for forming test paths by pad contact with external probes, pads belonging to different pad groups in the pad sequence do not contact probes at the same time to ensure that there is enough spacing space between probes to avoid short circuit caused by mis-touch.

[0011] The pad groups are pad arrays, and the interval values of adjacent pads in the pad groups in the row direction and the column direction are preset values pitchX and pitchY, which satisfy: pitchX≥2×sizeX+2×space; pitchY≥2×sizeY+2×space; wherein, the sizeX and the sizeY are the sizes of the pads in the row direction and the column direction respectively, and the space is a preset design rule distance.

[0012] The pad sequence is formed by alternately arranging pads belonging to two pad groups, the two pad groups are respectively recorded as a first pad group and a second pad group, and the pitchX of the first pad group and the pitchX of the second pad group are equal, and the pitchY of the first pad group and the pitchY of the second pad group are equal.

[0013] The pad sequence is formed by alternately arranging pads belonging to two pad groups, the two pad groups are respectively recorded as a first pad group and a second pad group, and the pitchX of the first pad group and the pitchX of the second pad group are equal, and the pitchY of the first pad group and the pitchY of the second pad group are equal.

[0014] The length of the optional area is the total length of the pad sequence in the first direction (including pads and pad spacing areas), and the width of the optional area is not greater than half of the interval of the pad sequence and its adjacent pad sequence in the second direction; the second direction is a direction orthogonal to the first direction. The area of the optional area can be greater than the area of a single optional area in a single pad group in the existing pad distribution method.

[0015] The pad sequence is formed by alternately arranging pads belonging to two pad groups, the two pad groups are respectively recorded as a first pad group and a second pad group, and the pitchX of the first pad group and the pitchX of the second pad group are equal, and the pitchY of the first pad group and the pitchY of the second pad group are equal.

[0016] The pad arrangement method further comprises: dividing the optional area into a plurality of sub-areas (ZONE), and respectively determining the pads and uses corresponding to the sub-areas. The way of dividing the sub-areas is to re-divide the pad group into smaller wire-wound pin areas according to a certain number of pads, for example, according to one sub-area corresponding to every three pads, so that the wire-wound pins in the sub-area are preferentially connected to the pads corresponding to the sub-area; by dividing the optional area into a plurality of sub-areas, the area of the optional device to be tested can be clearly divided, which facilitates the selection of the device to be tested and the more convenient wire winding of the device to be tested.

[0017] When the optional area is divided into a plurality of sub-areas, the lengths of the sub-areas in the first direction are all the same, and the width of the sub-area is the width of the optional area.

[0018] The test chip is a direct connection test chip on a chip, and the pads are arranged on the entire chip area.

[0019] Another aspect of the present application provides a test chip design method, comprising: step S1, reading a product chip layout, the layout comprising a front-end-of-line (FEOL) and a back-end-of-line (BEOL), and obtaining objects and object information in the layout based on graphical interpretation; step S2, creating a back-end-of-line of a test chip, comprising: arranging a plurality of pads on the product chip by using the pad arrangement method of the test chip; selecting a plurality of objects as target objects based on the objects and object information obtained in step S1; grabbing pins of the target objects; allocating pads to the pins of the target objects and realizing the connection between the pins of the target objects and the allocated pads by wire winding; and step S3, merging and connecting the front-end-of-line of the product chip layout and the back-end-of-line of the test chip created in step S2 to obtain the layout of the test chip. In the case of ensuring that the front-end-of-line and middle-end-of-line process layers of the product chip (i.e., the front-end-of-line FEOL of the product chip) remain unchanged, the layout of the test chip built-in in the product chip is obtained by modifying the connection layer and the back-end-of-line process layer (i.e., creating a new back-end-of-line BEOL) of the product chip. The test chip designed in this way is suitable for testing the key devices or hot spot patterns of the product chip in a real physical environment, and breaks through the limitation of not being able to effectively design a test chip with the same test structure as the physical environment faced by the devices or hot spot patterns in the product chip to optimize the test accuracy. The test chip design method provided in the product chip has great significance for improving the yield of chip products.

[0020] The graphical interpretation in the step S1 includes: using a preset feature pattern, identifying a corresponding object according to feature pattern matching, and using quantitative characterization object information; the object includes a device and a hotspot pattern, and the hotspot pattern is a structure pattern prone to process defects (such as photolithography process defects). By interpreting the layout of the product chip through the pattern, the object can be automatically and quickly identified and the target object can be extracted according to different test requirements by matching the preset feature pattern.

[0021] The object information in the step S1 refers to feature information that can affect the performance of the object, including information of the object feature pattern and environment information between the object feature pattern and its surrounding pattern. The environment information is, for example, relative distance information and the like.

[0022] The test chip design method also establishes an object database for storing the objects and object information obtained in the step S1; the object information includes: the name, position coordinates, and quantitative characterization feature information of the object.

[0023] In the step S2, the selected objects are screened as target objects, including: only screening the objects in the selectable area.

[0024] The test chip design method has a plurality of preset screening rules; in the step S2, the selected objects are screened as target objects, which also includes selecting suitable screening rules for different objects to screen the target objects.

[0025] As a preferred embodiment, the priority order of the selected screening rules is set according to the test requirements of the test chip, and the screening rules are applied in the priority order to screen the objects that meet the requirements as target objects.

[0026] The pin of the target object includes: a terminal of the target object, and a plurality of connection lines leading out the terminal; the plurality of connection lines leading out the terminal include connection lines with the same path as the connection lines in the product chip layout and / or newly created connection lines.

[0027] In the step S2, different pin-out directions (out pin directions) of different pins of the same target object are used for wire-out.

[0028] In the step S2, the pads are allocated to the pins, including: selecting the pad closest to the pin from a plurality of pads that meet the bendable linear principle for allocation. The bendable linear principle includes that the pad is bendable to the pin, and the overall bendable line of all pins.

[0029] The step S2 includes: recording two pad groups as a first pad group and a second pad group, respectively, which are alternately arranged in the pad sequence; recording an optional area on one side of the pad sequence as an odd area and an optional area on the other side of the pad sequence as an even area, wherein the odd area is the optional area of the first pad group, and the even area is the optional area of the second pad group; and assigning a pin of a target object located in the odd area of the pad sequence to a pad of the first pad group in the pad sequence, and assigning a pin of a target object located in the even area of the pad sequence to a pad of the second pad group in the pad sequence.

[0030] The product chip built-in test chip design method is provided with a plurality of winding rules; in the step S2, winding is performed according to different pins by selecting corresponding winding rules. Different pins include general pins, pins sensitive to voltage drop caused by current, and the like. In the step S2, the pins of the target object are directly connected to the pads, which is beneficial to the test chip to cover more test items and test conditions.

[0031] The step S2 further includes: deleting a back-end layer of the product chip.

[0032] After the step S3, the layout of the test chip obtained in the step S3 is verified, and the design of the test chip is completed if the verification is qualified.

[0033] The verification includes DRC verification and LVS verification; and the design of the test chip is completed if the verification is qualified. The DRC verification is used to check whether the design rules are met, the LVS verification is used to ensure that the connection of the back-end winding meets the requirements, and the test chip designed in this way can better meet the advanced customization requirements of monitoring the yield and performance of the product chip.

[0034] The test chip design system provided by the application includes a storage device; the storage device stores a plurality of instructions, and the instructions are suitable for being loaded and executed by a processor to implement the test chip design method. Users can conveniently and efficiently design the test chip built in the product chip according to different requirements in combination with the corresponding configuration of hardware and software.

[0035] The test chip provided by the application is a test chip built in a product chip and designed by using the test chip design method. Through the test chip, an enterprise can read the electrical parameters of a target object from an actual product chip, thereby changing the problem that the existing test chip will be different from the product chip as the process node continuously evolves, and helping the product chip to more accurately monitor the performance and locate the problem source, thereby promoting the enterprise to optimize the process and design and improving the quality of the product chip.

[0036] Compared with the prior art, the main beneficial effects of the present application are:

[0037] 1. The pad arrangement method of the test chip of the present application can maximize the reduction of the pad spacing in the pad sequence under the premise of avoiding probe short circuit through the staggered pad placement strategy, thereby discharging more optional areas in the entire chip; in the case of the same number of pads, the arranged pads not only occupy a smaller total area, but also increase the area of each optional area; in the case of continuing to support single-row independent testing or double-row parallel testing, more devices to be tested can be connected on the test chip, and the space for the selected device instances in each optional area is increased.

[0038] 2. The test chip design method built-in the product chip of the present application can automatically identify the target object and extract the target object according to different test requirements through graphical interpretation of the layout of the product chip; in the case of ensuring that the front and middle process layers of the product chip (i.e., the front-end-of-line (FEOL) layer of the product chip) remain unchanged, the layout of the test chip built-in the product chip is obtained by modifying the connection layer and the back-end-of-line (BEOL) layer of the product chip (i.e., creating a new BEOL layer), and the designed test chip is suitable for testing the key devices or hot spot patterns of the product chip in a real physical environment, thereby breaking through the limitation on optimizing test accuracy due to the different physical environments faced by the devices in the product chip and the test structures in the test chip, and having great significance for improving the yield of chip products. In addition, the pin direct connection pad of the target object is beneficial to the test chip covering more test items and test conditions.

[0039] 3. The test chip design system of the present application can conveniently and efficiently design the test chip built-in the product chip according to different requirements.

[0040] 4. The test chip built-in the product chip of the present application has corresponding advantages by being designed by the design method of the present application, can read the electrical parameters of the test object from the actual product chip, changes the problem that the existing test chip will be different from the product chip as the process node continuously evolves, can help the product chip to more accurately monitor performance and locate the problem source, adjust and optimize the design margin from the perspective of manufacturing process, and shorten the time from design to market (Design-to-Market) in the product life cycle, which is beneficial to the enterprise to quickly complete failure analysis (Failure Analysis) to continuously improve the product yield and performance indicators. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A pad schematic diagram is designed for a traditional pad arrangement.

[0042] Figure 2 A pad arrangement method process schematic diagram of embodiment one of the present application.

[0043] Figure 3 The schematic diagram of the staggered pad arrangement of the embodiment one of the present application.

[0044] Figure 4 The schematic diagram of the pin assignment of the staggered pad arrangement of the embodiment one of the present application.

[0045] Fig. 5(a) is the schematic diagram of the limit case of the pad arrangement of the area array type.

[0046] Fig. 5(b) is the schematic diagram of the limit case of the pad arrangement of the embodiment one of the present application.

[0047] Figure 6 The schematic diagram of the test chip design method of the embodiment two of the present application.

[0048] Fig. 7(a) is the layout schematic diagram of the product chip of the embodiment two of the present application.

[0049] Fig. 7(b) is the schematic diagram of the pad arrangement on the original product chip of the embodiment two of the present application.

[0050] Figure 8 The object information representation of the MOSFET stored in the object database of the embodiment two of the present application.

[0051] Figure 9 The object parameter schematic diagram of the MOSFET of the embodiment two of the present application.

[0052] Figure 10 The schematic diagram of the two pad group staggered arrangement process of the embodiment three of the present application.

[0053] Figure 11 The schematic diagram of the pad group and the optional area relationship of the embodiment three of the present application.

[0054] Figure 12 The target MOSFET information representation in the screening of the embodiment three of the present application.

[0055] Figure 13 The schematic diagram of the pin acquisition process of the target MOSFET in the embodiment three of the present application.

[0056] Figure 14 The schematic diagram of the pin to pad connection in the embodiment three of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.

[0058] The operations of the embodiments are described in the following examples in a specific order, and the description of the order is for better understanding of the details in the embodiments to fully understand the present application, but the description of the order does not necessarily correspond to the method of the present application, and cannot limit the scope of the present application.

[0059] Embodiment one

[0060] In the embodiment one of the present application, as shown in Figure 2 , a pad arrangement method of a test chip is provided, including: placing a plurality of pad groups on the test chip in a manner that two pad groups are placed in a staggered manner in a first direction, to form a plurality of pad sequences along the first direction; and determining optional areas of the pads in the pad sequences in regions on both sides of the pad sequences, to realize the layout of the optional areas of the pads, for connecting the pads to test object pins in the optional areas of the pads to form test paths. In the example, the pad group is a pad array, and the first direction is the row direction or the column direction of the pad array in the pad group. In this embodiment, the first direction is taken as the row direction, and the column direction is taken as the second direction for example, but is not limited thereto, the first direction and the second direction are orthogonal, and the first direction can also be the column direction. In the example, the test chip is a direct connection test chip on a chip, and the pads are placed on the entire chip area. In the example, the test chip is used to form test paths by contacting external probes through the pads, and it is ensured that the pads belonging to different pad groups in the pad sequences do not contact the probes at the same time, to ensure that there is enough spacing space between the probes to avoid miscontacting and short circuiting. In this embodiment, the pad spacing in the pad sequence can be reduced to the maximum extent under the premise of avoiding short circuiting of the probes.

[0061] In this embodiment, in the pad placement strategy of the staggered pads, as shown in Figure 3As shown, the white first pad group and the black second pad group are arranged into four pad sequences in a uniform and staggered manner. The first pad group and the second pad group of the example are both pad arrays, and the interval values of the adjacent pads in the row direction and the column direction in the pad group are preset values pitchX and pitchY, which satisfy: pitchX≥2×sizeX+2×space, pitchY≥2×sizeY+2×space. Wherein, sizeX and sizeY are the sizes of the pads in the row direction and the column direction, and space is a preset design rule distance; and it is required that pitchX of the first pad group and pitchX of the second pad group are equal, and pitchY of the first pad group and pitchY of the second pad group are equal. Generally, on a test chip, the pitchX of all pad groups is equal, and the pitchY of all pad groups is equal, but in the embodiment, it is not limited to that all non-staggered pad groups meet the requirement. In addition, because the pad sequences in the embodiment are uniformly and staggered arranged by the pads belonging to two pad groups, that is, the interval values of the adjacent pads in the first direction in the pad sequence are the same, and the interval values in the second direction are also the same. The second direction is the direction orthogonal to the first direction.

[0062] The optional area on one side of the pad sequence is recorded as an odd area, and the optional area on the other side is recorded as an even area; the odd area is the optional area of the first pad group, and the even area is the optional area of the second pad group. In the example, the pads in the pad sequence are counted in turn, and the pad group to which the pad with an odd order belongs is recorded as the first pad group, that is, the odd group (such as the white pad in Figure 3 The pad group to which the pad with an even order belongs is recorded as the second pad group, that is, the even group (such as the black pad in Figure 3 The interval between the pads in the odd group or the even group is the pad side length plus a few microns of design rule distance, which is obviously greater than the probe interval requirement, and can avoid probe short circuit.

[0063] In the embodiment, as shown in Figure 3 Two optional areas will be formed on both sides of each pad sequence, recorded as FRAME, and the number corresponds to the number of the pad sequence. The device pin in the optional area FRAME is connected to the pad in the odd group or the even group, which is distinguished by odd (odd area) and even (even area). For example, Frame-1-odd refers to the odd area on one side of the pad sequence 1, and Frame-2-even refers to the even area on one side of the pad sequence 2. As shown in Figure 4As shown, when the logic device within the optional region FRAME is taken as the test object, the pins that need to be connected out include the ports of the four poles of the transistor, i.e., the gate, the source, the drain and the body. Considering that the gate, the source and the drain of different devices in the group need to be controlled respectively under different test purposes, but the body pins can be shared as long as there is the same body voltage bias requirement between different devices, the pad arrangement method of the embodiment further includes: dividing the optional region into a plurality of sub-regions, and determining the pads and uses of the sub-regions respectively. In the example, one sub-region ZONE can be divided in each of the odd and even groups of pads in the corresponding optional region FRAME, and the length of the sub-region ZONE is 3 times the amplitude between the pads in the same group, the width is half the longitudinal distance between the different pad groups, and the number is the quotient of the number of pads in the same group divided by 3. One or more sub-regions ZONE in each optional region FRAME are used to connect the shared body, and the other sub-regions ZONE are used as optional regions of the devices to be tested.

[0064] In the example, the length of the optional region is the total length of the pads and the pad spacing regions in the first direction, and the width of the optional region is half the distance between the pad sequence and its adjacent pad sequence in the second direction.

[0065] Referring to FIGS. 5(a) and 5(b), the area utilization of the pad arrangement design of the area array method in the prior art and the pad arrangement method of the embodiment are compared. The calculation process of the occupied area in the extreme case is as follows: assuming that the pad group has 6n pads (n represents the number of sub-regions ZONE in the optional region FRAME on one side), each pad is a square with a side length of a microns, under the constraint of the probe group spacing, the minimum distance (lateral distance) pitch between the same group of testable pads is a microns, and the minimum distance (longitudinal distance) between the pads of different groups is also a microns when testing in parallel. Assuming that the design rule between the square metal patterns with a side length of a microns under the current process design rule satisfies the distance space of a fixed value of 3 microns. Assuming that all spaces are used to connect four-port logic devices and the body is shared, and there is only one sub-region ZONE in each of the optional regions FRAME on the upper and lower sides for connecting the shared body, the remaining n-1 sub-regions ZONE can be used as optional regions, and 2n-2 devices can be connected out.

[0066] As shown in FIG. 5(a), in the pad arrangement design of the area array method, a single pad group is divided into a 2x3n array, and the area of a single optional region is calculated as follows: WxL=0.5a x 6a=3a 2 The total occupied area of a single pad group is calculated as follows: HxD=4a x (6na-a)=(24n-4)a 2As shown in Fig. 5(b), in the pad arrangement method of the embodiment, the pads in a single group are arranged in a sequence of 1x6n, and the area of a single selectable region is calculated as follows: W'xL'=0.5a x (6a+15)=3a 2 +7.5a, and the total area is calculated as follows: H'xD'=2a x (6na+(6n-1) x 3)=12na 2 +36na-6a. It can be obtained that the ratio of the area of a single selectable region in the pad arrangement method of the embodiment to the area of a single selectable region in the pad arrangement design of the area array type is Ratio1= ; and the ratio of the total area in the pad arrangement method of the embodiment to the total area in the pad arrangement design of the area array type is Ratio2= The value of the pad side length a is much larger than 3 microns, and n is a positive integer greater than 2, so Ratio1 is always less than 1, i.e., the area of a single selectable region in a single pad group in the pad arrangement design of the area array type is smaller than the area of a single selectable region in the pad arrangement method of the embodiment; Ratio2 is always greater than 1 and close to 2, i.e., a single pad group in the pad arrangement design of the area array type needs to occupy an area close to twice the area occupied by the pad sequence in the pad arrangement method of the embodiment.

[0067] In summary, under the condition that the total number of pads is the same and the pin sharing mode is the same, the pad arrangement method of the test chip of the embodiment not only makes the total area occupied by the pads smaller, but also increases the area of each selectable region. In the case of continuing to support single-row independent testing or double-row parallel testing, more devices to be tested can be connected out on the chip, and the space for the selected device instances in each selectable region is increased.

[0068] Embodiment Two

[0069] The test chip design system provided in the embodiment of the application includes a storage device. The storage device stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the test chip design method built in a product chip of the embodiment. The process of the test chip design method built in the product chip provided in the embodiment is as follows Figure 6As shown, it comprises: step S1. Reading the layout of the product chip, which comprises the front-end layer and the back-end layer, and obtaining the objects and object information in the layout based on the graphical interpretation. Step S2. Creating the back-end layer of the test chip, comprising: arranging a plurality of pads on the product chip by using the pad arrangement method of the test chip in Embodiment One; selecting a plurality of objects as target objects based on the objects and object information obtained in step S1; grabbing the pins of the target objects; assigning pads to the pins of the target objects and realizing the connection between the pins of the target objects and their assigned pads by routing. Step S3. Merging and connecting the front-end layer of the product chip and the back-end layer of the test chip created in step S2 to obtain the layout of the test chip. In step S1 of the embodiment, the graphical interpretation comprises: using a pre-set feature pattern to identify the corresponding object according to the feature pattern matching, and using quantitative characterization to represent the corresponding object information; the objects include devices and hotspot patterns. The hotspot pattern is a structure pattern prone to process defects (such as photolithography process defects), which in the example includes connection line structures, active areas (AA), single diffusion breaks (SDB, single diffusion break). The example devices can include MOSFETs (metal oxide semiconductor field effect transistors), diodes, BJTs (bipolar junction transistors), resistors, capacitors, inductors, SRAMs (static random access memories). In this embodiment, the product chip as shown in Figure 7(a) is the original product chip, and the case after arranging pads on the original product chip is shown in Figure 7(b).

[0070] In the example of step S1, the object information refers to the characteristic information that can affect the performance of the object, including the information of the object feature pattern and the environmental information between the object feature pattern and its surrounding patterns. The environmental information is, for example, relative distance information, etc. In this embodiment, an object database is also established to store the objects and object information obtained in step S1. As shown in Figure 8 The object information as shown comprises: the name and position coordinates of the object, and the characteristic information of each quantitative characterization.

[0071] The following provides a specific example of the identification and object information acquisition of MOSFET as an example object. According to the type of MOSFET, two kinds of feature patterns are pre-set for identifying MOSFET. They are:

[0072] N-type MOSFET: N-type gate (ngate) on both sides respectively edge contacts N-type source and drain (nsd), and P-type body (ptap) in the non-NWELL region.

[0073] P-type MOSFET: P-type gate (pgate) on both sides respectively edge contacts P-type source and drain (psd), and N-type body (ntap) in the NWELL region.

[0074] Wherein, the MOSFET device related graph definition examples involved in the above characteristic graph are as follows. N-type active region: ndiff = ((AA and NIMP) not PIMP) not NWELL; P-type active region: pdiff = ((AA and PIMP) not NIMP) and NWELL; N-type gate: ngate = (POLY not EG) and ndiff; P-type gate: pgate = (POLY not EG) and pdiff; N-type source, drain: nsd = ndiff not POLY; P-type source, drain: psd = pdiff not POLY; N-type body: ntap = ((AA and NIMP) not PIMP) and NWELL; P-type body: ptap = ((AA and PIMP) not NIMP) not NWELL. The corresponding examples of the basic graph definition involved in the above characteristic graph are as follows: POLY is a polysilicon layer; POLYCUT is a polysilicon deletion layer; EG is an edge gate identification layer; AA is an active layer; NIMP is an N-type injection layer; PIMP is a P-type injection layer; NWELL is an N-well layer; PSUB is a P-substrate; IOMK is a thick device identification layer.

[0075] In the embodiment, the defined MOSFET intrinsic characteristic parameters and surrounding environment parameters can refer to Figure 9 , examples include L, W, DPL11, DPL12, SA, SB, PEEU, etc., which are not limited in specific cases here.

[0076] Embodiment three

[0077] The embodiment expands examples of some specific practices in step S2, which facilitates the professional technical personnel in the art to more fully understand the present application, but does not limit the present application in any way.

[0078] In the embodiment, the pad arrangement method of the test chip in embodiment one is used to arrange a plurality of pads on the product chip, which specifically includes: setting a pad group, the pad group is a pad array, the preset interval values of the adjacent pads in the pad group in the row direction and the column direction are respectively denoted as pitchX and pitchY; arranging a plurality of pad groups on the product chip, and placing the pads of the adjacent two pad groups in the row direction or the column direction in a staggered manner. The preset values of the design size of the pads in the row direction and the column direction are respectively denoted as sizeX and sizeY. Specifically as Figure 10As shown, the set pads are arranged as a pad array with 48x2 pads, and the pads of every two pad sets are interleaved in the Y direction. The product chip has an area of about 9mmx9mm, and about 232 pad sets can be arranged in the area, and the total number of pads is 22272, and the number of repeated rows of pad sets in the Y direction is four, and the number of repeated columns of pad sets in the X direction is fifty-eight. The row direction and the column direction can be the X and Y directions respectively or the Y and X directions respectively. Figure 10 The specific arrangement of the rows and the columns is merely illustrative and is not limited in this way.

[0079] In step S2, the embodiment screens a plurality of objects as target objects, including screening only the objects in the optional area. The optional area is the area on both sides of the interleaved pad sequence of the pads of the two adjacent pad sets, that is, the area on both sides of the pad sequence arranged along the Y direction in each column of the example. The optional area can refer to the DeviceArea in Figure 11 Figure 11 Pad group in the above table 1 represents the pad set.

[0080] The screening in the example is implemented by using a preset screening rule. The screening of a plurality of objects as target objects also includes selecting a suitable screening rule for different objects for screening. A plurality of screening rules are selected according to different objects for screening to obtain target objects. In the example, the priority order of the selected screening rules is set according to the actual application requirements of the test chip, and then the screening rules are applied in the priority order to screen a plurality of objects that meet the requirements as target objects. The example has more than 30 different screening rules, covering MOSFET, BJT, DIODE, resistor, capacitor, SRAM, hotspot, etc. The following will take one screening rule of MOSFET as an example: In the DEVICETYPE, various different types of MOSFET, according to the minimum value and the maximum value of the basic parameters W and L, the target devices that meet the requirements are selected respectively. The target devices screened in the screening rule of the example are interested in the W and L range of various MOSFETs in the product chip, that is, the minimum value and the maximum value at both ends of the range, which are used to monitor the process window. The selected target device parameters can refer to the following table 1.

[0081] Table 1. Selected target device parameter table

[0082]

[0083] In the general operation of the embodiment, three sample devices are randomly selected from the selected devices that meet the screening rule and are sufficient in number, and if the number of selected devices that meet the screening rule is less than three, all of them are selected first. The screening rule selects a total of, for example, Figure 12 ​The twenty target devices shown.

[0084] In step S2 of this embodiment, the pins of the target object include: terminals of the target object, and several connecting lines leading out from the terminals. For example... Figure 13 As shown, the example automatically identifies and captures the four terminals of the MOSFET: gate, source, drain, and body. Metal leads for these four terminals are then created, and processing is performed to conform to design rules, optimizing the pin routing directions to ensure the four pins exit from four different directions, making subsequent wiring steps easier. Because the actual location of the body is relatively far, [the following steps are not explicitly stated]. Figure 13 The image only shows the automatic identification and capture results of the gate, source, and drain terminals, retaining only the back-end layer. In some cases, the connection lines leading out from the terminals include connection lines with the same path as the connection lines in the original product chip layout and / or newly created connection lines. Generally, connection lines with the same path as the connection lines in the original product chip layout are used as much as possible, but this is not a limitation here.

[0085] In this embodiment, assigning pads to the pins of a target object includes: designating adjacent pad groups arranged in an alternating pattern to form a pad sequence as a first pad group and a second pad group, respectively; designating a selectable area on one side of the pad sequence as an odd-numbered area and a selectable area on the other side as an even-numbered area; the odd-numbered area is the selectable area of ​​the first pad group, and the even-numbered area is the selectable area of ​​the second pad group; assigning the pins of the target object located in the odd-numbered area of ​​the pad sequence to the pads of the first pad group, and assigning the pins of the target object located in the even-numbered area of ​​the pad sequence to the pads of the second pad group. For the selectable areas, refer to... Figure 10 and Figure 11 , Figure 10 Two pad groups are set up alternately in the Y direction (i.e., the column direction, the first direction is the column direction), namely the first pad group PadGroupⅠ and the second pad group Pad GroupⅡ. The optional area on the left side of the pad sequence arranged along the Y direction is set as the left optional area Device Area of ​​Pad GroupⅠ, and the optional area on the right side of the pad sequence arranged along the Y direction is set as the right optional area Device Area of ​​Pad GroupⅡ. When assigning pads, the pads belonging to the first pad group Pad GroupⅠ are assigned to the pins of the target object in the left optional area Device Area of ​​Pad GroupⅠ of the pad sequence in which the pad belongs, and the pads belonging to the second pad group Pad GroupⅡ are assigned to the pins of the target object in the right optional area Device Area of ​​Pad GroupⅡ of the pad sequence in which the pad belongs.

[0086] In step S2, the pads are assigned to the pins in the embodiment include selecting the pad closest to the pin from the pads that comply with the winding around linear principle. That is, when assigning the pads to the pins of the target object, the following principles are followed: 1) the principle of assigning in proximity and winding around linear, where the winding around linear principle includes the winding around linear of the pad for the pin and the overall winding around linear of all the pins; and 2) only assigning the pads to the pins of the target object within the optional area of the pads.

[0087] In the embodiment, a plurality of winding rules are preset. In step S2, the winding is performed according to the corresponding winding rule selected according to the different pins. When winding the pins of the target object to the assigned pads, the corresponding winding rule is automatically selected according to the different pins (such as general pins, pins sensitive to the voltage drop caused by current, etc.) to automatically wind.

[0088] In the embodiment, the pads are assigned to the pins of the target object in the following manner: Figure 13 The four pins of the target device MOSFET, i.e., the gate, source, drain, and body, are automatically wound. The body will share the bottom pad with other devices of the same type, and the remaining three pins will be assigned to the pads according to the winding around linear principle and the principle of proximity. As shown in the pad assignment shown in the following table: Figure 14 The pad assignment is as follows: the gate G is assigned to PAD_92; the drain D is assigned to PAD_94; the source S is assigned to PAD_96; and the body B is assigned to PAD_2 (bottom shared pad). The MOSFET is within the optional area of the pad group to which PAD_92, PAD_94, and PAD_96 belong. When winding, the gate G and the body B use single winding, and the drain D and the source S use large-area mesh winding to reduce the IR drop.

[0089] In the embodiment, step S2 further includes deleting the back-end layers (conductive interconnection layers) of the product chip. After step S3, the test chip is verified, for example, by DRC to verify whether it complies with the design rules, and by LVS to ensure that the connection of the back-end winding meets the requirements. If the verification is passed, the design of the test chip built-in in the product chip is completed, and a high-precision built-in test chip for monitoring the yield and performance of the product chip is obtained. In the embodiment, the test chip is provided, and about 6200 target objects are selected under the area of the product chip in the embodiment, and the measurement pins of the target objects are directly connected to the adjacent pads. In this way, the area utilization rate is improved, and more test items and test conditions can be covered through the direct connection of the pins to the pads.

[0090] Some commonly used English terms or letters used in the present application for the purpose of clear description are only used for exemplary reference and are not limited to the interpretation or specific usage, and the protection scope of the present application should not be limited by the possible Chinese translation or specific letters.

[0091] It should also be noted that the relational terms herein, such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0092] The above has carried on the detailed introduction to the present application, the structure and working principle of the present application are set forth by applying the specific example in the text, the above embodiment explanation is only for helping to understand the method and core idea of the present application. It should be pointed out that for the ordinary skilled person in the art, without departing from the principle of the present application, the present application can be improved and modified, these improvements and modifications also fall within the scope of the present application claimed.

Claims

1. A method of testing a pad arrangement of a chip, the method comprising: The application relates to a test chip and a test method thereof. A plurality of pad groups are arranged on the test chip in a manner that the pad groups are arranged in an interval staggered manner in a first direction, so as to form a plurality of pad sequences along the first direction; ​ On both sides of the pad sequence, optional regions of the pads in the pad sequence are determined respectively, which are used for connecting test object pins in the optional regions to form test paths; The pad group is a pad array, and the interval values of the adjacent pads in the pad group in the row direction and the column direction are preset values pitchX and pitchY, and the following conditions are met: pitchX >= 2* sizeX + 2* space; pitchY >= 2* sizeY + 2* space; The sizeX and the sizeY are the sizes of the pads in the row direction and the column direction respectively, the space is a preset design rule meeting distance, the first direction refers to the row direction or the column direction of the pad array in the pad group, the pad sequence is formed by the interval staggered arrangement of the pads belonging to two pad groups, the two pad groups are respectively referred to as a first pad group and a second pad group, the optional region on one side of the pad sequence is referred to as an odd region, and the optional region on the other side is referred to as an even region, the odd region is the optional region of the first pad group, and the even region is the optional region of the second pad group; The optional region is divided into a plurality of sub-regions, and the corresponding pads and uses of the sub-regions are determined respectively, wherein every three adjacent pads in the odd region and the even region are divided into a sub-region, one or more sub-regions in each optional region are used for connecting common body poles, and the other sub-regions are used as optional regions of the devices to be tested, the length of the optional region is the total length of the pads and the interval regions of the pads in the pad sequence in the first direction, and the width of the optional region is half of the interval of the pad sequence and the adjacent pad sequence in the second direction, the second direction is perpendicular to the first direction; The test chip is used for forming test paths by contacting external probes through the pads, and the pads belonging to different pad groups in the pad sequence do not contact the probes at the same time.

2. The test chip pad arrangement method of claim 1, wherein: The pitchX of the first pad group is equal to the pitchX of the second pad group, and the pitchY of the first pad group is equal to the pitchY of the second pad group.

3. The test chip pad arrangement method of claim 1, wherein: The pad sequence is formed by the uniform interval staggered arrangement of the pads belonging to the two pad groups, that is, the interval values of the adjacent pads in the pad sequence in the first direction are the same, and the interval values of the adjacent pads in the second direction are also the same.

4. The test chip pad arrangement method of claim 1, wherein: The length of the optional region is the length of the pad sequence in the first direction, and the width of the optional region is not greater than half of the interval of the pad sequence and the adjacent pad sequence in the second direction; the second direction is perpendicular to the first direction.

5. The test chip pad arrangement method of claim 1, wherein: When the optional region is divided into a plurality of sub-regions, the lengths of the sub-regions in the first direction are the same, and the width of the sub-region is the width of the optional region.

6. The test chip pad arrangement method according to any one of claims 1 to 5, wherein: The test chip is a direct connection test chip on a chip, and the pads are arranged on the whole chip area.

7. A method of testing a chip design, characterized by: The application relates to a test chip and a test method thereof. Step S1. Reading a layout of a product chip, the layout including a front-end layer and a back-end layer, obtaining objects and object information in the layout based on graphic interpretation; The graphic interpretation includes: using a preset feature pattern, identifying a corresponding object according to feature pattern matching, and quantitatively representing object information; the object includes a device and a hotspot pattern, and the hotspot pattern is a structure pattern prone to process defects; Step S2. Creating a back-end layer of a test chip, including: arranging a plurality of pads on the product chip using the pad arrangement method of any one of claims 1-6; selecting a plurality of objects as target objects based on the objects and object information obtained in step S1; grabbing pins of the target objects; assigning pads to the pins of the target objects and routing to connect the pins of the target objects to their assigned pads; Step S3. Merging and connecting the front-end layer of the product chip layout and the back-end layer of the test chip created in step S2 to obtain the layout of the test chip.

8. The test chip design method of claim 7, wherein: In step S1, the object information refers to characteristic information that can affect the performance of the object, including information of the object feature pattern and environmental information between the object feature pattern and its surrounding patterns.

9. The test chip design method of any of claims 7-8, wherein: An object database is also established to store the objects and object information obtained in step S1; the object information includes the name, position coordinates of the object, and quantitatively represented characteristic information.

10. The test chip design method of claim 7, wherein: In step S2, selecting a plurality of objects as target objects includes only selecting objects in the selectable area.

11. The test chip design method of claim 7, wherein: A plurality of screening rules are preset; in step S2, selecting a plurality of objects as target objects also includes selecting applicable screening rules for different objects to obtain target objects.

12. The test chip design method of claim 7, wherein: The pins of the target objects include terminals of the target objects and a plurality of connection lines leading to the terminals; the plurality of connection lines leading to the terminals include connection lines with the same path as the connection lines in the product chip layout and / or newly created connection lines.

13. The test chip design method of claim 7, wherein: In step S2, assigning the pads to the pins includes selecting the pad closest to the pin from a plurality of pads that meet the routability principle for assignment.

14. The test chip design method of claim 7, wherein: A plurality of routing rules are preset; in step S2, routing is performed according to corresponding routing rules selected for different pins.

15. The test chip design method of claim 7, wherein: After step S3, the layout of the test chip obtained in step S3 is also verified, and the design of the test chip is completed if the verification is qualified.

16. A test chip design system characterized by: A storage device is included; the storage device stores a plurality of instructions, and the instructions are suitable for being loaded and executed by a processor to perform the test chip design method of any one of claims 7-15.

17. A test chip, characterized by: Designed using the test chip design method of any one of claims 7-15.

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