Power management circuit and timing controller for a display device

Abstract

This embodiment relates to power management circuitry and a timing controller for a display device. The power management circuitry optimizes power consumption by receiving analysis information from the timing controller, which is capable of analyzing image data, and changing operating conditions of the power conversion circuitry based on the analysis information.

Description

TECHNICAL FIELD

[0001] This embodiment relates to power management circuit and timing controller technologies for display devices. BACKGROUND

[0002] A display device includes a power management circuit. The power management circuit is also referred to as a power management integrated circuit (abbreviated as PMIC).

[0003] The power management circuit mainly performs a function of converting system power supplied from a commercial power source or a battery based on characteristics of components included in the display device, and supplying the converted system power. For example, if a voltage of the system power and an operating voltage of the components are different, the power management circuit converts the voltage of the system power and supplies the converted voltage to the components.

[0004] The power conversion process can undergo power loss. In recent years, with the advent of low-power driving, various attempts have been made to minimize such power loss. SUMMARY

[0005] Various embodiments aim to provide a technology for optimizing power consumption in a display device.

[0006] In an aspect, embodiments provide a power management circuit including a switch driving circuit configured to drive at least one power switch, and a control circuit configured to receive a control signal from a timing controller and change a driving condition of the switch driving circuit in response to the control signal.

[0007] The panel can be a liquid crystal display (LCD) panel. The control circuit can control a bias current of an amplifier configured to supply a voltage to a common electrode of the panel in response to the control signal.

[0008] The control signal can include information about a size of a change in image data between frames. The control circuit can control the amplifier such that the bias current increases as the size of the change increases.

[0009] In another aspect, embodiments provide a timing controller including a load analysis circuit configured to analyze image data of respective frames and calculate panel loads of the respective frames, and a communication circuit configured to generate a control signal corresponding to a size of the panel loads and transmit the control signal to a power management circuit.

[0010] The communication circuit can transmit the control signal in units of frames.

[0011] As described above, according to the present embodiment, power consumption in a display device can be optimized. Attached Figure Description

[0012] Figure 1 This is a configuration diagram of a display device according to an embodiment.

[0013] Figure 2 This is a configuration diagram of the timing controller according to an embodiment.

[0014] Figure 3 This is a configuration diagram of the power conversion circuit and the power management circuit according to an embodiment.

[0015] Figure 4 This is a graph illustrating the efficiency curves of a power conversion circuit based on driving conditions.

[0016] Figure 5 This is a configuration diagram of a switching circuit according to a first example of an embodiment.

[0017] Figure 6 This is a configuration diagram of a switching circuit according to a second example of an embodiment.

[0018] Figure 7 This is a configuration diagram of a power management circuit according to another embodiment.

[0019] Figure 8 This is a diagram illustrating the function flow for each frame. Detailed Implementation

[0020] Figure 1 This is a configuration diagram of the display device 100 according to an embodiment.

[0021] refer to Figure 1 The display device 100 may include a display panel 140, a host 160, a timing controller 120, a source driver 130, a gate driver 150, a power management circuit 110, etc.

[0022] Multiple pixels P can be arranged in the display panel 140. The multiple pixels P can be connected to the source driver 130 via data lines and to the gate driver 150 via scan lines.

[0023] Pixel P can be formed using a liquid crystal type, or it can be formed using a light-emitting diode (LED) type or an organic light-emitting diode (OLED) type. In the following description, for ease of explanation, an example of pixel P being formed using a liquid crystal type will be described.

[0024] Pixel electrodes can be arranged in pixels P. Furthermore, the brightness of each pixel P can be determined based on the magnitude of the voltage formed between the pixel electrodes and the common electrode CE.

[0025] The gate driver 150 can supply a scan signal SCN to a scan line. In a case where the scan signal SCN is supplied to the scan line, the corresponding pixel P can be connected to a data line. A data voltage VD supplied to the corresponding data line can be supplied to the pixel P, more accurately, to the pixel electrode.

[0026] A plurality of scan lines can be arranged in the display panel 140. The gate driver 150 can supply the scan signal SCN to the plurality of scan lines in sequence in response to a scan clock GCLK.

[0027] The gate driver 150 can receive the scan clock GCLK and a gate control signal GCS from the timing controller 120. Also, the gate driver 150 can generate the scan signal SCN in response to the scan clock GCLK and the gate control signal GCS.

[0028] The scan signal SCN can include a gate high voltage VGH and a gate low voltage VGL. The gate high voltage VGH and the gate low voltage VGL can be supplied to the gate driver 150 from the power management circuit 110.

[0029] In a case where the pixel P is connected to the data line in response to the scan signal SCN, the source driver 130 can supply the data voltage VD to the data line. Also, the brightness of the pixel P can be adjusted based on the magnitude of the data voltage VD.

[0030] The source driver 130 can receive the image data RGB and a data control signal DCS from the timing controller 120, can generate the data voltage VD in response to the image data RGB and the data control signal DCS, and can supply the data voltage VD to the pixel P.

[0031] The image data RGB can include a grayscale value of each pixel P. The source driver 130 can check the grayscale value of each pixel P based on the image data RGB, can generate the data voltage VD corresponding to the grayscale value, and can supply the data voltage VD to each pixel P. In this case, the timing at which the data voltage VD is supplied to each pixel P can be determined by the data control signal DCS.

[0032] Since the grayscale value of each pixel P included in the image data RGB is a digital value, the source driver 130 can include a digital-to-analog converter (DAC) for converting the digital value into an analog voltage and an output buffer for amplifying the analog voltage.

[0033] The power management circuit 110 can supply the gamma voltage GMA to the DAC and supply the driving voltage AVDD to the output buffer. Also, the source driver 130 can convert a digital value into an analog voltage by using the gamma voltage GMA and can amplify the analog voltage into a data voltage VD by using the driving voltage AVDD.

[0034] The power amount for amplifying the data voltage VD can be greatly affected by the pattern of the image data RGB. For example, if the image data RGB in the previous frame and the current frame are identical to each other, the power amount for amplifying the data voltage VD can be small. In general, the power for outputting the data voltage VD is used to store a parasitic capacitance formed in the display panel 140. If the image data RGB in the previous frame and the current frame are identical to each other, since there is no need to store or discharge the parasitic capacitance, the power amount for amplifying the data voltage VD can be small. In contrast, if there is a great difference between the grayscale values of each pixel P in the image data RGB in the previous frame and the current frame, since the power required to store or discharge the parasitic capacitance also increases, the power amount for amplifying the data voltage VD also increases.

[0035] The power used in driving the pixel P along with the storage and discharge of the parasitic capacitance can be referred to as a panel load.

[0036] The timing controller 120 can analyze the pattern of the image data RGB and calculate the size of the panel load. For example, if the pattern of the image data RGB is dynamic, the timing controller 120 can determine that the size of the panel load is large. Also, if the pattern of the image data RGB represents a still image, the timing controller 120 can determine that the size of the panel load is small.

[0037] The timing controller 120 converts the original image data RGB' supplied by the host 160 into a form that the source driver 130 can understand. In addition to this conversion, the timing controller 120 can analyze the pattern of the image data RGB and calculate the size of the panel load.

[0038] The timing controller 120 can quantitatively calculate the size of the panel load. Also, the timing controller 120 can discretely calculate the size of the panel load. For example, the timing controller 120 can divide the size of the panel load into three levels. If the pattern of the image data RGB dynamically changes like a moving image, the timing controller 120 can determine the size of the panel load as a maximum level. Also, if the pattern of the image data RGB has a static form like a photograph, the timing controller 120 can determine the size of the panel load as a minimum level. Also, the timing controller 120 can determine the pattern of the image data RGB between the two levels as an intermediate level.

[0039] The timing controller 120 can generate a power control signal PCS based on the size of the panel load, and can transmit the power control signal PCS to the power management circuit 110.

[0040] Further, the power management circuit 110 can control the driving conditions of the power conversion circuit in different ways in response to the power control signal PCS.

[0041] For example, the power management circuit 110 can control the switching frequency of the power conversion circuit in different ways in response to the power control signal PCS. Alternatively, if the power conversion circuit includes a plurality of power switches connected in parallel, the power management circuit 110 can control the number of power switches driven in different ways in response to the power control signal PCS.

[0042] For another example, the power management circuit 110 can supply a common voltage VCOM to the common electrode CE by using an amplifier. The power management circuit 110 can control the bias current of the amplifier in different ways in response to the power control signal PCS.

[0043] As described above, if the power management circuit 110 changes the driving conditions of the power conversion circuit in response to the power control signal PCS, power consumption can be reduced. The power management circuit 110 can have different efficiencies according to the size of the panel load and the driving conditions. The power management circuit 110 according to an embodiment can operate at an optimal driving condition suitable for the size of the panel load by changing the driving conditions based on the size of the panel load.

[0044] If the size of the panel load is not considered, a user can randomly change the driving conditions of the power management circuit 110. For example, the host 160 can recognize a user manipulation and transmit option information OPT based on the user manipulation to the timing controller 120. Further, the timing controller 120 can recognize the driving conditions included in the option information OPT, can generate a power control signal PCS based on the driving conditions, and can transmit the power control signal PCS to the power management circuit 110. Further, the power management circuit 110 can change the driving conditions in response to the power control signal PCS.

[0045] Figure 2 is a configuration diagram of a timing controller according to an embodiment.

[0046] Referring to Figure 2 , the timing controller 120 can include a communication circuit 210, a memory 220, a load analysis circuit 230, etc.

[0047] The communication circuit 210 can receive raw image data RGB' and option information OPT from a host.

[0048] The original image data RGB' is converted into image data RGB in a form that the source driver can understand. The timing controller 120 can also include conversion circuitry (not illustrated) for such conversion.

[0049] Further, the communication circuitry 210 can transmit the image data RGB to the source driver. Further, the communication circuitry 210 can transmit the data control signal DCS to the source driver and transmit the power control signal PCS to the power management circuitry.

[0050] The image data RGB can be stored in the memory 220 in units of frames.

[0051] Further, the load analysis circuitry 230 can analyze the image data RGB of each frame and calculate the panel load PL of each frame. Further, the load analysis circuitry 230 can store the panel load PL in the memory 220.

[0052] The communication circuitry 210 can generate the power control signal PCS in a manner corresponding to the size of the panel load PL and can transmit the generated power control signal PCS to the power management circuitry.

[0053] The communication circuitry 210 can transmit the power control signal PCS to the power management circuitry through a single line. If the timing controller 120 and the power management circuitry share a ground terminal, the timing controller 120 can perform serial communication through the single line. The communication circuitry 210 can transmit the power control signal PCS through such serial communication.

[0054] The communication circuitry 210 can receive option information OPT from the host. The option information OPT can include mode information. The communication circuitry 210 can generate the power control signal PCS by further using the mode information. The mode information, which is information indicating a power saving mode, can include data divided into a normal mode, a power saving mode, an ultra power saving mode, and the like.

[0055] The load analysis circuitry 230 can calculate the size of the panel load PL in units of frames. The communication circuitry 210 can transmit the power control signal PCS in units of frames based on the size of the panel load PL.

[0056] The load analysis circuitry 230 can calculate the size of the panel load PL based on the size of the change in the image data RGB between frames.

[0057] The power management circuitry can receive the power control signal PCS and change a driving condition in response to the power control signal PCS.

[0058] Figure 3is a configuration diagram of a power conversion circuit and a power management circuit according to an embodiment.

[0059] Referring to Figure 3 , the power conversion circuit 10 can include an inductor L, a capacitor Co, at least one power switch SW, and a diode D. In addition, the power management circuit 110 can include a switching circuit 330, a switching driving circuit 310, and a control circuit 320.

[0060] The at least one power switch SW can be classified as included in the power management circuit 110, or can be classified as included in the power conversion circuit 10. In Figure 3 , although the at least one power switch SW has been exemplified as included in the power management circuit 110, it can also be understood as one element of the power conversion circuit 10.

[0061] Figure 3 An example in which the power conversion circuit 10 has been implemented in the form of a buck converter is exemplified, but the power conversion circuit 10 can also be implemented in another form including a boost converter. For ease of description, examples in which the power conversion circuit 10 has the form of a buck converter are described below.

[0062] In the power management circuit 110, the at least one power switch SW can be connected to the first node N1 of the power conversion circuit 10 through a switching terminal TSW. In this case, the first node N1 can be a node to which the inductor L and the diode D are connected.

[0063] In the case where the at least one power switch SW is turned on, energy is stored in the inductor L due to a voltage difference between both ends of the inductor L. In addition, in the case where the at least one power switch SW is turned off, the energy stored as described above is transmitted to the capacitor Co through the diode D. As such processing is periodically repeated, the input voltage VIN is converted into the output voltage VO.

[0064] The switching driving circuit 310 can operate the power conversion circuit by driving the at least one power switch SW. The switching driving circuit 310 can generate a gate signal VGA, and can transmit the gate signal VGA to a gate terminal of the at least one power switch SW. According to an embodiment, the diode D can also be replaced with a power switch. In this case, the power switch can be supplied with a gate inverse signal VGB.

[0065] The switching driving circuit 310 can sense a feedback voltage VFB corresponding to the output voltage VO through a feedback resistor Rfb included in the power conversion circuit 10. In addition, the switching driving circuit 310 can drive the at least one power switch SW in response to the feedback voltage VFB.

[0066] The switch driving circuit 310 can sense the current ISW flowing into the at least one power switch SW through the current sensor Rsw connected in series with the at least one power switch SW, and can drive the at least one power switch SW in response to the current ISW.

[0067] The control circuit 320 can receive the power control signal PCS from the timing controller. Also, the control circuit 320 can change a driving condition of the switch driving circuit 310 in response to the power control signal PCS.

[0068] In this case, the driving condition can refer to a condition that affects driving of the at least one power switch SW. For example, a switching frequency of the at least one power switch SW can correspond to one driving condition. For another example, if the at least one power switch SW includes a plurality of power switches, the number of the power switches driven among the plurality of power switches can correspond to another driving condition.

[0069] The control circuit 320 can receive the power control signal PCS from the timing controller, and can adjust a switching frequency of the at least one power switch SW in response to the power control signal PCS. Alternatively, the control circuit 320 can receive the power control signal PCS from the timing controller, and can adjust the number of the power switches driven in response to the power control signal PCS.

[0070] Figure 4 is a graph illustrating efficiency curves of a power conversion circuit according to driving conditions.

[0071] Generally, a driving condition of a power conversion circuit is fixed. Generally, a conventional power conversion circuit is characterized by having similar (power conversion) efficiency over the entire power consumption region, and having high efficiency in the middle power consumption region, as in the first efficiency curve 410.

[0072] On the contrary, according to the driving condition, the power conversion circuit can have high efficiency in the low power consumption region as in the second efficiency curve 422, have high efficiency in the middle power consumption region as in the third efficiency curve 424, and have high efficiency in the high power consumption region as in the fourth efficiency curve 426.

[0073] The power management circuit according to the embodiment can receive a power control signal including information about the size of the panel load from the timing controller. Further, the power management circuit can drive the power conversion circuit in a first driving condition based on the size of the panel load, in which a second efficiency curve 422 is formed in a low power consumption region. Further, the power management circuit can drive the power conversion circuit in a second driving condition based on the size of the panel load, in which a third efficiency curve 424 is formed in an intermediate power consumption region. Further, the power management circuit can drive the power conversion circuit in a third driving condition based on the size of the panel load, in which a fourth efficiency curve 426 is formed in a high power consumption region.

[0074] In this way, by changing the driving condition of the power conversion circuit based on the size of the panel load, the power management circuit can obtain a fifth efficiency curve 420 for the power conversion circuit, which has high efficiency over the entire power consumption region.

[0075] Figure 5 is a configuration diagram of a switching circuit according to a first example of the embodiment.

[0076] Referring to Figure 5 , the switching circuit 330a can include a plurality of power switches SWa to SWn constituting the power conversion circuit. In this case, the plurality of power switches SWa to SWn can be interconnected in parallel.

[0077] Further, the control circuit of the power management circuit can control the number of power switches driven among the plurality of power switches SWa to SWn differently in response to the power control signal.

[0078] For example, as the size of the panel load decreases, the control circuit can decrease the number of power switches driven. Further, as the size of the panel load increases, the control circuit can increase the number of power switches driven.

[0079] Generally, a capacitance can be formed between the drain and the source of each of the power switches SWa to SWn. Further, in the on and off processing of the power switches SWa to SWn, a phenomenon in which charges are stored in the capacitance and discharged from the capacitance can occur. Power loss can occur due to this phenomenon. Such loss is also referred to as switching loss.

[0080] In the case where the size of the panel load is small, the control circuit can decrease the number of power switches driven to reduce such switching loss.

[0081] In a state in which each of the power switches has been turned on, a resistance can be formed between the drain and the source of each of the power switches SWa to SWn. In addition, due to such a resistance, a turn-on resistance loss can occur.

[0082] The turn-on resistance loss increases when a large current flows. In a case in which the size of the panel load is large, the control circuit can increase the number of the power switches to be driven to reduce such a turn-on resistance loss.

[0083] Figure 6 is a configuration diagram of a switching circuit according to a second example of an embodiment.

[0084] Reference Figure 6 , the switching circuit 330b can include a first power switch SW1 and a second power switch SW2 that constitute a power conversion circuit.

[0085] The first power switch SW1 and the second power switch SW2 can be interconnected in parallel.

[0086] In addition, the size of the second power switch can be larger than the size of the first power switch. From another perspective, the channel width of the second power switch can be wider than the channel width of the first power switch. When the channel width of the power switch increases, the power switch can have a low turn-on resistance and better current performance. In addition, when the channel width of the power switch decreases, the power switch can have a small capacitance and a small switching loss.

[0087] The control circuit of the power management circuit can drive the first power switch SW1 and / or the second power switch SW2 in response to a power control signal.

[0088] For example, in a case in which the size of the panel load is small, the control circuit can drive the first power switch SW1, and can not drive the second power switch SW2. In addition, in a case in which the size of the panel load is moderate, the control circuit can not drive the first power switch SW1, and can drive the second power switch SW2. In addition, in a case in which the size of the panel load is large, the control circuit can drive both the first power switch SW1 and the second power switch SW2.

[0089] The power control signal can include data of two bits. In addition, the control circuit can determine whether to drive the second power switch SW2 based on a first bit value of the data, and can determine whether to drive the first power switch SW1 based on a second bit value of the data.

[0090] Figure 7 is a configuration diagram of a power management circuit according to another embodiment.

[0091] Reference Figure 7 , in addition to Figure 3The power management circuit 710 can further include an amplifier 712 in addition to the elements of the power management circuit 110 illustrated.

[0092] The amplifier 712 can supply a common voltage VCOM to a common electrode of the display panel.

[0093] Further, the control circuit 320 of the power management circuit 710 can control a bias current of the amplifier 712.

[0094] For example, the control circuit 320 can receive a power control signal from a timing controller. The power control signal can include information about a size of a change in image data between frames. Further, the control circuit 320 can control the amplifier 712 such that the bias current of the amplifier 712 increases as the size of the change in the image data between the frames increases.

[0095] Alternatively, the power control signal can include information about a size of a panel load. The control circuit 320 can control the amplifier 712 such that the bias current of the amplifier 712 increases as the size of the panel load increases.

[0096] Figure 8 is a diagram illustrating a functional flow performed for each frame.

[0097] Referring to Figure 8 , a timing controller can receive image data for each frame, and can analyze a pattern of the image data.

[0098] The timing controller can receive first image data RGB1 in a first frame FRM1, and can calculate a size of a panel load by analyzing a pattern of the first image data RGB1. Further, the timing controller can receive second image data RGB2 in a second frame FRM2, and can calculate a size of a panel load by analyzing a pattern of the second image data RGB2.

[0099] The timing controller can transmit the first image data RGB1 to a source driver in the second frame FRM2, and can transmit a first power control signal PCS1 including information about the size of the panel load of the first image data RGB1 to a power management circuit. Further, the timing controller can transmit the second image data RGB2 to the source driver in a third frame FRM3, and can transmit a second power control signal PCS2 including information about the size of the panel load of the second image data RGB2 to the power management circuit.

[0100] The source driver can convert the first image data RGB1 into a data voltage in the third frame FRM3 and can drive the pixels. The power management circuit can supply power to the source driver in response to the first power control signal PCS1 in the third frame FRM3 and can supply a common voltage to the common electrode of the panel. Also, the source driver can convert the second image data RGB2 into a data voltage in the fourth frame and can drive the pixels. The power management circuit can supply power to the source driver in response to the second power control signal PCS2 in the fourth frame and can supply a common voltage to the common electrode of the panel.

[0101] As described above, according to the present embodiment, power consumption in the display apparatus can be optimized.

[0102] CROSS-REFERENCE TO RELATED APPLICATIONS

[0103] This application claims priority to Korean Patent Application No. 10-2020-0177993, filed on December 18, 2020, which is incorporated by reference into the present application for all purposes as if fully set forth in the present application.

Claims

1. A power management circuit connected to a power conversion circuit and a timing controller, the power management circuit comprising: a switch driving circuit configured to drive a plurality of power switches connected to the power conversion circuit; and a control circuit configured to receive a control signal from the timing controller and change a driving condition of the switch driving circuit in response to the control signal, wherein the plurality of power switches have different channel widths, the control signal includes information about a size of a panel load, and the control circuit is configured to select at least one power switch based on the size of the panel load and the channel width of each of the one or more power switches, and is configured to drive the selected power switch, and wherein the plurality of power switches includes a first power switch and a second power switch having a channel width wider than that of the first power switch, wherein, in a case where the size of the panel load is a first value, the control circuit is configured to drive the first power switch and is configured not to drive the second power switch; in a case where the size of the panel load is a second value larger than the first value, the control circuit is configured not to drive the first power switch and is configured to drive the second power switch; and in a case where the size of the panel load is a third value larger than the second value, the control circuit is configured to drive both the first power switch and the second power switch.

2. The power management circuit according to claim 1, wherein the plurality of power switches are connected in parallel, and the control circuit adjusts the number of power switches driven in response to the control signal. The control circuit is configured to adjust a switching frequency of the at least one power switch in response to the control signal.

3. The power management circuit of claim 1, wherein, 4. The power management circuit according to claim 1, wherein the plurality of power switches include a first power switch and a second power switch having a channel width wider than that of the first power switch, the control signal includes two bits of data, and the control circuit determines whether to drive the second power switch based on a first bit value of the data, and determines whether to drive the first power switch based on a second bit value of the data. Power converted by the at least one power switch is supplied to a source driver configured to drive pixels of a panel.

5. The power management circuit of claim 1, wherein, The control circuit is configured to control a bias current of an amplifier configured to supply a voltage to a common electrode of the panel in response to the control signal.

6. The power management circuit of claim 5, wherein, 7. The power management circuit according to claim 6, wherein the control signal includes information about a size of a change in image data between frames, and the control circuit is configured to control the amplifier such that the bias current increases as the size of the change increases.

8. A timing controller, the timing controller comprising: a load analysis circuit configured to analyze image data of each frame and calculate a panel load of each frame; and a control signal generator configured to generate a control signal based on the panel load of each frame. ​ communication circuitry configured to generate a control signal corresponding to a size of the panel load and transmit the control signal for changing a driving condition of the control circuitry to power management circuitry including the control circuitry and a plurality of power switches, wherein the plurality of power switches includes a first power switch and a second power switch having a channel width wider than a channel width of the first power switch, wherein, in a case where the size of the panel load is a first value, the control circuitry is configured to drive the first power switch and is configured not to drive the second power switch; in a case where the size of the panel load is a second value larger than the first value, the control circuitry is configured not to drive the first power switch and is configured to drive the second power switch; and in a case where the size of the panel load is a third value larger than the second value, the control circuitry is configured to drive both the first power switch and the second power switch.

9. The timing controller of claim 8, wherein, the communication circuitry transmits the control signal to the power management circuitry through a single line.

10. The timing controller of claim 8, wherein, the communication circuitry receives the image data and mode information from a host and generates the control signal by further using the mode information.

11. The timing controller of claim 8, wherein, the load analysis circuitry calculates the size of the panel load based on a size of a change between frames of the image data.

12. The timing controller of claim 8, wherein, the communication circuitry transmits the control signal in units of frames.

13. The timing controller of claim 8, wherein, the power management circuitry changes a driving condition of at least one power switch in response to the control signal.

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