Integrated assembly with word line driver circuitry directly below vertically extending word lines

Abstract

Some embodiments include an integrated assembly having word line driver circuitry directly below vertically extending word lines. The word line driver circuitry is subdivided among horizontally extending sub-word line driver (SWD) cells. Memory cells are over a substrate and arranged in vertically extending rows. Each of the memory cells includes an access device and a storage element coupled with the access device. Word lines extend vertically along the rows. Each of the SWD cells is associated with at least two of the word lines and is configured to simultaneously activate the associated word lines.

Description

Technical Field

[0001] Integrated assembly. Integrated memory. An assembly having a word line driver circuitry system located directly below the vertically extending word lines. Background Technology

[0002] Memory is a type of integrated circuit used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, sense lines, or data / sense lines) and access lines (also called word lines). Digital lines electrically interconnect memory cells along columns of the array, and access lines electrically interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed using a combination of digital lines and access lines.

[0003] Memory cells can be volatile or non-volatile. Non-volatile memory cells can store data for extended periods, including when the computer is off. Volatile memory dissipates data and is therefore refreshed / rewritten rapidly, often multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two distinct optional states. In binary, these states are represented as either "0" or "1". In other systems, at least some individual memory cells may be configured to store information in more than two levels or states.

[0004] Some memory cells may contain transistors in combination with capacitors (or other suitable storage elements). The transistors are used to selectively access the capacitors and can be called access devices. Capacitors electrostatically store energy as an electric field within the capacitor dielectric between two plates. The electrical state of the capacitor can be used to indicate the memory state.

[0005] Word lines can be coupled to word line driver circuitry, and digital lines can be coupled to sense amplifier circuitry. A memory device (e.g., a dynamic random access memory (DRAM) device) can be considered as collectively including word lines, digital lines, memory cells, sense amplifier circuitry, and word line driver circuitry. The need for higher levels of integration necessitates the development of architectures that enable memory devices to consume less space than valuable semiconductor area. Summary of the Invention

[0006] In some instances, an integrated assembly is described. The integrated assembly may include: vertically extending word lines above a substrate; memory cells adjacent to the word lines, each of the word lines associated with a row of the memory cells; the memory cells in each row being vertically stacked together; and a word line driver circuitry within the substrate; the word line driver circuitry being subdivided among sub-word line driver (SWD) cells; each of the SWD cells being associated with at least two of the word lines and configured to simultaneously activate the at least two of the word lines.

[0007] In some instances, an integrated assembly is described. The integrated assembly may include: a CMOS substrate; the CMOS substrate including a word line driver circuitry; the word line driver circuitry being subdivided among horizontally extending sub-word line driver (SWD) cells; memory cells above the substrate, the memory cells being arranged in vertically extending rows; each of the memory cells including an access device and a memory element coupled to the access device; word lines extending vertically along the rows; and each of the SWD cells being associated with and configured to simultaneously activate the at least two of the word lines.

[0008] In some instances, an integrated assembly is described. The integrated assembly may include: an array of stacked memory cells over a CMOS substrate; each of the memory cells including a horizontally extending capacitor coupled to a horizontally extending access device; the memory cells arranged in vertically extending rows; the rows being paired, wherein paired rows share a capacitor plate between the horizontally extending capacitors of the memory cells; the CMOS substrate including a word line driver circuitry; the word line driver circuitry being subdivided between sub-word line driver (SWD) cells; word lines extending along the rows; the word lines being paired, wherein a set of paired word lines is associated with each of the paired rows; and each of the SWD cells is associated with at least one of the set of paired word lines and configured to simultaneously activate the word line of the at least one of the set. Attached Figure Description

[0009] Figure 1 It is a graphical 3D view of the instance area of ​​the instance integration assembly.

[0010] Figure 2 It is a graphical 3D view of the instance area of ​​the instance integration assembly.

[0011] Figure 3 It is a graphical 3D view of the instance area of ​​the instance integration assembly.

[0012] Figure 4This is a schematic cross-sectional side view of the instance area of ​​the instance integration assembly.

[0013] Figure 5 It is a top view of the cross section of the instance area of ​​the instance integration assembly.

[0014] Figure 6 It is a top view of the cross section of the instance area of ​​the instance integration assembly.

[0015] Figure 7 This is a top-view diagram of the instance area of ​​the instance integration assembly.

[0016] Figure 8 and 9 It is a diagrammatic explanation of the instance operation relationships of instance memory devices. Detailed Implementation

[0017] Some embodiments include an integrated assembly having vertically extending word lines and a word line driver circuitry directly beneath at least some of the vertically extending word lines. (Reference) Figures 1 to 9 Describe an example implementation.

[0018] refer to Figure 1 The regions of the integrated component 10 are illustrated. The regions adjacent to the assembly 10 provide an x, y, z coordinate system to help describe the relative orientation of the various structures of the assembly 10.

[0019] Assembly 10 includes a substrate 12. The substrate 12 may include semiconductor materials; and, for example, may include monocrystalline silicon, be substantially composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure that includes semiconductor materials, including but not limited to bulk semiconductor materials, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor materials (alone or in an assembly including other materials). The term "substrate" refers to any support structure, including but not limited to the semiconductor substrate described above. In some applications, substrate 12 may correspond to a semiconductor substrate housing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0020] Substrate 12 may include CMOS (Complementary Metal-Oxide-Semiconductor) regions, which include sensing circuitry and / or control circuitry. In the illustrated embodiment, a sub-word line driver (SWD) circuitry is located in region 14 of the substrate, and a sense amplifier (SA) circuitry is located in region 16 of the substrate. Regions 14 and 16 may be referred to as the SWD region and the SA region, respectively. The illustrated SWD and SA regions may represent a plurality of SWD and SA regions formed across substrate 12.

[0021] A pair of vertically extending word lines 18 are displayed above the substrate. The vertically extending word lines 18 extend along the illustrated z-axis. In some embodiments, the region 14 may be considered to extend along the illustrated y-axis direction and have a horizontally extending upper surface 15. The word lines 18 may be considered to extend orthogonally to the upper surface 15, or at least substantially orthogonally to this upper surface; wherein the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances. In some embodiments, the vertically extending word lines 18 may extend within approximately 10° of the horizontally extending upper surface 15 orthogonal to the SWD region 14.

[0022] In the illustrated embodiment, the two illustrated word lines 18 are labeled WL-1 and WL-2 so that they can be distinguished relative to each other.

[0023] Memory cells (MC) 20 are adjacent to word lines 18. The memory cells can be viewed as being arranged in an array 22, which comprises vertically extending rows 24. In the illustrated embodiment, the row adjacent to word line WL-1 is labeled 24a, and the row adjacent to word line WL-2 is labeled 24b. Each row includes memory cells 20 stacked vertically on top of each other. Word lines 18 can be viewed as extending along rows 24 of the memory array 22, wherein each word line is associated with a memory cell in one of the rows (e.g., where word line WL-1 is associated with memory cell 20 in row 24a).

[0024] Memory cell 20 may include any suitable configuration, and in some embodiments may include an access device (AD) 32 coupled to memory element (SE) 34, as shown in the top memory cell 20 relative to row 24b. Access device 32 may be any suitable device, including, for example, a transistor, diode, bidirectional threshold switch, etc. Memory element 34 may be any suitable device having at least two detectable states; and in some embodiments, memory element may be, for example, a capacitor, resistive memory device, conductive bridge device, phase-change memory (PCM) device, programmable metallized cell (PMC), etc.

[0025] Digital lines 26 extend along columns of memory array 22, wherein the illustrated digital lines are labeled DL-1_0, DL-1_1, etc.; wherein the markings on the digital lines indicate the level and digital line number (e.g., DL-1_0 is digital line 0 in level 1). In the illustrated embodiment, digital lines 26 extend orthogonally (or at least substantially orthogonally) relative to the horizontally extending SWD area 14. Specifically, digital lines 26 are shown extending along the illustrated x-axis direction, and SWD area 14 is shown extending along the illustrated y-axis direction.

[0026] Each of the memory cells 20 is shown to be electrically coupled to a word line and a digital line, and can be considered to be uniquely addressed by the digital line in combination with the word line in the word line.

[0027] The digital lines are coupled to the sense amplifier circuitry, and in the illustrated embodiment, an example digital line (specifically, digital line DL-1_0) is shown as electrically coupled to SA region 16. Other digital lines will also be coupled to SA regions, but such SA regions are not illustrated for simplicity. Several example physical directions from the digital lines to the associated SA regions are schematically indicated by arrows along digital lines DL-4_0 and DL-4_1.

[0028] SWD region 14 is located directly below word lines 18 and is shown electrically coupled to such word lines. In some embodiments, SWD region 14 may be considered to correspond to an SWD cell, which is associated with and configured to simultaneously activate two word lines WL-1 and WL-2. Although the illustrated SWD cell 14 is configured to simultaneously activate two word lines, in other embodiments, a comparable SWD cell may be used to simultaneously activate more than two word lines. Generally, an SWD cell may be configured to simultaneously activate at least two, at least four, etc., of word lines 18. SWD region 14 may include any suitable circuitry and, in some embodiments, may include one or more inverters. Using inverters increases the fill density of the SWD region compared to other configurations lacking inverters.

[0029] SA region 16 is shown to be laterally offset from SWD region 14 and not directly below memory cell 20. In some embodiments, SA region 16 may be laterally offset from array 22 such that it is not directly below the array. In other embodiments, at least a portion of SA region 16 may be below array 22. SA region 16 may be provided in any suitable location, including below array 22, laterally offset relative to array 22, above array 22, etc.

[0030] The illustrated area of ​​assembly 10 can be considered as portion 28 of the assembly along a pair of word lines. This portion can represent a large portion within memory array 22. The memory array can include hundreds, thousands, hundreds of thousands, millions, etc., memory cells; hundreds, thousands, hundreds of thousands, millions, etc., word lines; and hundreds, thousands, hundreds of thousands, millions, etc., digital lines. SWD cells can represent a large number of SWD cells provided within substrate 12, wherein the SWD cells together comprise the overall configuration of the word line driver circuitry system.

[0031] Section 28 can be considered to include layers (hierarchies) 30, each layer containing a pair of illustrated digital lines and a pair of illustrated memory cells (e.g., bottom layer 30 contains digital lines DL-1_0 and DL-1_1, and bottom memory cells 20 contained in rows 24a and 24b). Although the illustrated area includes four layers 30, it should be understood that any suitable number of layers may exist. For example, in some embodiments, eight layers, 16 layers, 32 layers, 64 layers, etc., may exist.

[0032] Figure 1 The advantage of this configuration is that the formation of the SWD region 14 directly below the vertically extending word line 18 allows for a tight encapsulation of the SWD region relative to the memory array 22, while retaining valuable semiconductor footprint compared to conventional configurations. Configuring the SWD region 14 to simultaneously activate two or more word lines may be advantageous because the SWD region is typically relatively large compared to the word line pitch (where the example word line pitch is in...). Figure 1 This is illustrated in the diagram as spacing P. Therefore, the minimum footprint of a single word line and SWD configuration is limited by the footprint of the SWD area. The one-to-one correspondence between word lines and SWD areas limits the word line spacing to the SWD area spacing. Conversely, having multiple word lines associated with each of the SWD areas allows the word line spacing to be reduced to less than the SWD area spacing.

[0033] Figure 2 This shows another instance area of ​​the integrated assembly 10. Figure 2 The instance area comprises an SWD region (cell) 14 along the base 12 and includes four word lines 18 associated with this SWD region. The word lines are labeled WL-1, WL-2, WL-7, and WL-8. Each of the word lines is associated with a row 24 of the memory cell 20 within the array 22, wherein the individual rows are labeled 24a, 24b, 24g, and 24h.

[0034] Digital lines 26 extend along columns of array 22. Each memory cell 20 is uniquely addressed by a combination of one digital line and one word line. Several instances of physical directions from the digital lines to the SA regions associated with the digital lines are graphically indicated by arrows along digital lines DL-4_0, DL-4_1, DL-4_2, and DL-4_3.

[0035] The illustrated area comprises four levels 30. In other embodiments, the area may include more than four such levels, and may include, for example, eight levels, 16 levels, 32 levels, 64 levels, etc.

[0036] SWD unit 14 can be configured to simultaneously activate all four illustrated word lines 18, and is therefore labeled WL_1 / 2 / 7 / 8. In some embodiments, SWD unit 14 may be provided to extend to a sufficient length such that all word lines are directly above the SWD area. In the illustrated embodiment, SWD area 14 (e.g., containing a CMOS area) is located only directly below the center word lines WL-2 and WL-7, and a redistribution circuitry (e.g., wiring) 36 is provided to couple SWD area 14 to the two outer word lines WL-1 and WL-8.

[0037] Figure 1 and 2 The memory array 22 in this embodiment may include any suitable configuration. (See reference...) Figure 3 and 4 Describe the instance configuration.

[0038] refer to Figure 3 Access device 32 is shown as corresponding to a transistor (only one is labeled), wherein such transistor includes source / drain regions 38 and 40, and a channel region 42. Storage element 34 corresponds to a capacitor (only one is labeled), wherein such capacitor is coupled to transistor 32 via conductive interconnect 44. In some applications, the conductive interconnect may be considered as part of capacitor 34, and may be considered, for example, as part of storage node of such capacitor.

[0039] Memory cell 20 (only one of which is labeled) includes transistor 32 and capacitor 34. The memory cells are arranged in array 22, which has rows 24 extending along the illustrated z-axis and columns 46 extending along the illustrated x-axis. Individual rows are labeled 24a, 24c, and 24e, and individual columns are labeled 46a-c.

[0040] Digital lines 26 (labeled DL-1_0, DL-2_0 and DL-3_0) extend along column 46 and are coupled to the source / drain region 38 of transistor 32.

[0041] Word lines 18 (labeled WL-1, WL-3, and WL-5) extend along rows of the memory array and are adjacent to the channel region 42 of transistor 32. In the illustrated embodiment, each of the word lines includes two components (labeled 18a and 18b for word line WL-1), wherein such components extend along the z-axis and are on opposite sides of the channel region 42. In some embodiments, each of the word lines may be considered as branching into two vertically extending components. In other embodiments, the word lines may include other suitable configurations and may include, for example, a single component only on one side of the channel region, or may include a gate-all-around configuration, etc.

[0042] Word line 18 includes a gating region operatively adjacent to channel region 42 of transistor 32, such that source / drain regions 38 and 40 of each transistor 32 are coupled to each other in a gating manner. When used herein, the term "gating coupling" may refer to controlled coupling / decoupling of source / drain regions 38 and 42 that may be triggered by electrical activation / deactivation of word line 18.

[0043] The gate region along word line 18 may be spaced from channel region 42 by a gate dielectric material (not shown). The gate dielectric material may include any suitable composition, and in some embodiments may include silicon dioxide, substantially composed of silicon dioxide, or composed of silicon dioxide.

[0044] Word lines extend to SWD units 14, and in the illustrated embodiment, each of the word lines extends to a separate SWD unit (where SWD units are labeled 14a-c, and SWD-1 to SWD-3). In some embodiments, Figure 3 Assembly 10 can be considered as including a word line driver circuit system, wherein this word line driver circuit system is subdivided among a plurality of SWD units. The illustrated units 14a-c represent SWD units.

[0045] In the illustrated embodiment, the body region (channel region) 42 of transistor 32 is coupled to a conductive plate 48. This plate can be used to allow excess carriers (e.g., holes) to drain from the body region 42 during certain operating modes of memory cell 20. Plate 48 may comprise one or more of any suitable conductive composition; such as various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0046] Figure 4 Showing along the y-axis Figure 3 A cross-sectional side view of assembly 10, wherein the cross-section passes through the memory cell 20 associated with word line WL-1. Word line WL-1 is in Figure 4 The dashed line (or short dashed line) is used in the view to indicate its offset from the illustrated section. Specifically, the word line WL-1 will be relative to... Figure 4 The section described is located both inside and outside the page.

[0047] Transistor 32 is shown extending horizontally along the y-axis and is shown to include a body region 42 and source / drain regions 38 and 40.

[0048] The capacitor 34 is also shown extending horizontally along the y-axis and includes an outer node (storage node) 50, an inner node (plate electrode) 52, and a capacitor dielectric material 54.

[0049] Nodes 50 and 52 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). Nodes 50 and 52 may include compositions that are the same as each other, or they may include compositions that are different from each other.

[0050] The capacitor dielectric material 54 may include any suitable composition; and in some embodiments may include one or more of silicon oxide, aluminum oxide, hafnium oxide, etc.

[0051] SWD area 14a is shown extending horizontally along the y-axis and electrically coupled to both word lines WL-1 and WL-2. Word line WL-2 is shown associated with row 24b of memory cell 20. In the illustrated embodiment, the memory cell associated with row 24b is labeled 20b, and the memory cell associated with row 24a is labeled 20a. Furthermore, the capacitors and transistors within memory cell 20a are labeled 34a and 32a, respectively; and the capacitors and transistors within memory cell 20b are labeled 34b and 32b, respectively.

[0052] Capacitor 34b is a mirror image of capacitor 34a, which is located across a plane 49 centrally between capacitors 34a and 34b. Plane 49 extends through plate electrode 52.

[0053] Capacitors 34a and 34b extend horizontally along the y-axis. Transistor 32a also extends horizontally along the y-axis. Transistor 32b may be configured similarly to transistor 32a, such that they also extend horizontally along the y-axis. In the illustrated embodiment, transistor 32b is shown schematically for simplicity of the diagram.

[0054] In some embodiments, memory cell 20a in row 24a can be considered to be paired with memory cell 20b in row 24b, since memory cells 20a and 20b share capacitor plates 52 in capacitors 34a and 34b.

[0055] In some embodiments, word lines WL-1 and WL-2 can be considered as paired with each other because they are associated with paired rows 24a and 24b. Word lines WL-1 and WL-2 can be considered together as forming a set of paired word lines, and this set can represent a large collection of paired word lines extending across the memory array 22 of the integrated assembly 10. In the illustrated embodiment, at least a portion of individual memory cells 20a and 20b is laterally positioned between word lines WL-1 and WL-2 (e.g., capacitors 34a and 34b are laterally positioned between word lines WL-1 and WL-2).

[0056] Word lines WL-1 and WL-2 extend to the same SWD area 14a and can be activated simultaneously by SWD area 14a.

[0057] Figure 4 The assembly 10 displays multiple insulating materials 56, 58, 60, and 62. These insulating materials may include any suitable composition, including one or more of, for example, silicon nitride, aluminum oxide, silicon dioxide, hafnium oxide, zirconium oxide, etc. Insulating materials 56, 58, 60, and 62 may differ in composition from each other, or one or more of these insulating materials may be identical in composition.

[0058] Figure 5 Displayed in a similar Figure 3 and 4 The configuration is shown in the top cross-sectional view of the area passing through assembly 10. The assembly contains six representative numeral lines 18 (labeled WL-1 to WL-6). A pair of representative numeral lines 26 are illustrated in a dashed (dashed) view to indicate that the numeral lines are out of plane relative to the illustrated cross-sectional view.

[0059] Figure 5 The memory array 22 is shown to include representative memory cells 20a-f, each of which includes a horizontally extending transistor (e.g., 32a) and a horizontally extending capacitor (e.g., 34a). A plate electrode 52 branches the memory cells into a first group on one side of the plate electrode and a second group on the other side. The first group includes memory cells 20a, 20c, and 20e, and the second group includes memory cells 20b, 20d, and 20f.

[0060] Memory cells 20a and 20b can be considered as paired with each other. Similarly, memory cells 20c and 20d can be considered as paired with each other, and memory cells 20e and 20f can be considered as paired with each other.

[0061] Word lines WL-1 and WL-2 can be considered as a first set of paired word lines associated with the first SWD unit 14a (SWD-1), word lines WL-3 and WL-4 can be considered as a second set of paired word lines associated with the second SWD unit 14b (SWD-2), and word lines WL-5 and WL-6 can be considered as a third set of paired word lines associated with the third SWD unit 14c (SWD-3).

[0062] A first conductive plate 48a is operably close to the body regions (channel regions) of transistors 32a, 32c, and 32e to discharge excess carriers from such body regions during the operating modes of memory cells 20a, 20c, and 20e. Similarly, a second conductive plate 48b is operably close to the body regions of transistors 32b, 32d, and 32f to discharge excess carriers from such body regions during the operating modes of memory cells 20b, 20d, and 20f.

[0063] Figure 5 The embodiment shows each of two SWD regions 14 associated with a word line (e.g., SWD region 14a is associated with word lines WL-1 and WL-2). In other embodiments, similar SWD regions may be associated with more than two word lines. For example, Figure 6 This demonstrates an example of how individual SWD areas are associated with four word lines.

[0064] Figure 6 The integrated assembly 10 includes twelve representative word lines WL-1 to WL-12 and includes representative memory cells 20a to 20l operatively adjacent to the gating regions of the word lines. Figure 6 The integrated assembly 10 also includes SWD regions 14a-c (SWD-1 to SWD-3). However, with Figure 5 The components are different. Figure 6 The assembly has each of the individual SWD zones associated with the four word lines. For example, SWD zone 14a (SWD-1) is associated with word lines WL-1, WL-2, WL-7, and WL-8, and is configured to activate all such associated word lines simultaneously.

[0065] Figure 6 Conductive plates 48a-d are shown, which extend along the x-axis and are operatively coupled to the body regions of transistors 32a-l of memory cells 20a-l to drain excess carriers from such body regions.

[0066] Word lines WL-1 to WL-12 can be considered as comprising six sets of paired word lines, wherein such paired sets include WL-1 / WL-2, WL-3 / WL-4, WL-5 / WL-6, WL-7 / WL-8, WL-9 / WL-10, and WL-11 / WL-12. Paired sets can be considered as being within a first group 64 and a second group 66, wherein the second group is laterally offset relative to the first group. For example, paired set WL-1 / WL-2 is within the first group 64 and laterally offset from paired set WL-7 / WL-8 within the second group 66. However, paired sets WL-1 / WL-2 and WL-7 / WL-8 are both associated with the same SWD unit (specifically, unit 14a, i.e., SWD-1).

[0067] Intermediate region 68 lies between two groups 64 and 66. Intermediate region includes an insulating panel 70 sandwiched between conductive plates 48b and 48c. In some embodiments, plates 48b and 48c may be referred to as first and second conductive plates, respectively, and the insulating panel 70 may be considered as sandwiched between such first and second conductive plates.

[0068] The insulating panel 70 may include any suitable composition, and in some embodiments may include one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, etc.

[0069] SWD unit 14a-c can extend horizontally along a sufficient length to be in conjunction with Figure 6 In this configuration, such an SWD unit extends below all word lines associated with it. For example, SWD unit 14a (SWD-1) may extend horizontally for a sufficient length to be below all word lines WL-1, WL-2, WL-7, and WL-8. Alternatively, the SWD unit may be below only a few word lines associated with it, similar to the above reference. Figure 2 The described configuration allows for the redistribution of circuitry to other word lines. Figure 7 The display can be relative to Figure 6 A specific implementation of the practical configuration. Specifically, Figure 7 The diagram illustrates the paired word line groups WL-1 / W-2 and WL-7 / WL-8 associated with SWD unit 14a (SWD-1), showing SWD unit 14a located only directly below the center word lines WL-2 and WL-7. A redistribution circuitry system 36 is provided to reach the outer word lines WL-1 and WL-8 from SWD unit 14a.

[0070] The configuration described above can be operated in any suitable manner. Figure 8 and 9 This describes the instance operating mechanism that can be used relative to this configuration.

[0071] First refer to Figure 8 This display can be relative to Figure 1 and 5 The example implementation uses an operating mechanism in which the SWD unit is associated with only two word lines. It should be understood that... Figure 8 The representation is not a physical representation of a specific embodiment, but rather a representation of operational characteristics relative to the example embodiments described above. Therefore, Figure 8 The structures shown may or may not have the physical proximity represented in the diagram. Word lines are not in... Figure 8 Instead of showing it in detail, the memory cell 20 is illustrated with an elliptical diagram, and the position of the word line can be inferred relative to the position of the memory cell.

[0072] SWD unit 14 is indicated graphically by arrows corresponding to SWD-1 to SWD-8. An open circle is provided immediately adjacent to SWD-6 to indicate that it is selected, and a solid circle (black dot) is provided immediately adjacent to the other SWDs to indicate that it is not selected.

[0073] Memory cells 20 are arranged in columns along representative digital lines 26. Memory cells 20 are also arranged in rows that extend in the direction indicated by the arrow below the SWD cell. Figure 8 The rows and columns are relative to the above with respect to memory array 22 (e.g., Figure 3 The rows 24 and columns 46 described in the memory array 22 shown are not the same.

[0074] Digital lines are shown arranged in pairs of relatively coupled lines, wherein the relatively coupled lines extend to the sense amplifier 16. For example, digital lines DL-0T and DL-0C correspond to a pair of relatively coupled digital lines extending to the sense amplifier circuit system SA-0. Digital line DL-0T can be considered a “real” digital line and digital line DL-0C can be considered a “complementary” digital line relatively coupled to the real digital line. For the purposes of understanding this disclosure and the appended claims, if the sense amplifier circuit system is configured to compare the electrical characteristics (e.g., voltage) of the first digital line and the second digital line with each other, then the first digital line is “relatively coupled” to the second digital line through the sense amplifier circuit system. The terms “real” and “complementary” are arbitrary and used to distinguish digital lines compared with each other through the sense amplifier circuit system. The hierarchy of memory cells is in Figure 8 Unless otherwise specified, for convenience, only the numbers on the line illustrate specific concepts.

[0075] The true number line can be offset laterally relative to the complementary number line. If Figure 1 and 5 If the number lines are real number lines, then the associated complementary number lines can be in a position relative to... Figure 1 and 5 The array 22 shown is in a different array.

[0076] Each of the SWD cells can be considered as simultaneously activating multiple word lines. For example, SWD-6 is shown as two groups 68 and 70 activating memory cells 20, where such groups are illustrated using ellipses. Each of groups 68 and 70 contains two memory cells. Groups 68 and 70 may be in different levels relative to each other. A specific memory cell within an active group can be addressed using one of the indicated digital lines. In the illustrated embodiment, memory cell 20a is shown as being addressed using SWD-6 and digital line DL-0T. The addressing of the memory cell is illustrated by providing a square frame around the memory cell.

[0077] Figure 9 The display can be relative to Figure 2 , 6 The operating mechanism used in the example embodiment of 7, wherein the SWD unit is associated with four word lines. The SWD unit identified as SWD-6 is shown as active, comprising a group 72 containing four memory units 20. The memory unit 20a within this active group is addressed using a digital line identified as DL-0T.

[0078] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0079] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0080] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0081] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others may be to provide linguistic variation within this disclosure to simplify the presuppositions of the appended claims.

[0082] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the figures or rotated relative to such an orientation.

[0083] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features in the plane of the cross section and do not show the material behind the plane of the cross section in order to simplify the drawings.

[0084] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intermediary structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intermediary structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0085] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally to the upper surface of the substrate.

[0086] Some embodiments include an integrated assembly having word lines extending vertically above a substrate. Memory cells are adjacent to the word lines. Each word line is associated with a row of memory cells. Memory cells in each row are stacked vertically on top of each other. The word line driver circuitry is within the substrate. The word line driver circuitry is subdivided among sub-word line driver (SWD) cells. Each SWD cell is associated with at least two word lines and configured to activate said at least two word lines simultaneously.

[0087] Some embodiments include an integrated assembly having a CMOS substrate containing a word line driver circuitry. The word line driver circuitry is subdivided among horizontally extending sub-word line driver (SWD) cells. Memory cells are located above the substrate and arranged in vertically extending rows. Each memory cell includes an access device and a memory element coupled to the access device. Word lines extend vertically along the rows. Each SWD cell is associated with at least two word lines and configured to simultaneously activate the associated word lines.

[0088] Some embodiments include an integrated assembly comprising an array of stacked memory cells over a CMOS substrate. Each memory cell includes a horizontally extending capacitor coupled to a horizontally extending access device. The memory cells are arranged in vertically extending rows. The rows are paired, with paired rows sharing a capacitor plate between the horizontally extending capacitors of the memory cells. The CMOS substrate includes a word line driver circuitry. The word line driver circuitry is subdivided between sub-word line driver (SWD) cells. Word lines extend along the rows. The word lines are paired, with a set of paired word lines associated with each of the paired rows. Each SWD cell is associated with at least one of the paired word line groups and is configured to simultaneously activate the word lines of said at least one group.

[0089] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: Vertically extending letter lines above the base; The memory cells adjacent to the word lines, each of the word lines being associated with a row of the memory cells; the memory cells in each row are stacked vertically on top of each other; and The word line driver circuitry within the substrate; The word line driver circuitry is subdivided among sub-word line driver SWD units; each of the SWD units is associated with at least two of the word lines and configured to simultaneously activate the at least two of the word lines. The substrate includes one or more sensing circuit systems and redistribution circuit systems.

2. The integrated assembly of claim 1, wherein each of the SWD units is directly below at least some of the word lines associated with it.

3. The integrated assembly of claim 1, wherein each of the SWD units is directly below all the word lines associated with it.

4. The integrated assembly of claim 1, wherein each of the SWD units is configured to simultaneously activate at least four of the word lines.

5. The integrated assembly of claim 4, wherein each of the SWD units is configured to simultaneously activate four of the word lines; wherein the four word lines simultaneously activated by the SWD unit are considered associated with this SWD unit; wherein each of the SWD units includes a CMOS circuitry below the center two of the four word lines associated with it, and includes a redistributed circuitry extending from the CMOS circuitry to the outer two of the four word lines associated with it.

6. The integrated assembly of claim 1, comprising horizontally extending digital lines extending along the columns of the memory cells.

7. The integrated assembly of claim 6, wherein the digital line extends into the sensing amplifier circuitry within the substrate and is laterally offset directly below the memory cell.

8. The integrated assembly of claim 1, wherein the substrate comprises monocrystalline silicon.

9. The integrated assembly of claim 1, wherein each of the memory cells comprises a transistor coupled to a capacitor.

10. The integrated assembly of claim 9, wherein the transistor extends horizontally.

11. The integrated assembly of claim 9, wherein the capacitor extends horizontally.

12. An integrated assembly comprising: Includes CMOS substrate; The CMOS substrate includes a word line driver circuit system; The word line driver circuitry is subdivided between horizontally extending sub-word line driver SWD units. The memory cells are arranged in vertically extending rows above the substrate; each of the memory cells includes an access device and a storage element associated with the access device. The character line extends vertically along the line; Each of the SWD units is associated with at least two of the word lines and is configured to activate the at least two of the word lines simultaneously. and Each of the SWD units is associated with only two of the word lines.

13. The integrated assembly of claim 12, comprising horizontally extending digital lines extending along the columns of the memory cells.

14. The integrated assembly of claim 13, wherein the horizontally extending digital line extends substantially orthogonally relative to the horizontally extending SWD unit.

15. The integrated assembly of claim 12, wherein the substrate has a horizontally extending surface, and wherein the word lines extend substantially orthogonally to the horizontally extending surface.

16. The integrated assembly of claim 12, wherein each of the SWD units is associated with four of the word lines.

17. The integrated assembly of claim 12, wherein the access device is a transistor.

18. The integrated assembly of claim 17, wherein the transistor extends horizontally.

19. The integrated assembly of claim 12, wherein the storage element is a capacitor.

20. The integrated assembly of claim 19, wherein the capacitor extends horizontally.

21. The integrated assembly of claim 12, wherein the SWD unit comprises an inverter.

22. An integrated assembly comprising: An array of stacked memory cells on a CMOS substrate; Each of the memory cells includes a horizontally extending capacitor coupled to a horizontally extending access device. The memory cells are arranged in vertically extending rows; The rows are in a paired relationship, wherein the paired rows share a capacitor plate between the horizontally extending capacitors of the memory cells; The CMOS substrate includes a word line driver circuit system; The word line driver circuitry is subdivided among the sub-word line driver SWD units; The word line extending along the line; The word lines are in a pairing relationship, wherein a pair of paired word lines are associated with each of the paired lines; and Each of the SWD units is associated with at least one of the groups of the paired word lines and is configured to simultaneously activate the word lines of at least one of the groups; and Each of the SWD units is associated with only one of the groups of the paired word lines.

23. The integrated assembly of claim 22, wherein the access device is a transistor.

24. The integrated assembly of claim 22, comprising horizontally extending digital lines extending along the columns of the memory cells.

25. The integrated assembly of claim 24, wherein the horizontally extending capacitor and access device extend along a first direction, and wherein the horizontally extending digital line extends along a second direction substantially orthogonal to the first direction.

26. The integrated assembly of claim 22, wherein at least a portion of the memory cells in the pairing line associated with a given in the group of the pairing word lines are laterally positioned between the pairing word lines of the given in the group.

27. The integrated assembly of claim 22, wherein each of the SWD units is associated with and configured to simultaneously activate the paired word lines of the at least two of the group of paired word lines.

28. The integrated assembly of claim 22, wherein each of the SWD units is associated with and configured to simultaneously activate the pairing word lines of the two in the group, and wherein the two in the group are laterally offset from each other and spaced apart from each other by an intervening region comprising an insulating panel.

29. The integrated assembly of claim 28, wherein the intermediate region comprises the insulating panel sandwiched between the first conductive plate and the second conductive plate.

30. The integrated assembly of claim 28, wherein the intervening region comprises the insulating panel sandwiched between the plate containing the first semiconductor and the plate containing the second semiconductor.

31. An integrated assembly comprising: Vertically extending letter lines above the base; The memory cells adjacent to the word lines, each of the word lines being associated with a row of the memory cells; the memory cells in each row are stacked vertically on top of each other; and The word line driver circuitry within the substrate; The word line driver circuitry is subdivided among sub-word line driver SWD units; each of the SWD units is associated with at least two of the word lines and configured to simultaneously activate the at least two of the word lines. Each of the SWD units is configured to simultaneously activate at least four of the word lines; and Each of the SWD units is configured to activate all four word lines simultaneously; The four word lines simultaneously activated by the SWD unit are considered to be associated with this SWD unit; wherein each of the SWD units contains a CMOS circuit system below the center two of the four word lines associated with it, and contains a redistributed circuit system extending from the CMOS circuit system to the outer two of the four word lines associated with it.

32. An integrated assembly comprising: Vertically extending letter lines above the base; The memory cells adjacent to the word lines, each of the word lines being associated with a row of the memory cells; the memory cells in each row are stacked vertically on top of each other; and The word line driver circuitry within the substrate; The word line driver circuitry is subdivided among sub-word line driver SWD units; each of the SWD units is associated with at least two of the word lines and configured to simultaneously activate the at least two of the word lines. A horizontally extending digital line that extends along the columns of the memory cells; and The digital line extends into the sensing amplifier circuitry within the substrate and is offset laterally from directly below the memory cell.

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