Conductive features of semiconductor devices and methods of forming the same

Abstract

The present disclosure relates generally to conductive features of semiconductor devices and methods of forming the same. One method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and a bottom surface of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different than the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region comprises a uniform mixture of the first conductive material and the second conductive material.

Description

Technical Field

[0001] This disclosure generally relates to the conductive characteristics of semiconductor devices and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is constantly increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a device region on a substrate; forming a first dielectric layer on the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along the sidewalls and bottom surface of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region comprises a homogeneous mixture of the first conductive material and the second conductive material.

[0005] According to another embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a fin protruding from a substrate; forming a gate structure extending along the sidewalls of the fin and over a top surface of the fin; forming a source / drain region adjacent to the gate structure in the fin; forming a first dielectric layer over the source / drain region; forming an opening in the first dielectric layer, wherein the opening exposes a surface of the source / drain region; depositing a liner layer along the sidewalls of the opening and on the exposed surface of the source / drain region, the liner layer comprising a first material; depositing a fill layer on the liner layer, wherein the fill layer comprises a second material different from the first material, wherein the interface between the liner layer and the fill layer has a stepped concentration distribution; and performing an annealing process, wherein after performing the annealing process, the interface between the liner layer and the fill layer has a gradient concentration distribution.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first conductive feature extending through a dielectric layer to physically contact and electrically contact a second conductive feature, wherein the first conductive feature comprises: an outer layer comprising a first conductive material; an inner layer comprising a second conductive material, the second conductive material being different from the first conductive material, wherein the outer layer at least partially surrounds the inner layer; and an interface layer located between the outer layer and the inner layer, the interface layer comprising a homogeneous mixture of the first conductive material and the second conductive material, wherein a region of the interface layer adjacent to the outer layer has a greater concentration of the first conductive material than a region of the interface layer adjacent to the inner layer. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a 3D view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B, Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A and Figure 25B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 26A , Figure 26B , Figure 26C , Figure 26D , Figure 26E and Figure 26F This is a cross-sectional view of an intermediate stage in the manufacturing of conductive features according to some embodiments.

[0011] Figure 27A , Figure 27B and Figure 27C This is a cross-sectional view of the conductive features according to some embodiments.

[0012] Figure 28A , Figure 28B , Figure 28C and Figure 28D This is a cross-sectional view of an intermediate stage in the manufacturing of conductive features with a cap layer according to some embodiments.

[0013] Figure 29A , Figure 29B , Figure 29C and Figure 29D This is a cross-sectional view of the conductive features according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0016] The various embodiments described herein allow for the formation of low-resistance conductive features such as vias and wires. The embodiments described herein allow for the formation of conductive features using a liner layer comprising a first conductive material and a filler layer comprising a second conductive material capable of forming a homogeneous mixture with the first conductive material. Heat treatments such as annealing can be performed to create a smoother interface between the liner layer and the filler layer, which can reduce the resistance of the conductive feature. Forming conductive features in this manner can reduce bending due to seam merging or thermal expansion, which can improve yield and reliability. A capping layer can be formed to increase the contact area of ​​the conductive feature, which can reduce contact resistance. The techniques described herein can form conductive features as part of middle-end-of-line (MEOL) and / or back-end-of-line (BEOL) processes.

[0017] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fin 52 protrudes above the adjacent isolation regions 56. Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate or the semiconductor substrate including the isolation regions. Furthermore, although the fin 52 is shown as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0018] A gate dielectric layer 92 runs along the sidewall of fin 52 and is located above the top surface of fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. A source / drain region 82 is disposed on the opposite side of fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1The reference cross sections used in the following figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction perpendicular to, for example, the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 52 in the direction of current flow between, for example, the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, the following figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs), nanostructured field-effect transistors (NSFETs) (e.g., nanosheets, nanowires, gate-all-around, etc.), etc.

[0020] Figures 2 to 25B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 It shows Figure 1 The reference cross section AA shown is different in that it has multiple fins / FinFETs. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A Along Figure 1 The reference section AA is shown, and Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 14C , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B Along Figure 1 The similar cross-section BB shown is different in that it has multiple fins / FinFETs. Figure 10C and Figure 10D Along Figure 1 The reference cross section CC shown is different in that it has multiple fins / FinFETs.

[0021] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0022] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). The p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 50N and the p-type region 50P.

[0023] exist Figure 3 In this process, fins 52 are formed in the substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0024] The fin can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fin 52. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on the fin 52.

[0025] exist Figure 4 An insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert it into another material (e.g., oxide)), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material 54 is formed such that an excess of the insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fins 52. A filler material, such as the filler material described above, may then be formed on the liner.

[0026] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 from the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etching back, or a combination thereof may be used. This planarization process exposes the fin 52 such that, after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where a mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the mask or the top surfaces of the fin 52 and the insulating material 54 are flush, respectively.

[0027] exist Figure 6In this process, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in the n-type region 50N and p-type region 50P protrude between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 56 can be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess the STI regions 56, such as etching processes selectively targeting the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fins 52). For example, an oxide employing, for example, dilute hydrofluoric acid (dHF) can be used for removal.

[0028] about Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes from the dielectric layer to form the fin. Furthermore, in some embodiments, heteroethelic structures can be used for fin 52. For example, Figure 5 The fin 52 can be recessed, and a different material can be epitaxially grown on the recessed fin 52. In such an embodiment, the fin 52 comprises a recessed material and an epitaxial growth material disposed on the recessed material. In another embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which avoids prior and subsequent implantation, but in-situ doping and implantation doping can be used together.

[0029] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P (e.g., the PMOS region) in the n-type region 50N (e.g., the NMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si). x Ge 1-x(where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0030] Further in Figure 6 In this process, suitable wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0031] In embodiments with different well types, photoresist and / or other masks (not shown) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 52 and STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin coating technique, and the photoresist can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 With about 10 18 cm -3 Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0032] Following implantation into the p-type region 50P, a photoresist is formed over the fins 52 and STI regions 56 within the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16cm -3 Peace Treaty 10 18 cm -3 Between. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0033] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0034] exist Figure 7 In this process, a dummy dielectric layer 60 is formed on fin 52. For example, the dummy dielectric layer 60 can be silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 may be made of other materials that have high etch selectivity relative to the etching of the isolation regions (e.g., STI region 56 and / or dummy dielectric layer 60). For example, the mask layer 64 may comprise one or more layers of silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown as covering only the fin 52. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the STI region 56, extends over the STI region, and extends between the dummy gate layer 62 and the STI region 56.

[0035] Figures 8A to 16B Various additional steps for manufacturing the devices of the embodiments are shown. Figures 8A to 16B Features of either the n-type region 50N or the p-type region 50P are shown. For example, Figures 8A to 16B The structure shown can be applied to both n-type region 50N and p-type region 50P. The differences in the structure of n-type region 50N and p-type region 50P (if any) are described in the text accompanying each figure.

[0036] exist Figure 8A and Figure 8B In this process, acceptable photolithography and etching techniques can be used to process mask layer 64 (see...). Figure 7 The mask 74 is patterned to form a dummy gate layer 62. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique to form the dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to separate each dummy gate 72 from adjacent dummy gate entities. The dummy gate 72 may also have a length direction substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0037] Further in Figure 8A and Figure 8B In this process, a gate sealing spacer 80 can be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. The gate sealing spacer 80 can be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0038] After the gate sealing spacer 80 is formed, implantation for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different device types, the process is similar to the above. Figure 6 The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 52 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have a doping density of approximately 10. 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair injection damage and reactivate the injected impurities.

[0039] exist Figure 9A and Figure 9BIn this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0040] Note that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be employed, such as leaving the gate seal spacer 80 uncerased before forming the gate spacer 86, creating an "L-shaped" gate seal spacer, forming and removing the spacers, etc. Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device can be formed before forming the gate seal spacer 80, while the LDD region for a p-type device can be formed after forming the gate seal spacer 80.

[0041] exist Figure 10A and Figure 10B In the fin 52, epitaxial source / drain regions 82 are formed. The epitaxial source / drain regions 82 are formed in the fin 52 such that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fin 52 and may also extend through the fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 82 can be selected to apply stress in the corresponding channel region 58, thereby improving performance.

[0042] The epitaxial source / drain region 82 in the n-type region 50N can be formed by masking the p-type region 50P and etching the source / drain region of the fin 52 in the n-type region 50N to form a recess in the fin 52. Then, the epitaxial source / drain region 82 in the n-type region 50N is epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon-phosphorus, etc. The epitaxial source / drain region 82 in the n-type region 50N can have a surface protruding from the corresponding surface of the fin 52 and can have a facet.

[0043] The epitaxial source / drain region 82 in the p-type region 50P can be formed by masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a recess in the fin 52. Then, the epitaxial source / drain region 82 in the p-type region 50P is epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P can include a material for applying compressive strain in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 82 in the p-type region 50P can have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0044] The epitaxial source / drain regions 82 and / or fins 52 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have approximately 10-1 19 cm -3 Peace Treaty 10 21 cm -3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0045] As a result of the epitaxial process used to form the epitaxial source / drain regions 82 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions has small planes that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these small planes cause adjacent source / drain regions 82 of the same FinFET to merge, such as... Figure 10C As shown. In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as... Figure 10D As shown. In Figure 10C and Figure 10D In the illustrated embodiment, the gate spacer 86 is formed to cover the extension of the sidewall of the fin 52 above a portion of the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 86 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 56.

[0046] exist Figure 11A and Figure 11B In Figure 10A and Figure 10BA first interlayer dielectric (ILD) 88 is deposited on the structure shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, mask 74, and gate spacer 86. CESL 87 may include a dielectric material that may have a lower etch rate than the material of the first ILD 88 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0047] exist Figure 12A and Figure 12B In this process, a planarization process (e.g., CMP) can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. This planarization process may also remove the mask 74 over the dummy gate 72, as well as portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After this planarization process, the top surfaces of the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0048] exist Figure 13A and Figure 13BIn one or more etching steps, the dummy gate 72 and mask 74 (if present) are removed to form a recess 90. A portion of the dummy dielectric layer 60 within the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 while etching little or no of the first ILD 88 or gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 can then be optionally removed after the dummy gate 72 has been removed.

[0049] exist Figure 14A and Figure 14B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 14C It shows Figure 14B A detailed view of region 89. A gate dielectric layer 92 is deposited in the recess 90, for example, on the top surface and sidewalls of fin 52 and on the sidewalls of gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 comprises a silicon oxide interface layer formed by thermal oxidation or chemical oxidation, and a high-k dielectric material thereon, such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, metal oxides or silicates. The gate dielectric layer 92 may include a dielectric layer with a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In an embodiment in which a portion of the dummy gate dielectric 60 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy gate dielectric 60 (e.g., SiO2).

[0050] Gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the remaining portion of the recess 90. Gate electrodes 94 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in Figure 14B A single-layer gate electrode 94 is shown, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler material 94C, such as Figure 14C As shown. After filling the recess 90, a planarization process such as CMP can be performed to remove excess material from the gate electrode 94 and the gate dielectric layer 92 above the top surface of the ILD 88. The remaining material from the gate electrode 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as the “gate stack”. The gate and the gate stack can extend along the sidewalls of the channel region 58 of the fin 52.

[0051] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed by different processes, such that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0052] In some embodiments, a gate mask (not explicitly shown) is formed over a gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask includes recessing the gate stack to form a recess directly above the gate stack and between opposing portions of the gate spacers 86. The recess may then be filled with a gate mask comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), followed by a planarization process to remove excess dielectric material extending above the first ILD 88.

[0053] exist Figure 15A and Figure 15BIn this process, a second ILD 102 is deposited on top of a first ILD 88. In some embodiments, the second ILD 102 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 102 may be a material similar to that of the first ILD 88 and may be formed in a similar manner. For example, the second ILD 102 may be formed of a dielectric material such as oxide, PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD or PECVD. In some embodiments, an optional etch stop layer 100 is formed prior to the deposition of the second ILD 102. The etch stop layer 100 may comprise a dielectric material whose etch rate may be lower than that of the overlying second ILD 102 material, such as silicon nitride, silicon oxynitride, etc.

[0054] Figures 16A to 20B A conductive feature 108 according to some embodiments is shown (see Figure 20B The conductive feature 108 provides an electrical connection to the corresponding epitaxial source / drain region 82 and can be considered in some cases as a "source / drain contact plug" or the like. In some embodiments, this is achieved through a first conductive material 104 (see...) Figures 17A-17B A second conductive material 106 (see above) is deposited on top of the material. Figures 18A-18B The first conductive material 104 is used to form the conductive feature 108. In this way, the first conductive material 104 can be an outer layer that at least partially surrounds the inner layer of the second conductive material 106. In some cases, the first conductive material 104 serves as a liner layer to improve the adhesion of the second conductive material 106. In this way, in some cases, the second conductive material 106 can be considered a "filler layer". In some embodiments, after depositing the second conductive material 106, a thermal process 107 is performed (see...). Figures 19A-19B The first conductive material 104 and the second conductive material 106 form a hybrid interface 105, which can reduce the resistance of the conductive feature 108.

[0055] Figure 16A and Figure 16BA patterning process for a second ILD 102, an etch stop layer 100, a first ILD 88, and a CESL 87, according to some embodiments, is illustrated to form an opening 103. The opening 103 may expose the surface of the source / drain region 82. Patterning can be performed using acceptable photolithography and etching techniques. For example, a photoresist can be formed on the second ILD 102 and patterned. The photoresist can be formed using, for example, a spin coating technique and can be patterned using acceptable photolithography techniques. One or more suitable etching processes can be performed using the patterned photoresist as an etching mask to form the opening 103. The one or more etching processes may include wet etching processes and / or dry etching processes. In some embodiments, the one or more etching processes may be performed using etchants such as CF4, CHF3, CH2F2, C4F6, C4F8, Ar, O2, N2, H2, etc., or combinations thereof. Figures 16A-16B The opening 103 is shown as having a substantially vertical sidewall, but in other embodiments, the opening 103 may have an inclined sidewall, a curved sidewall, or another sidewall profile.

[0056] refer to Figure 17A and Figure 17B According to some embodiments, a first conductive material 104 is deposited in the opening 103. In some embodiments, a cleaning process may be performed before the opening 103 is filled with the first conductive material 104. In some embodiments, the cleaning process may be using materials including H2, BCl3, NF3, HF, HCl, SiCl4, Cl2, SF6, CF4, and CH4. x F y Plasma cleaning processes using process gases such as He, Ar, or combinations thereof. Other cleaning processes are also possible.

[0057] In some embodiments, the first conductive material 104 may include one or more metallic materials, such as Ru, Ir, Ni, Os, Rh, Al, Mo, W, Co, Cu, Ag, combinations thereof, etc. The first conductive material 104 may be deposited using suitable techniques such as CVD, PVD, ALD, electrochemical plating processes, chemical plating processes, combinations thereof, etc. Other materials or deposition techniques are also possible. In some embodiments, the first conductive material 104 is conformally deposited as a layer on the sidewall and bottom surfaces of the opening 103, for example, on the exposed surface of the source / drain region 82. The first conductive material 104 may also be deposited on the second ILD 102. In some embodiments, the first conductive material 104 is deposited to a sufficient thickness to allow continuous coverage of the sidewall and bottom surfaces of the opening 103. In some embodiments, the first conductive material 104 is deposited to a sufficient thickness to allow deposition of the second conductive material 106 thereon without forming seams or voids. For example, in some embodiments, the first conductive material 104 may be deposited to a thickness of approximately [missing information]. to approximately The thickness is within a certain range, but other thicknesses are also possible. In some cases, different regions of the first conductive material 104 within the opening 103 may have different thicknesses.

[0058] In some cases, if one or more dimensions (e.g., size) of a conductive feature formed of a metallic material are approximately equal to or smaller than the mean free path of electrons of that metallic material, the conductive feature may have increased resistance. For example, in some cases, a thin film of metallic material (e.g., having a thickness of about 10 nm or less, but other thicknesses are also possible) may have a higher resistivity than a bulk metallic material. This increase in resistivity of small feature sizes or thin films may be due to, for example, electron scattering effects. Therefore, in some cases, using a metallic material with a relatively small mean free path of electrons can reduce the resistance of some relatively small conductive features. Thus, in some embodiments, the first conductive material 104 may include a metallic material with a relatively small mean free path of electrons. For example, in some embodiments, the metallic material of the first conductive material 104 may include metals such as Rh, Ir, Ru, Ni, Os, Mo, etc., which have a smaller mean free path of electrons than other metals such as W, Co, Cu, Ag, etc. For example, in some embodiments, the metallic material of the first conductive material 104 is Ru, but other metallic materials may also be used in other embodiments. In this way, the selection of the metallic material of the first conductive material 104 allows for a reduction in the subsequently formed conductive feature 108 (see [reference]). Figure 20B The resistance of ).

[0059] In some embodiments where the first conductive material 104 includes Ru, CVD, PECVD, ALD, etc., can be used to deposit the first conductive material 104. In some embodiments, a suitable precursor gas can be used to perform the deposition process, such as Ru(CO)5, Ru3(CO). 12 The precursor gas may contain RuCl3, Ru(od)3, bis(cyclopentadienyl)ruthenium(II), Ru(CO)3C6H8, Ru(CO)2(tmhd)2, Ru(EtCp)2, Ru(CO)2(acac)2, Ru(C6H6)(C6H8), Ru(DMBD)(CO)3, amidamate-based or hexadienyl Ru precursors, or combinations thereof. In some embodiments, the precursor gas may have a flow rate in the range of about 10 sccm to about 100 sccm. In some embodiments, in addition to the precursor gas, a carrier gas and / or additional process gas may be used during deposition. The carrier gas may include N2, Ar, CO, O2, mixtures thereof, etc. The carrier gas may have a flow rate in the range of about 50 sccm to about 500 sccm. The additional process gas may include H2, O2, NH3, mixtures thereof, etc. The additional process gas may have a flow rate in the range of about 100 sccm to about 1000 sccm. In some embodiments, the deposition process can be performed at a process temperature ranging from about 75°C to about 300°C. In some embodiments, the deposition process can be performed at a process pressure ranging from about 0.1 mTorr to about 10 mTorr. Other deposition techniques or parameters are also possible.

[0060] In some embodiments where the first conductive material 104 includes Os, the first conductive material 104 may use a suitable precursor gas (e.g., Os3(CO)). 12 (etc.) are deposited via CVD, PECVD, ALD, etc. In some embodiments where the first conductive material 104 includes Rh, the first conductive material 104 can use a suitable precursor gas (e.g., Rh6(CO)). 16 (etc.) are deposited via CVD, PECVD, ALD, etc. In some embodiments where the first conductive material 104 includes Mo, the first conductive material 104 can use a suitable precursor gas (e.g., MoF6, Mo(CO)6, MoCl5, MoO). x Cl y Deposition can be achieved through CVD, PECVD, ALD, etc. Other materials and precursor gases are also possible.

[0061] exist Figure 18A and Figure 18BIn some embodiments, a second conductive material 106 is deposited on a first conductive material 104. In some embodiments, the second conductive material 106 is deposited on the first conductive material 104 and fills the opening 103. The first conductive material 104 may also be deposited on a second ILD 102. In some embodiments, the second conductive material 106 may include one or more metallic materials, such as Ru, Ir, Ni, Os, Rh, Al, Mo, W, Co, Cu, Ag, combinations thereof, etc. In some embodiments, the second conductive material 106 is a different material from the first conductive material 104. In some embodiments, the second conductive material 106 may be a material less prone to fusion than the first conductive material 104. By using a second conductive material 106 that is less prone to fusion to fill the opening 103, the effects of fusion, such as stress or bending, can be reduced. As an example, in some embodiments, the second conductive material 106 may be Co, which is relatively less prone to fusion, and the first conductive material 104 may be Ru, which is relatively more prone to fusion. This is an example, and other materials or combinations of materials may be used in other embodiments.

[0062] In some cases, the presence of the first conductive material 104 allows the second conductive material 106 to adhere better within the opening 103. In some embodiments, the second conductive material 106 may have a larger mean free path of electrons or a larger resistivity than the first conductive material 104. In some embodiments, the second conductive material 106 may have a smaller coefficient of thermal expansion (CTE) than the first conductive material 104, as described in more detail below. In some embodiments, the second conductive material 106 is a material that can form a homogeneous mixture with the first conductive material 104, as described in more detail below.

[0063] The second conductive material 106 can be deposited using suitable techniques such as CVD, PVD, ALD, electrochemical plating, chemical plating, or combinations thereof. Other materials or deposition techniques are also possible. In some embodiments, the first conductive material 104 is deposited to a sufficient thickness to fill the opening 103 without forming seams or voids. For example, in some embodiments, the second conductive material 106 may be deposited to approximately [a thickness not specified in the original text]. to approximately The thickness is within the range, but other thicknesses are also possible. In some embodiments, the ratio of the thickness of the first conductive material 104 to the thickness of the second conductive material 106 may be in the range of about 1:1.5 to about 1:9, but other ratios are also possible.

[0064] In some embodiments, the second conductive material 106 may be a material having a smaller coefficient of thermal expansion (CTE) than the first conductive material 104. In some cases, materials with a relatively high CTE can cause stress or bending (e.g., “thermal buckling”) during subsequent processing at higher temperatures, for example, during annealing or other processing steps. In some cases, forming conductive features with a conductive material having a relatively high CTE can lead to stress, bending, and process defects due to thermal expansion. Therefore, by using both a first conductive material 104 with a relatively large CTE and a second conductive material 106 with a relatively small CTE to form conductive features, stress or bending due to thermal expansion can be reduced, which can improve yield, device reliability, or device performance. As an example, in some embodiments, the first conductive material 104 may be Ru with a relatively large CTE, and the second conductive material 106 may be Co with a relatively small CTE. This is an example, and other materials or combinations of materials may be used in other embodiments.

[0065] In some embodiments where the second conductive material 106 includes Co, the second conductive material 106 may use a suitable precursor gas (e.g., Co4(CO)). 12 Materials such as Co2(CO)8, W, etc., can be deposited using CVD, PECVD, ALD, etc. In some embodiments where the second conductive material 106 includes W, the second conductive material 106 can be deposited using a suitable precursor gas (e.g., W(CO)6, W(F)6, etc.) via CVD, PECVD, ALD, etc. Other materials and precursor gases are also possible.

[0066] exist Figures 19A-19B In some embodiments, a thermal process 107 is performed on a first conductive material 104 and a second conductive material 106. In some embodiments, the thermal process 107 promotes the interdiffusion of the first conductive material 104 and / or the second conductive material 106, which can create a mixing interface 105 between the first conductive material 104 and the second conductive material 106. The mixing interface 105 includes a region in which both the first conductive material 104 and the second conductive material 106 are present (e.g., having a non-zero concentration). As an example, performing the thermal process 107 can cause a steep (e.g., stepped) concentration distribution (e.g., as shown in the image) between the first conductive material 104 and the second conductive material 106. Figures 18A-18B As shown, the concentration distribution becomes a smoother (e.g., gradient) distribution between the first conductive material 104 and the second conductive material 106 (e.g., as shown). Figures 19A-19B(As shown in the mixing interface 105). In some embodiments, the mixing interface 105 is defined by a region of the first conductive material 104 and / or a region of the second conductive material 106. In some embodiments, during the thermal process 107, the first conductive material 104 may diffuse into the second conductive material 106 up to approximately [amount missing]. to approximately The distance within the range. In some embodiments, during the thermal process 107, the second conductive material 106 can diffuse into the first conductive material 104 up to approximately [distance missing]. to approximately The distance within the range. In this way, in some embodiments, the hybrid interface 105 may have approximately to approximately Width within the range. Other diffusion distances or widths of the mixing interface 105 are also possible.

[0067] In some embodiments, the first conductive material 104 and the second conductive material 106 can be different materials capable of forming a homogeneous mixture. In some embodiments, the first conductive material 104 and the second conductive material 106 can form a homogeneous mixture in any proportion at the operating pressure and / or operating temperature of the device. For example, Ru and Co can form a homogeneous mixture in any proportion at atmospheric pressure, but other materials are also possible. In other embodiments, the first conductive material 104 and the second conductive material 106 can form a homogeneous mixture in a certain proportion within a certain temperature or pressure range. In some cases, the homogeneous mixture of the first conductive material 104 and the second conductive material 106 can form a mixing interface 105 having a smoother (e.g., less steep) concentration distribution between the first conductive material 104 and the second conductive material 106, for example, having a gradient concentration distribution. In some cases, forming a homogeneous mixing interface 105 with a gradient concentration distribution in this way can reduce interface scattering of electrons flowing between the first conductive material 104 and the second conductive material 106. For example, a homogeneous mixing interface 105 with a gradient concentration distribution can have significantly smaller electron scattering compared to an interface with a steep concentration distribution. By reducing electron scattering in this way, the resistance of the conductive feature formed by both the first conductive material 104 and the second conductive material 106 can be reduced by performing the thermal process 107 as described herein. This allows conductive features to be formed from multiple conductive materials without significantly increasing resistance.

[0068] In some embodiments, the thermal process 107 may be, for example, an annealing process, such as a rapid thermal annealing (RTA) process. In some embodiments, the thermal process 107 may be performed at a temperature ranging from about 100°C to about 1000°C. In some embodiments, the thermal process 107 may be performed for a duration ranging from about 1 second to about 300 seconds. In some embodiments, the thermal process 107 may be performed in a gaseous environment including N2, He, Ar, H2, synthesis gases (e.g., 5% by volume H2 in N2), mixtures thereof, etc. Other temperatures, durations, or other process conditions for the thermal process 107 are also possible.

[0069] exist Figures 20A-20B In some embodiments, a planarization process is performed to remove excess first conductive material 104 and second conductive material 106 and form conductive feature 108. The planarization process can be a polishing process, a CMP process, etc. In some embodiments, after performing the planarization process, the surfaces of conductive feature 108 and second ILD 102 can be substantially flush. Figures 20A-20B The conductive feature 108 is shown as having substantially vertical sidewalls, but in other embodiments, the conductive feature 108 may have sloping sidewalls, curved sidewalls, or another sidewall profile.

[0070] The conductive feature 108 may include a region of a first conductive material 104, a region of a second conductive material 106, and / or a mixing interface 105 (e.g., a region including a mixture of both the first conductive material 104 and the second conductive material 106). For example, in some embodiments, the conductive feature 108 includes an outer region of the first conductive material 104 that at least partially surrounds an inner region of the second conductive material 106, and the mixing interface 105 extends between the outer region of the first conductive material 104 and the inner region of the second conductive material 106. In other embodiments, the conductive feature 108 may include only the mixing interface 105, only the mixing interface 105 and the first conductive material 104, or only the mixing interface 105 and the second conductive material 106. In some embodiments, the mixing interface 105 extends from the first conductive material 104 near a first side of the conductive feature 108 to the first conductive material 104 near a second side of the conductive feature 108 opposite to the first side. In some embodiments, the mixing interface 105 extends completely from the first side of the conductive feature 108 to the second side of the conductive feature 108 opposite to the first side. In some embodiments, the hybrid interface 105 extends to the bottom of the conductive feature 108 (e.g., to the corresponding source / drain region 82). In some embodiments, after a planarization process is performed, the top surface of the conductive feature 108 may include a first conductive material 104, a second conductive material 106, and / or the exposed surface of the hybrid interface 105.

[0071] Figures 20A to 23B Conductive features 114A, 114B, and 114C according to some embodiments are shown (see [link]). Figures 23A-23B The conductive feature 114A provides an electrical connection to the gate electrode 94 of the corresponding gate stack, and in some cases can be considered as a "gate contact plug," etc. The conductive feature 114B provides an electrical connection to the corresponding conductive feature 108, and in some cases can be considered as a "conductive via," etc. The conductive feature 114C is electrically connected to both the conductive feature 108 and the gate electrode 94. Figures 23A-23B In this embodiment, conductive features 114A, 114B, and 114C are shown in the same plane, but in other embodiments, conductive features 114A, 114B, and / or 114C may be formed in different planes. Figures 20A-23B The process shown is an example, and conductive features 114A-C can be formed using any suitable process, such as damascene, dual damascene, or other processes.

[0072] exist Figure 21A and Figure 21B In this process, a dielectric layer 112 is deposited over the second ILD 102 and the conductive feature 108. In some embodiments, the dielectric layer 112 is a flowable film formed by a flowable CVD method. In some embodiments, the dielectric layer 112 may be a material similar to that of the first ILD 88 or the second ILD 102, and may be formed in a similar manner. For example, the dielectric layer 112 may be formed of a dielectric material such as oxide, PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD or PECVD. The dielectric layer 112 may be another material beyond these examples. In some cases, the dielectric layer 112 may be considered a “third ILD”. In some embodiments, an optional etch stop layer 110 is formed prior to the deposition of the dielectric layer 112. The etch stop layer 110 may be similar to that for the etch stop layer 100 (see [link to etch stop layer 100]). Figures 15A-15B The material described may be similar to that used in the etch stop layer 100 and may be formed using similar techniques, or the etch stop layer 110 may be a different material than that described for the etch stop layer 100.

[0073] Figure 22A and Figure 22BA patterning process for a dielectric layer 112, an etch stop layer 110, a second ILD 102, and an etch stop layer 100 according to some embodiments is illustrated to form openings 113A-C. Openings 113A-C may expose the surfaces of a gate electrode 94 and / or a conductive feature 108. For example, opening 113A may expose the surface of the gate electrode 94, and opening 113B may expose the surface of the conductive feature 108. In some embodiments, opening 113C may expose the surface of the gate electrode 94, the surface of the conductive feature 108, and the top surface of the second ILD 102.

[0074] Patterning of openings 113A-C can be performed using one or more acceptable photolithography and etching techniques. For example, a photoresist can be formed on dielectric layer 112 and patterned. The photoresist can be formed using, for example, spin coating and can be patterned using acceptable photolithography techniques. The patterned photoresist can be used as an etching mask to perform one or more suitable etching processes to form openings 113A-C. In some embodiments, one or more etching processes may include wet etching processes and / or dry etching processes, which may be similar to those previously described for forming opening 103 (see...). Figures 16A-16B The openings 113A, 113B and / or 113C may be patterned simultaneously or in separate patterning steps. Figures 22A-22B The openings 113A-C are shown as having substantially vertical sidewalls, but in other embodiments, the openings 113A-C may have sloping sidewalls, curved sidewalls, or other sidewall profiles.

[0075] exist Figure 23A and Figure 23BIn some embodiments, conductive material is deposited in openings 113A-C to form conductive features 114A-C. The conductive material fills the openings 113A-C to form conductive features 114A-C. In some embodiments, the conductive material may include one or more metallic materials, such as Ru, Ir, Ni, Os, Rh, Al, Mo, W, Co, Cu, Ag, combinations thereof, etc. The conductive material can be deposited using suitable techniques such as CVD, PVD, ALD, electrochemical plating processes, chemical plating processes, combinations thereof, etc. Other materials or deposition techniques are also possible. In some embodiments, the conductive material is similar to the first conductive material 104 or the second conductive material 106 of conductive feature 108 and can be formed in a similar manner. For example, in some embodiments, conductive features 114A-C include Ru and Co, and the conductive material is Ru or Co. Other materials or combinations of materials are also possible. In other embodiments, the conductive material is different from the first conductive material 104 and / or the second conductive material 106. The conductive material may be deposited on the dielectric layer 112. A planarization process (e.g., grinding, CMP, etc.) can be performed to remove excess conductive material from the dielectric layer 112, and the surfaces of the dielectric material 112 and the conductive features 114A-C can be substantially flush. Figures 23A-23B The conductive features 114A-C are shown as having substantially vertical sidewalls, but in other embodiments, the conductive features 114A-C may have sloping sidewalls, curved sidewalls, or other sidewall profiles.

[0076] Figure 24A and Figure 24B The formation of conductive features 115A-C, comprising a first conductive material 116 and a second conductive material 118, according to some embodiments is illustrated. Conductive features 115A-C are similar to... Figures 23A-23B The conductive features 114A-C differ from those 115A-C in that they are formed from more than one conductive material. In some embodiments, conductive features 115A-C are formed from a first conductive material 116 and a second conductive material 118. The first conductive material 116 may be used in conjunction with the first conductive material 104 (see [link to documentation]). Figures 17A-17B The material is similar to the material described, and can be deposited using a similar technique. The second conductive material 118 can be the same as that used for the second conductive material 106 (see...). Figures 18A-18B The materials described are similar to those described and can be deposited using similar techniques. Other materials and deposition techniques are also possible. The first conductive material 116 and / or the second conductive material 118 of conductive features 115A-C may be the same as or different from the first conductive material 104 and / or the second conductive material 106 of conductive feature 108 below.

[0077] In some embodiments, conductive features 115A-C are formed using a process similar to that previously described for conductive feature 108. For example, conductive features 115A-C may be formed by depositing a first conductive material 116 within openings 113A-C, and then depositing a second conductive material 118 on top of the first conductive material 116. In some embodiments, after depositing the second conductive material 118, a thermal process is performed to form a hybrid interface 117 between the first conductive material 116 and the second conductive material 118, which can reduce the resistance of conductive features 115A-C. The thermal process may be similar to the previously described thermal process 107, and the hybrid interface 117 may have the same characteristics as the hybrid interface 105 previously described (see [link to previous description]). Figures 19A-19B Similar characteristics to those described above. In some embodiments, a first thermal process is performed to form a hybrid interface 105 of conductive features 108 before forming conductive features 115A-C. A second thermal process is then performed to form a hybrid interface 117 of conductive features 115A-C. In other embodiments, a single thermal process is performed to form both the hybrid interface 105 of conductive features 108 and the hybrid interface 117 of conductive features 115A-C. By forming conductive features 115A-C in this manner, conductive features 115A-C can have similar advantages to those previously described for conductive features 108, such as improved reliability and reduced resistance.

[0078] Figure 25A and Figure 25B The formation of conductive features 122A-C and conductive features 128A-C according to some embodiments is shown. Figures 25A-25B The structure shown can then be derived from Figures 23A-23B The structure shown is manufactured using [the specific process]. In other embodiments, [the structure is] similar to [the previous one]. Figures 25A-25B The structure shown can be subsequently derived from similar structures. Figures 24A-24B The structure shown is fabricated. Conductive features 122A-C and conductive features 128A-C are electrically connected to conductive features 114A-C and can provide additional electrical interconnections within the structure. In this way, conductive features 122A-C and / or conductive features 128A-C may include electrical wiring, conductive vias, conductive lines, etc. In some embodiments, an additional conductive feature layer may be formed on conductive features 128A-C. In some embodiments, one or both of conductive features 122A-C or conductive features 128A-C are not formed. Conductive features 122A-C and conductive features 128A-C may be formed using suitable processes, such as damascene processes, dual damascene processes, or other processes. In some embodiments, conductive features 122A-C and / or conductive features 128A-C may be formed using a process similar to that described for forming conductive features 115A-C.

[0079] As an example process for forming conductive features 122A-C, a dielectric layer 120 can be formed over the dielectric layer 112 and conductive features 114A-C. The dielectric layer 120 can be similar to the dielectric layer 112 and can be formed using similar techniques. An optional etch stop layer 118, which can be similar to the previously described etch stop layer 110, can be formed between the dielectric layer 112 and the dielectric layer 120. Other materials or techniques are also possible. Openings can then be patterned in the dielectric layer 120 and the etch stop layer 118 to expose the surfaces of the conductive features 114A-C. A conductive material can be deposited within the openings to form the conductive features 122A-C. The conductive material can be similar to that used for conductive features 114A-C (see [link to documentation]). Figures 23A-23B The material described herein can be formed in a similar manner. Other conductive materials are also possible. A planarization process can be performed to remove excess conductive material from the dielectric layer 120. Figures 25A-25B The conductive features 122A-C are shown as having substantially vertical sidewalls, but in other embodiments, the conductive features 122A-C may have sloping sidewalls, curved sidewalls, or other sidewall profiles.

[0080] In some embodiments, conductive features 122A-C may be in conjunction with conductive features 115A-C (see...). Figures 24A-24B ), or below for Figures 26A-26F The described conductive feature 210 is formed in a similar manner. For example, a first conductive material can be deposited within the opening, and then a second conductive material can be deposited on top of the first conductive material. A thermal process can then be performed to form a hybrid interface between the first and second conductive materials. The first conductive material can be similar to first conductive material 116, the second conductive material can be similar to second conductive material 118, the hybrid interface can be similar to hybrid interface 117, and the thermal process can be similar to thermal process 107. Other materials or techniques are also possible.

[0081] As an example process for forming conductive features 128A-C, a dielectric layer 126 may be formed over the dielectric layer 120 and conductive features 122A-C. The dielectric layer 126 may be similar to the dielectric layer 112 and can be formed using similar techniques. An optional etch stop layer 124, which may be similar to the previously described etch stop layer 110, may be formed between the dielectric layer 120 and the dielectric layer 126. Other materials or techniques are also possible. Openings may then be patterned in the dielectric layer 126 and the etch stop layer 124 to expose the surfaces of the conductive features 122A-C. A conductive material may be deposited within the openings to form the conductive features 128A-C. The conductive material may be similar to that used for conductive features 114A-C (see [link to documentation]). Figures 23A-23BThe material described herein can be formed in a similar manner. Other conductive materials are also possible. A planarization process can be performed to remove excess conductive material from the dielectric layer 126. Figures 25A-25B The conductive feature 128 is shown as having substantially vertical sidewalls, but in other embodiments, the conductive feature 128 may have sloping sidewalls, curved sidewalls, or other sidewall profiles.

[0082] In some embodiments, conductive features 128A-C may be in conjunction with conductive features 115A-C (see...). Figures 24A-24B ), or below for Figures 26A-26F The described conductive feature 210 is formed in a similar manner. For example, a first conductive material can be deposited within the opening, and then a second conductive material can be deposited on top of the first conductive material. A thermal process can then be performed to form a hybrid interface between the first and second conductive materials. The first conductive material can be similar to first conductive material 116, the second conductive material can be similar to second conductive material 118, the hybrid interface can be similar to hybrid interface 117, and the thermal process can be similar to thermal process 107. Other materials or techniques are also possible.

[0083] Go to Figures 26A to 26F According to some embodiments, a conductive feature 210 is shown (see [reference]). Figures 26E-26F This is an intermediate step. The conductive feature 210 can be, for example, a conductive wire, a conductive via, etc. In some embodiments, the conductive feature 210 forms an electrical connection between the lower conductive feature 202 and the upper conductive feature 216, such as... Figure 26F As shown. In some embodiments, the conductive feature 210 may be formed as part of a back-to-end (BEOL) process or as part of a mid-end (MEOL) process. In some embodiments, Figure 20B The conductive feature 108 shown Figures 24A-24B The conductivity characteristics shown are 115A-C. Figures 25A-25B The conductive characteristics shown are 122A-C. Figures 25A-25B The conductive features 128A-C shown herein, and / or other conductive features described herein, may be formed similarly to conductive feature 210 and using similar techniques. In some embodiments, conductive feature 210 is used in conjunction with conductive feature 108 (see [link to conductive feature 108]). Figures 20A-20B The technology described above is similar to that used to form the conductive feature 108. In this way, the advantages previously described for conductive feature 108 can be applied to conductive feature 210 formed as part of a BEOL or MEOL process, etc.

[0084] Figure 26A An opening 203 of an exposed conductive feature 202 according to some embodiments is shown. Figure 26AThe illustrated structure includes a lower conductive feature 202 formed in dielectric layer 204. The lower conductive feature 202 can be formed using any suitable process, such as damascene, dual damascene, or other processes. Optional etch stop layer 205 and dielectric layer 206 are formed over the lower conductive feature 202, and opening 203 is patterned to expose the lower conductive feature 202. Dielectric layer 204 and / or dielectric layer 206 can be similar to the previously described second ILD 102 or dielectric layer 112 and can be formed using similar techniques. Etch stop layer 205 can be similar to the previously described etch stop layer 110 or etch stop layer 118 and can be formed using similar techniques. (See also: [link to documentation]) Figure 16B ) or opening 113A-C (see Figures 22A-22B The technique described herein is similar to that used to pattern the opening 203. The lower conductive feature 202 can be a conductive line, a conductive via, etc., and can be similar to conductive features 108, 114A-C, 115A-C, 122A-C, 128A-C, or other conductive features described herein, and can be formed using similar techniques. For example, the lower conductive feature 202 can include a single conductive material similar to conductive feature 114A-C, or multiple conductive materials similar to conductive feature 115A-C.

[0085] exist Figure 26B In some embodiments, a first conductive material 207 is deposited in the opening 203 and on the lower conductive feature 202. The first conductive material 207 may be conformally deposited on the sidewalls of the opening 203 and on the exposed surface of the lower conductive feature 202. The first conductive material 207 may be similar to the first conductive material 104 (see...). Figures 17A-17B ) or the first conductive material 116 (see Figures 24A-24B It can be formed using similar techniques. In some embodiments, the first conductive material 207 and the lower conductive feature 202 may be the same material. In other embodiments, the first conductive material 207 is a different material from the lower conductive feature 202.

[0086] exist Figure 26C In some embodiments, a second conductive material 209 is deposited in the opening 203 and on top of the first conductive material 207. The second conductive material 209 may fill the opening 203. The second conductive material 209 may be similar to the second conductive material 106 (see...). Figures 18A-18B ) or second conductive material 118 (see Figures 24A-24B The second conductive material 209 and the lower conductive feature 202 can be formed using similar techniques. In some embodiments, the second conductive material 209 and the lower conductive feature 202 may be the same material. In other embodiments, the second conductive material 209 is a different material from the lower conductive feature 202.

[0087] exist Figure 26D In some embodiments, a thermal process 107 is performed to form a hybrid interface 208. The thermal process 107 may be similar to the previously described thermal process 107 (see [link to previous description]). Figures 19A-19B The hybrid interface 208 is a mixture of the first conductive material 207 and the second conductive material 209, and can be similar to the hybrid interface 105 previously described (see [link]). Figures 19A-19B ).exist Figure 26E In this process, a planarization process (e.g., polishing, CMP, etc.) is performed to remove excess first conductive material 207 and second conductive material 209, thereby forming conductive feature 210. After performing the planarization process, dielectric layer 206 and conductive feature 210 can have substantially flush surfaces. Figures 26E-26F The conductive feature 210 is shown as having substantially vertical sidewalls, but in other embodiments, the conductive feature 210 may have sloping sidewalls, curved sidewalls, or other sidewall profiles, examples of which are described below. Figures 29A-29D Describe it.

[0088] exist Figure 26F In some embodiments, an upper conductive feature 216 is formed on conductive feature 210. The upper conductive feature 216 may be a conductive line, a conductive via, etc. The upper conductive feature 216 can be formed using any suitable process, such as damascene, dual damascene, or other processes. In some embodiments, the upper conductive feature 216 may be similar to the lower conductive feature 202, or other conductive features described herein, and can be formed using similar techniques. For example, the upper conductive feature 216 may include a single conductive material similar to conductive features 114A-C, or multiple conductive materials similar to conductive features 115A-C.

[0089] As an example of forming the upper conductive feature 216, an optional etch stop layer 212 and a dielectric layer 214 may be formed over the conductive feature 210 and the dielectric layer 206. Openings may be patterned to expose the conductive feature 210, and conductive material may be deposited in the openings to form the upper conductive feature 216. The dielectric layer 214 may be similar to the previously described dielectric layer 206 and may be formed using similar techniques. The etch stop layer 212 may be similar to the previously described etch stop layer 205 and may be formed using similar techniques. The conductive material of the upper conductive feature 216 may be the same as or different from the conductive material of the lower conductive feature 202. In some embodiments, the conductive material of the upper conductive feature 216 includes a first conductive material 207 and / or a second conductive material 209.

[0090] In some embodiments, a thermal process may be performed to form a hybrid interface between conductive feature 210 and other conductive features. For example, Figure 27A , Figure 27B and Figure 27C Intermediate steps are shown in forming a hybrid interface 218 between conductive feature 210 and lower conductive feature 202, and forming a hybrid interface 219 between conductive feature 210 and upper conductive feature 216. According to some embodiments, Figure 27A The lower hybrid interface 218 formed between the conductive feature 210 and the lower conductive feature 202 is shown. Figure 27B An upper hybrid interface 219 is shown between conductive feature 210 and upper conductive feature 216, and Figure 27C The lower mixing interface 218 and the upper mixing interface 219 are shown. (For...) Figures 27A-27C The techniques described herein can be applied to other conductive features or structures described herein. By forming a hybrid interface between conductive feature 210 and another conductive feature, the resistance between conductive feature 210 and the other conductive feature can be reduced, which can improve device performance.

[0091] Figure 27A It shows something similar to Figure 26F The structure shown differs in that a lower mixing interface 218 is formed between the conductive feature 210 and the lower conductive feature 202. The material of the lower conductive feature 202 can be selected such that it can form a homogeneous mixture with the first conductive material 207. For example, in some embodiments, the material of the lower conductive feature 202 can be the same as the second conductive material 209. In other embodiments, the material of the lower conductive feature 202 can be different from the second conductive material 209. A process similar to thermal process 107 (see...) can be performed. Figures 19A-19B A thermal process is performed to form the lower hybrid interface 218. In some embodiments, the thermal process to form the lower hybrid interface 218 may be performed after the deposition of the first conductive material 207, and then a separate thermal process (e.g., thermal process 107) may be performed after the deposition of the second conductive material 209 to form the hybrid interface 208. In other embodiments, the thermal process may be performed after the deposition of the second conductive material 209 to form both the lower hybrid interface 218 and the hybrid interface 208.

[0092] Figure 27B It shows something similar to Figure 26F The structure shown differs in that an upper mixing interface 219 is formed between conductive feature 210 and upper conductive feature 216. The material of upper conductive feature 216 may be selected such that it can form a homogeneous mixture with the first conductive material 207. For example, in some embodiments, the material of upper conductive feature 216 may be the same as the second conductive material 209. In other embodiments, the material of upper conductive feature 216 may be different from the second conductive material 209. A process similar to thermal process 107 (see...) can be performed. Figures 19A-19BA thermal process is used to form the upper hybrid interface 219. In some embodiments, a first thermal process (e.g., thermal process 107) may be performed before forming the upper conductive feature 216 to form the hybrid interface 208, and then a second thermal process may be performed after forming the upper conductive feature 216 to form the upper hybrid interface 219. In other embodiments, a single thermal process may be used to form both the upper hybrid interface 219 and the hybrid interface 208 after forming the upper conductive feature 216.

[0093] Figure 27C It shows something similar to Figure 26F The structure shown differs in that both the lower mixing interface 218 and the upper mixing interface 219 are formed. The materials of the lower conductive feature 202 and the upper conductive feature 216 can be selected such that they can form a homogeneous mixture with the first conductive material 207. For example, in some embodiments, the materials of the lower conductive feature 202 and / or the upper conductive feature 216 can be the same as the second conductive material 209. In other embodiments, one or more of the materials of the lower conductive feature 202, the upper conductive feature 216, or the second conductive material 209 can be different. A process similar to thermal process 107 (see...) can be performed. Figures 19A-19B One or more thermal processes can be used to form the lower mixing interface 218 and the upper mixing interface 219. For example, in some embodiments, a first thermal process can be performed to form the lower mixing interface 218, followed by a second thermal process (e.g., thermal process 107) to form the mixing interface 208, and then a third thermal process can be performed to form the upper mixing interface 219. In other embodiments, a first thermal process can be performed to form both the lower mixing interface 218 and the mixing interface 208, and then a second thermal process can be performed to form the upper mixing interface 219. In other embodiments, a first thermal process can be performed to form the lower mixing interface 218, the mixing interface 208, and the upper mixing interface 219, followed by a second thermal process. In other embodiments, a single thermal process can be used to form the lower mixing interface 218, the mixing interface 208, and the upper mixing interface 219 after the upper conductive feature 216 is formed.

[0094] Figures 28A to 28D Intermediate steps for forming conductive features 210 having a cap layer 220 according to some embodiments are shown. Figures 28A-28D The structure shown is similar to Figures 26E-26FThe structure shown differs in that a cap layer 220 is formed and an optional thermal process 227 is performed. The cap layer 220 is a conductive material that can effectively increase the contact area between the conductive feature 210 and the upper conductive feature 216, which can reduce the contact resistance between the conductive feature 210 and the upper conductive feature 216. Furthermore, by performing the optional thermal process 227, a hybrid interface 221 can be formed between the cap layer 220 and the upper conductive feature 216, which can further reduce the contact resistance. [The structure described is for forming...] Figures 28A-28D The capping technique shown can be applied to other conductive features or structures described herein.

[0095] Figure 28A A conductive feature 210 according to some embodiments is shown. Figure 28A The structure shown is similar to Figure 26E The structure shown can be formed in a similar manner. Figure 28B In some embodiments, a cap layer 220 is formed over the conductive feature 210. The material of the cap layer 220 may be selected such that it can form a homogeneous mixture with the first conductive material 207 of the conductive feature 210. For example, in some embodiments, the material of the cap layer 220 may be the same as the material of the second conductive material 209. In other embodiments, the material of the cap layer 220 may be different from the material of the second conductive material 209. The cap layer 220 may be formed having approximately to approximately The thickness is within the range specified, but other thicknesses are also possible. The width of the cap layer 220 can be less than the width of the conductive feature 210, approximately the same as the width of the conductive feature 210, or greater than the width of the conductive feature 210. For example, the width of the cap layer 220 can be in the range of approximately 50% to approximately 95% of the width of the lower conductive feature 210. Other widths are also possible.

[0096] The cap layer 220 can be formed using suitable photolithography and deposition processes. For example, in some embodiments, a photoresist can be formed over the dielectric layer 206 and the conductive feature 210. Openings can then be patterned in the photoresist corresponding to the cap layer 220. Material of the cap layer 220 can then be deposited in the openings and on the conductive feature 210. The material of the cap layer 220 can be deposited using suitable techniques, for example, previously for the first conductive material 104 (see...). Figures 17A-17B ) or second conductive material 106 (see Figures 18A-18B The technique described herein. After depositing the material of the cap layer 220, suitable etching and / or ashing processes, for example, can be used to remove the photoresist and excess material. This is an example process for forming the cap layer 220, and other processes are considered to be within the scope of this disclosure.

[0097] exist Figure 28CIn some embodiments, an upper conductive feature 216 is formed on the cap layer 220. The upper conductive feature 216 may be similar to... Figure 26F The upper conductive feature 216 is shown, and can be formed in a similar manner. In some embodiments, the upper conductive feature 216 may surround and cover the cap layer 220. The material of the upper conductive feature 216 may be selected such that it can form a homogeneous mixture with the material of the cap layer 220. For example, in some embodiments, the material of the upper conductive feature 216 may be the same as the material of the first conductive material 207. In other embodiments, the material of the upper conductive feature 216 may be different from the material of the first conductive material 207. In this way, the upper conductive feature 216 can make electrical contact with the conductive feature 210 at least partially through the cap layer 220, which can reduce resistance.

[0098] exist Figure 28D In some embodiments, an optional thermal process 227 may be performed to form a hybrid interface 221 around the cap layer 220. In some embodiments, the thermal process 227 may include annealing, etc., and may be similar to the previously described thermal process 107 (see [link to previous embodiment]). Figures 19A-19B Thermal process 227 may form a hybrid interface 221 between cap layer 220 and upper conductive feature 216. In some embodiments, thermal process 227 may also form a hybrid interface 221 between cap layer 220 and first conductive material 207. In some embodiments, thermal process 227 is a separate thermal process from thermal process 107. In other embodiments, thermal process 107 has not been previously performed, and thermal process 227 forms both hybrid interface 208 and hybrid interface 221. By forming hybrid interface 221 in this way, the resistance between upper conductive feature 216 and cap layer 220 can be reduced, which can further reduce the resistance between conductive feature 210 and upper conductive feature 216.

[0099] Figures 26A to 28D The conductive feature 210 is shown as having substantially vertical sidewalls; however, in other embodiments, the conductive feature 210 may have sloping sidewalls, curved sidewalls, or other sidewall profiles. As an example, Figure 29A , Figure 29B , Figure 29C and Figure 29D An embodiment in which the conductive feature 210 has different sidewall profiles is shown. Figures 29A-29D The conductive feature 210 shown can be similar to that for Figures 26A to 28D The described conductive feature 210 can be formed using similar techniques. For example, the formation of opening 203 can be controlled (see [link to documentation]). Figure 26A One or more etching processes are used to control the sidewall profile of the conductive feature 210. Figures 29A-29DThe sidewall profile shown is an example, and other sidewall profiles are possible and considered to be within the scope of this disclosure.

[0100] Figure 29A and Figure 29B A conductive feature 210 with a sloping or tapered sidewall profile is shown according to some embodiments. For example, the upper width of the conductive feature 210 may be greater than the lower width. Figure 29A The conductive feature 210 without the cap layer 220 is shown, similar to Figure 26F or Figures 27A-27C The electrical conductivity characteristics shown. Figure 29B The conductive feature 210 with cap layer 220 is shown, similar to Figures 28C-28D The conductive feature 210 and the cap layer 220 are shown. In some cases, the conductive feature 210 with sloping sidewalls may have reduced contact resistance between the conductive feature 210 and the overlying upper conductive feature 216.

[0101] Figure 29C and Figure 29D A conductive feature 210 with a circular or sloping upper sidewall region is shown according to some embodiments. For example, the width of the upper sidewall region of the conductive feature 210 may be greater than the width of the lower sidewall region. Figure 29C The conductive feature 210 without the cap layer 220 is shown, similar to Figure 26F or Figures 27A-27C The electrical conductivity characteristics shown. Figure 29D The conductive feature 210 with cap layer 220 is shown, similar to Figures 28C-28D The conductive feature 210 and the cap layer 220 are shown. In some cases, the conductive feature 210, which has a wider upper sidewall region, may have a reduced contact resistance between the conductive feature 210 and the overlying upper conductive feature 216.

[0102] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning an alternating stack of channel and sacrificial layers. The dummy gate stack and source / drain regions are formed in a manner similar to those described in the embodiments above. After removing the dummy gate stack, the sacrificial layer can be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to those described in the embodiments above, and the replacement gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contacts of the replacement gate structure and source / drain regions can be formed in a manner similar to those described in the embodiments above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0103] The embodiments of this disclosure can achieve advantages. In some embodiments, a second conductive material deposited on a first conductive material can be used to form conductive features such as conductive vias or conductive lines. In some cases, the first conductive material may have a relatively low resistance, which can reduce the overall resistance of the conductive feature. One or both of the conductive materials may have a relatively small mean free path, which can reduce the resistance of smaller conductive features. In some cases, by using a second conductive material in addition to the first conductive material, problematic characteristics of the first conductive material can be reduced. For example, the effects of stress due to thermal expansion or bending due to seams can be reduced or eliminated. In some cases, the first conductive material can act as a "liner" and improve the adhesion of the second conductive material.

[0104] In some embodiments, the first and second conductive materials of the conductive feature may be selected such that a homogeneous mixture can be formed between the two conductive materials. Thermal processes such as annealing may be performed to diffuse the first and second conductive materials and form a mixed interface with a homogeneous phase. In some cases, forming a mixed interface in this manner can reduce the resistance between the first and second conductive materials and may also improve the adhesion between them. In some embodiments, a capping layer may be formed over the conductive feature to increase the contact area and reduce the contact resistance to the overlying feature. The embodiments described herein can also be applied to various features formed during MEOL and / or BEOL processes, such as contact plugs, conductive lines, and / or conductive vias.

[0105] According to one embodiment, a method includes: forming a device region on a substrate; forming a first dielectric layer on the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along the sidewalls and bottom surface of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region comprises a homogeneous mixture of the first conductive material and the second conductive material. In one embodiment, the first conductive material is Ru, and the second conductive material is Co. In one embodiment, the first thermal process diffuses the first conductive material into the second conductive material. In one embodiment, the first thermal process diffuses the second conductive material into the first conductive material. In one embodiment, the first thermal process includes annealing performed at a temperature in the range of 100°C to 1000°C. In one embodiment, the method includes: performing a planarization process to remove excess first conductive material and excess second conductive material; after performing the planarization process, depositing a capping layer on the second conductive material, wherein the capping layer comprises the second conductive material; and forming a first conductive feature covering the capping layer. In one embodiment, the method includes performing a second thermal process to diffuse a capping layer into a first conductive feature. In one embodiment, an opening in the first dielectric layer exposes a surface of the second conductive feature, and the first thermal process diffuses a first conductive material into the second conductive feature.

[0106] According to one embodiment, a method includes: forming a fin protruding from a substrate; forming a gate structure extending along the sidewalls of the fin and over a top surface of the fin; forming a source / drain region adjacent to the gate structure in the fin; forming a first dielectric layer over the source / drain region; forming an opening in the first dielectric layer, wherein the opening exposes a surface of the source / drain region; depositing a liner layer along the sidewalls of the opening and on the exposed surface of the source / drain region, the liner layer comprising a first material; depositing a filler layer on the liner layer, wherein the filler layer comprises a second material different from the first material, wherein the interface between the liner layer and the filler layer has a stepped concentration distribution; and performing an annealing process, wherein after performing the annealing process, the interface between the liner layer and the filler layer has a gradient concentration distribution. In one embodiment, prior to performing the annealing process, the first region of the liner layer does not contain the second material, and the second region of the filler layer does not contain the first material, and after performing the annealing process, the first region and the second region comprise a mixture of the first material and the second material. In one embodiment, the annealing process reduces the contact resistance between the liner layer and the filler layer. In one embodiment, the first material comprises Ru, and the second material comprises Co. In one embodiment, the method includes forming a conductive feature over a liner layer and a filler layer, wherein forming the conductive feature includes depositing a first material layer on the filler layer. In one embodiment, forming the conductive feature further includes depositing a second material layer on the first material layer. In one embodiment, the conductive feature is in solid and electrical contact with a gate structure. In one embodiment, the method includes depositing a second dielectric layer over a first dielectric layer, wherein an opening extends through the second dielectric layer.

[0107] According to one embodiment, a device includes: a first conductive feature extending through a dielectric layer to substantially and electrically contact a second conductive feature, wherein the first conductive feature includes: an outer layer comprising a first conductive material; an inner layer comprising a second conductive material different from the first conductive material, wherein the outer layer at least partially surrounds the inner layer; and an interface layer located between the outer layer and the inner layer, the interface layer comprising a homogeneous mixture of the first and second conductive materials, wherein a region of the interface layer adjacent to the outer layer has a higher concentration of the first conductive material than a region of the interface layer adjacent to the inner layer. In one embodiment, the second conductive feature comprises the second conductive material. In one embodiment, the device includes a third conductive feature substantially and electrically contacting the top surface of the first conductive feature, wherein the third conductive feature comprises a layer of the second conductive material. In one embodiment, the third conductive feature comprises a layer of the first conductive material on top of the layer of the second conductive material.

[0108] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0109] Example 1 is a method of forming a semiconductor device, comprising: forming a device region on a substrate; forming a first dielectric layer on the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along the sidewalls and bottom surface of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region comprises a homogeneous mixture of the first conductive material and the second conductive material.

[0110] Example 2 is the method described in Example 1, wherein the first conductive material is Ru and the second conductive material is Co.

[0111] Example 3 is the method described in Example 1, wherein the first thermal process diffuses the first conductive material into the second conductive material.

[0112] Example 4 is the method described in Example 1, wherein the first thermal process diffuses the second conductive material into the first conductive material.

[0113] Example 5 is the method of Example 1, wherein the first thermal process includes annealing performed at a temperature in the range of 100°C to 1000°C.

[0114] Example 6 is the method of Example 1, further comprising: performing a planarization process to remove excess first conductive material and excess second conductive material; after performing the planarization process, depositing a capping layer on the second conductive material, wherein the capping layer includes the second conductive material; and forming a first conductive feature covering the capping layer.

[0115] Example 7 is the method of Example 6, further comprising: performing a second thermal process to diffuse the capping layer into the first conductive feature.

[0116] Example 8 is the method of Example 1, wherein an opening in the first dielectric layer exposes the surface of the second conductive feature, and wherein the first thermal process diffuses the first conductive material into the second conductive feature.

[0117] Example 9 is a method of forming a semiconductor device, comprising: forming a fin protruding from a substrate; forming a gate structure extending along the sidewalls of the fin and over a top surface of the fin; forming a source / drain region adjacent to the gate structure in the fin; forming a first dielectric layer over the source / drain region; forming an opening in the first dielectric layer, wherein the opening exposes a surface of the source / drain region; depositing a liner layer along the sidewalls of the opening and on the exposed surface of the source / drain region, the liner layer comprising a first material; depositing a fill layer on the liner layer, wherein the fill layer comprises a second material different from the first material, wherein the interface between the liner layer and the fill layer has a stepped concentration distribution; and performing an annealing process, wherein after performing the annealing process, the interface between the liner layer and the fill layer has a gradient concentration distribution.

[0118] Example 10 is the method of Example 9, wherein, prior to performing the annealing process, a first region of the lining layer does not contain the second material, and a second region of the filler layer does not contain the first material, and wherein, after performing the annealing process, the first region and the second region comprise a mixture of the first material and the second material.

[0119] Example 11 is the method described in Example 9, wherein the annealing process reduces the contact resistance between the lining layer and the filler layer.

[0120] Example 12 is the method described in Example 9, wherein the first material comprises Ru and the second material comprises Co.

[0121] Example 13 is the method of Example 9, further comprising: forming a conductive feature over the liner layer and the filler layer, wherein forming the conductive feature comprises depositing a layer of the first material over the filler layer.

[0122] Example 14 is the method described in Example 13, wherein forming the conductive feature further includes depositing a layer of the second material on the first material layer.

[0123] Example 15 is the method described in Example 13, wherein the conductive feature is substantially in contact with and electrically in contact with the gate structure.

[0124] Example 16 is the method of Example 9, further comprising: depositing a second dielectric layer over the first dielectric layer, wherein the opening extends through the second dielectric layer.

[0125] Example 17 is a semiconductor device comprising: a first conductive feature extending through a dielectric layer to physically contact and electrically contact a second conductive feature, wherein the first conductive feature comprises: an outer layer comprising a first conductive material; an inner layer comprising a second conductive material, the second conductive material being different from the first conductive material, wherein the outer layer at least partially surrounds the inner layer; and an interface layer located between the outer layer and the inner layer, the interface layer comprising a homogeneous mixture of the first conductive material and the second conductive material, wherein a region of the interface layer adjacent to the outer layer has a greater concentration of the first conductive material than a region of the interface layer adjacent to the inner layer.

[0126] Example 18 is the device described in Example 17, wherein the second conductive feature includes the second conductive material.

[0127] Example 19 is the device described in Example 17, further comprising: a third conductive feature, the third conductive feature being in solid and electrical contact with the top surface of the first conductive feature, wherein the third conductive feature comprises a layer of the second conductive material.

[0128] Example 20 is the device described in Example 19, wherein the third conductive feature further includes: a layer of the first conductive material on the second conductive material layer.

Claims

1. A method for forming a semiconductor device, comprising: The device region is formed on the substrate; A first dielectric layer is formed over the device region; An opening is formed in the first dielectric layer; A first conductive material is conformally deposited along the sidewalls and bottom surface of the opening; A second conductive material is deposited on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; A first thermal process is performed to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region comprises a homogeneous mixture of the first conductive material and the second conductive material; A planarization process is performed to remove excess first conductive material and excess second conductive material; After performing the planarization process, a capping layer is deposited on the second conductive material, wherein the capping layer comprises the second conductive material; and A first conductive feature is formed around and covering the cap layer.

2. The method according to claim 1, wherein, The first conductive material is Ru, and the second conductive material is Co.

3. The method according to claim 1, wherein, The first thermal process diffuses the first conductive material into the second conductive material.

4. The method according to claim 1, wherein, The first thermal process diffuses the second conductive material into the first conductive material.

5. The method according to claim 1, wherein, The first thermal process includes annealing performed at a temperature in the range of 100°C to 1000°C.

6. The method according to claim 1, further comprising: A second thermal process is performed to diffuse the capping layer into the first conductive feature.

7. The method according to claim 1, wherein, An opening in the first dielectric layer exposes the surface of the second conductive feature, and wherein the first thermal process diffuses the first conductive material into the second conductive feature.

8. A method of forming a semiconductor device, comprising: Forming fins that protrude from the substrate; A gate structure is formed along the sidewalls of the fin and extending above the top surface of the fin; A source / drain region adjacent to the gate structure is formed in the fin; A first dielectric layer is formed on the source / drain region; An opening is formed in the first dielectric layer, wherein the opening exposes the surface of the source / drain region; A liner layer comprising a first material is deposited along the sidewall of the opening and on the exposed surface of the source / drain region. A filler layer is deposited on the lining layer, wherein the filler layer comprises a second material different from the first material, and wherein the interface between the lining layer and the filler layer has a stepped concentration distribution; An annealing process is performed, wherein, after the annealing process is performed, the interface between the lining layer and the filler layer has a gradient concentration distribution; A conductive feature is formed over the liner layer and the filler layer, wherein forming the conductive feature includes: Deposit a layer of the first material on the filler layer; and A second material is deposited on the first material layer, wherein the second material layer surrounds and covers the first material layer.

9. The method according to claim 8, wherein, Before the annealing process is performed, the first region of the lining layer does not contain the second material, and the second region of the filler layer does not contain the first material, wherein, after the annealing process is performed, the first region and the second region comprise a mixture of the first material and the second material.

10. The method according to claim 8, wherein, The annealing process reduces the contact resistance between the lining layer and the filler layer.

11. The method according to claim 8, wherein, The first material includes Ru, and the second material includes Co.

12. The method according to claim 8, wherein, The conductive feature is in physical and electrical contact with the gate structure.

13. The method of claim 8, further comprising: A second dielectric layer is deposited on top of the first dielectric layer, wherein the opening extends through the second dielectric layer.

14. A semiconductor device, comprising: A first conductive feature extends through a dielectric layer to physically and electrically contact a second conductive feature, wherein the first conductive feature includes: Including the outer layer of the first conductive material; The outer layer includes an inner layer of a second conductive material, which is different from the first conductive material, wherein the outer layer at least partially surrounds the inner layer; and An interface layer located between the outer layer and the inner layer, the interface layer comprising a homogeneous mixture of a first conductive material and a second conductive material, wherein the region of the interface layer adjacent to the outer layer has a higher concentration of the first conductive material than the region of the interface layer adjacent to the inner layer; and A third conductive feature, wherein the third conductive feature is in solid and electrical contact with the top surface of the first conductive feature, wherein the third conductive feature comprises: A layer of the second conductive material; and A layer of the first conductive material on top of the second conductive material, wherein the first conductive material surrounds and covers the second conductive material.

15. The device according to claim 14, wherein, The second conductive feature includes the second conductive material.

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