A semiconductor structure and a method of manufacturing the same
By employing a dual-groove manufacturing method in the image sensor manufacturing process, the problems of polysilicon residue and over-etching in the logic and pixel areas are solved, achieving stable isolation and improved conductivity of the semiconductor structure, which is suitable for the manufacturing of image sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2022-04-24
- Publication Date
- 2026-07-24
AI Technical Summary
In the manufacturing process of image sensors, existing technologies struggle to effectively avoid polysilicon residue and over-etching issues caused by the different depths of shallow trench isolation structures in the logic area and pixel area, which affect the quality of the semiconductor structure.
The dual-trench manufacturing method involves forming first and second types of trenches on the substrate and creating steps on both sides of the trenches. By using different etch selectivity ratios and material filling, the protrusion heights of the logic area and pixel area are equal and their top surfaces are flush, thus avoiding polysilicon residue and over-etching.
Stable isolation between the logic region and the pixel region is achieved, reducing the possibility of polysilicon residue and over-etching, improving the current communication efficiency of the semiconductor structure and the conductivity stability of the image sensor, and reducing the risk of short circuits.
Smart Images
Figure CN114725145B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing, and specifically relates to a semiconductor structure and its manufacturing method. Background Technology
[0002] An image sensor, also known as a photosensitive element, is a device that converts optical images into electronic signals. It is characterized by its small size, light weight, high integration, high resolution, low power consumption, long lifespan, and low price, and is therefore widely used in digital cameras and other electro-optical devices.
[0003] The shallow trench isolation structures on the logic region and pixel region of an image sensor have different depths, therefore, the methods for forming different shallow trench isolation structures also differ during the manufacturing process. During semiconductor structure formation, issues such as polysilicon residue or over-etching of polysilicon can easily occur, affecting the quality of the formed semiconductor structure. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor structure and a method for manufacturing the same, so as to improve the quality of semiconductor structures.
[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:
[0006] A method for manufacturing a semiconductor structure includes at least the following steps:
[0007] A substrate is provided, wherein the substrate includes a logic region and a pixel region;
[0008] A pad oxide layer and a pad nitride layer are formed on the substrate;
[0009] A protective layer is formed on the nitrided pad layer;
[0010] The substrate is etched to form first-type trenches on the logic region and the pixel region;
[0011] The first type of trench on the logic region is etched again to form the second type of trench;
[0012] Remove the protective layer; and
[0013] The pad oxide layer and the pad nitride layer on both sides of the first type trench and the second type trench are etched back to form steps on both sides of the first type trench and the second type trench.
[0014] In one embodiment of the present invention, after forming the step, the method for manufacturing the semiconductor structure further includes:
[0015] Material is filled into the first type of trench, the second type of trench, and the step to form a trench isolation structure.
[0016] In one embodiment of the present invention, the method for forming the first type of trench includes:
[0017] A first photoresist layer is formed on the protective layer; and
[0018] Using the first photoresist layer as a mask, the protective layer, the pad nitride layer, and the pad oxide layer are etched to form a first type of etched hole.
[0019] In one embodiment of the present invention, the method for forming the first type of trench includes:
[0020] The substrate is etched within the first type of etch hole to form the first type of trench.
[0021] In one embodiment of the present invention, the method for forming the second type of trench includes:
[0022] A second photoresist layer is formed, and the second photoresist layer is located within the first type of trench in the pixel area and on the protective layer; and
[0023] The first type of trench and the protective layer on the logic region are etched to form the second type of trench.
[0024] In one embodiment of the present invention, when forming the second type of trench, the etching selectivity ratio of the protective layer and the substrate is 1:2 to 1:8.
[0025] In one embodiment of the present invention, the method for removing the protective layer and etching the pad oxide layer includes:
[0026] The protective layer and the pad oxide layer near the trench are etched to form a second type of etched hole.
[0027] In one embodiment of the present invention, when the protective layer is removed and the pad oxide layer is etched, the etch selectivity ratio of the protective layer and the pad oxide layer is 5:1 to 15:1.
[0028] In one embodiment of the present invention, the etching solution used to etch the pad nitride layer is phosphoric acid.
[0029] A semiconductor structure comprising at least:
[0030] A substrate having a logic region and a pixel region disposed thereon;
[0031] An oxide layer is disposed on the substrate;
[0032] A nitrided layer is disposed on the oxide layer of the pad;
[0033] A first type of trench is disposed within the pixel area;
[0034] A second type of trench is disposed within the logic area, wherein the aspect ratio of the second type of trench is smaller than that of the first type of trench; and
[0035] Steps are provided on the substrate and located on both sides of the first type of trench and the second type of trench.
[0036] As described above, this invention provides a method for manufacturing a semiconductor structure to obtain a semiconductor structure with equal convex heights and flush top surfaces in both the logic region and pixel region, thereby avoiding polysilicon residue in the logic region and pixel region during subsequent processes. Furthermore, the dual-trench manufacturing method provided by this invention can obtain deep trenches in the logic region and shallow trenches in the pixel region within the same process, avoiding over-etching of polysilicon. Simultaneously, the dual-trench manufacturing method provided by this invention reduces the possibility of voids appearing in the first and second type trenches, forming a stable active region isolated semiconductor structure and improving current conduction efficiency within the semiconductor structure. Therefore, this invention provides a more stable, effective semiconductor structure that facilitates ion implantation in subsequent processes. Applying the semiconductor structure provided by this invention in applications such as image sensor manufacturing can reduce short-circuit risks and improve the conductivity stability of image sensors.
[0037] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a flowchart of the manufacturing method of the semiconductor structure described in this invention.
[0040] Figure 2 This is a diagram of the hierarchical structure on the substrate.
[0041] Figure 3 This is a schematic diagram of the structure of the first photoresist layer.
[0042] Figure 4 This is a schematic diagram of the structure for forming the first photoresist layer.
[0043] Figure 5 This is a schematic diagram of the structure of the first photoresist layer.
[0044] Figure 6To form the semiconductor structure pattern after the first etching.
[0045] Figure 7 This is a schematic diagram of the photoresist filling structure for the first type of trench.
[0046] Figure 8 This is a schematic diagram of the structure for forming the second photoresist layer.
[0047] Figure 9 This is a schematic diagram of the structure of the second photoresist layer.
[0048] Figure 10 A schematic diagram of the structure for forming the second type of trench.
[0049] Figure 11 This is a diagram of the semiconductor structure after the second etching.
[0050] Figure 12 This is a diagram of the semiconductor structure after the third etching.
[0051] Figure 13 This is a diagram of the semiconductor structure after the fourth etching.
[0052] Figure 14 This is a schematic diagram of the structure for the formation of the oxide layer on the pad by thermal oxidation.
[0053] Figure 15 This is a schematic diagram of the structure of the oxide layer of the pad.
[0054] Figure 16 This is a schematic diagram of the structure of the nitrided liner layer.
[0055] Figure 17 This is a schematic diagram of a structure that forms a filling section.
[0056] Figure 18 This is a schematic diagram of a structure that forms a filling section.
[0057] Figure 19 This is a schematic diagram of the structure after the filling part is flattened.
[0058] Figure 20 This is a schematic diagram of the structure after the filling part is flattened.
[0059] Figure 21 This is a structural diagram of a semiconductor structure.
[0060] Figure 22 This is a structural diagram of a semiconductor structure.
[0061] Figure 23 This is a schematic diagram of the structure of the first liner.
[0062] Figure 24 This is a schematic diagram of the second liner.
[0063] Labeling Explanation: 1 Semiconductor structure; 2 Logic region; 3 Pixel region; 4 Step; 5 Bump; 10 Substrate; 20 Pad oxide layer; 30 Pad nitride layer; 40 Protective layer; 50 First photoresist layer; 501 First photoresist layer; 502 First photoresist layer plate; 60 First type trench; 70 Second type trench; 80 First type etched hole; 801 Second type etched hole; 802 Third type etched hole; 90 Second photoresist layer; 901 Second photoresist layer; 902 Second photoresist layer plate; 100 Pad oxide layer; 1001 First pad; 110 Pad nitride layer; 1101 Second pad; 120 Filler portion. Detailed Implementation
[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0065] Please see Figures 1-24 As shown, an image sensor, or photosensitive element, is a device that converts optical images into electronic signals. It is widely used in digital cameras and other electro-optical devices. An image sensor typically includes a logic region 2 and a pixel region 3. The logic region 2 houses an integrated circuit used to control the image sensor's operation. The pixel region 3 houses photoelectric devices used to collect and output photoelectric information. The image sensor can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS). It can also be a contact image sensor (CIS). Different types of image sensors use different structures for the logic region 2 and pixel region 3. This invention provides a semiconductor structure 1 with double trenches, possessing a precise and stable shallow trench isolation structure to isolate the device, suitable for image sensors of the types of charge-coupled devices, complementary metal-oxide-semiconductors, and contact image sensors.
[0066] Please see Figures 1-24 As shown, the present invention provides a method for manufacturing a semiconductor structure, wherein the steps of the method for manufacturing the semiconductor structure include, for example, steps S1 to S9.
[0067] S1. A substrate 10 is provided, and the substrate 10 includes a logic region 2 and a pixel region 3. A pad oxide layer 20, a pad nitride layer 30 and a protective layer 40 are sequentially disposed on the substrate 10.
[0068] S2. A first photoresist layer 50 is disposed on the protective layer 40.
[0069] S3. First etching. Using the first photoresist layer 50 as a mask, etch the protective layer 40, the pad nitride layer 30, and the pad oxide layer 20. On the logic region 2 and the pixel region 3, etch the protective layer 40, the pad nitride layer 30, and the pad oxide layer 20 to form a first type of etch hole 80. Continue etching the substrate 10 within the first type of etch hole 80 to form a first type of trench 60.
[0070] S4. A second photoresist layer 90 is formed in the first type trench 60 of the pixel area 3 and on the protective layer 40 on both sides of the first type trench 60.
[0071] S5. Second etching. Using the second photoresist layer 90 as a mask, the substrate 10 within the first type trench 60 is etched to form the second type trench 70 in the logic region 2.
[0072] S6. Third etching. Etch the pad oxide layer 20 on both sides of the first type etch hole 80, form the second type etch hole 801 in the first type etch hole 80, and etch away the protective layer 40.
[0073] S7. Fourth etching. The pad nitride layer 30 on the second type etch hole 801 is etched to form a third type etch hole 802 within the second type etch hole 801.
[0074] S8. Material filling. Material is filled into the second type trench 70 and the first type trench 60 to form a filling portion 120, and material is filled into the third type etched hole 802 to form a protrusion 5.
[0075] S9. Polish flat. Polish the protrusion 5 flat so that the surface of the protrusion 5 is flush with the surface of the pad nitride layer 30. Then remove the pad oxide layer 20 and the pad nitride layer 30 to form the semiconductor structure of logic region 2 and pixel region 3.
[0076] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S1, the substrate 10 provided is made of, for example, silicon. The substrate 10 is placed in a high-temperature environment, and an oxidizing atmosphere is introduced into the substrate 10 to convert the silicon on the surface of the substrate 10 into silicon dioxide, thereby forming a pad oxide layer 20. The high-temperature environment is, for example, 1000–2000°C, and the introduced oxidizing atmosphere can be dry, pure oxygen, pure water vapor, or a mixture of dry, pure oxygen and pure water vapor. The introduction time of the oxidizing atmosphere is greater than, for example, 30 minutes. The thickness of the pad oxide layer 20 is, for example, 100–200 angstroms. The formed pad oxide layer 20 can protect the active region of the substrate 10 from chemical contamination when the protective layer 40 material is washed away. On the surface of the pad oxide layer 20, a pad nitride layer 30 is formed by, for example, low-pressure chemical vapor deposition of silicon nitride, and the thickness of the pad nitride layer 30 is, for example, 800–1800 angstroms. Silicon nitride is a robust mask material that helps protect the active region during trench filling and also acts as a polishing barrier when the surface is flat. A protective layer 40 is formed on the pad nitride layer 30 by, for example, low-pressure chemical vapor deposition of tetraethyl orthosilicate (TEOS) or by a high aspect ratio process (HARP). The thickness of the protective layer 40 is, for example, 500–2000 angstroms, and the thickness of the protective layer 40 can be adjusted according to the trench depth disposed on the substrate 10.
[0077] Please see Figure 1 and Figures 3-5As shown, in one embodiment of the present invention, in step S2, after the deposition of the protective layer 40 is completed, the surface of the protective layer 40 is first pretreated to improve the adhesion of the photoresist on the protective layer 40. Specifically, contaminants such as particulate matter, organic matter, process residues, mobile ions, and water vapor are removed from the surface of the protective layer 40. The substrate 10 is pre-baked to, for example, 100-200°C, and then an adhesion promoter such as hexamethyldisilazane is spin-coated onto the protective layer 40 to increase the adhesion of the subsequent photoresist coating. After the pretreatment of the protective layer 40 is completed, the substrate 10 is cooled to room temperature, and the photoresist is spin-coated onto the protective layer 40 to form a first photoresist layer 501. The solvent of the first photoresist layer 501 is removed by pre-baking, a first photoresist layer 502 is placed on the first photoresist layer 501, and the first photoresist layer 501 is exposed by, for example, an electron beam. A difference in solubility is created between the illuminated and unilluminated areas on the first photoresist layer 501. The substrate 10 is then immersed in a developer solution, such as an alkaline aqueous solution or an organic solvent, to dissolve the exposed areas and form the first photoresist layer 50. When the first photoresist layer 501 is an ultraviolet photoresist, the exposed areas can be rinsed with water after the first photoresist layer 50 is formed. When the first photoresist layer 501 is an electron beam resist, the exposed areas are fixed using a fixing solution after the first photoresist layer 50 is formed. After the first photoresist layer 50 is formed, it is baked to make the first photoresist layer 501 adhere more firmly to the protective layer 40, thereby increasing the etching resistance of the first photoresist layer 50 during the first etching.
[0078] Please see Figure 1 and Figure 6 As shown, in one embodiment of the present invention, in step S3, using the first photoresist layer 50 as a mask, the substrate 10, pad oxide layer 20, pad nitride layer 30, and protective layer 40 are etched for the first time, and the first etching is a dry etching. During the first etching process, the protective layer 40, pad nitride layer 30, and pad oxide layer 20 outside the area covered by the first photoresist layer 50 are etched away with plasma gas and highly corrosive chemicals, thereby forming a first type of etch hole 80 on the substrate 10. The substrate 10 is then etched further within the first type of etch hole 80, forming a first type of trench 60 in the logic region 2 and pixel region 3 of the substrate 10. In the same etching environment, the first type of trench 60 formed in the logic region 2 and pixel region 3 has the same depth and the same aspect ratio. The depth of the first type of trench 60 is, for example, 1000 to 2000 angstroms, and the aspect ratio is, for example, 1:4 to 1:10. The area of the logic region 2 and pixel region 3 is variable according to the requirements of the semiconductor structure 1 required for the product. After the first etching is completed, the photoresist is dissolved and etched using an organic solvent or a photoresist remover to remove the photoresist serving as the first photoresist layer 50. In other embodiments, the first photoresist layer 50 can also be removed by ashing with an oxygen plasma gas.
[0079] Please see Figure 1 , Figures 7-9 As shown, in one embodiment of the present invention, in step S4, surface contaminants such as process residues, mobile ions, and water vapor are removed from the protective layer 40. An adhesion promoter is applied to the protective layer 40, and the substrate 10 is pre-baked to improve the adhesion promoter film formation. The substrate 10 is cooled to room temperature, and photoresist is filled into the first type trench 60 until it overflows, so as to facilitate spin-coating to form a second photoresist layer 90. Photoresist is spin-coated onto the protective layer 40 to form a second photoresist layer 901. The second photoresist layer 901 is baked at high temperature to evaporate and remove the solvent in the second photoresist layer 901, so that the photoresist content in the second photoresist layer 901 is less than, for example, 5%, so that the second photoresist layer 901 adheres to the surface of the protective layer 40. According to the second photoresist layer 902, the second photoresist layer 902 is exposed by, for example, an electron beam, to create a difference in solubility between the illuminated and unilluminated portions of the second photoresist layer 901. The substrate 10 is then immersed in a developing solution, such as an alkaline aqueous solution or an organic solvent, to dissolve the exposed areas, thereby forming a second photoresist layer 90 on the protective layer 40, with a thickness of, for example, 1000–3000 angstroms. When the second photoresist layer 901 is an ultraviolet photoresist, the exposed areas are rinsed with water after its formation. When the second photoresist layer 901 is an electron beam resist, the exposed areas are fixed using a fixing solution after its formation. After the second photoresist layer 90 is formed, it is baked to ensure a more secure adhesion between the second photoresist layer 901 and the protective layer 40, thereby increasing the etch resistance of the second photoresist layer 90 during the second etching process. In the process of forming the second photoresist layer 90, photoresist is filled into the first type trench 60 within the pixel region 3, and then photoresist is spin-coated onto the protective layer 40 to form the second photoresist layer 90, thereby improving the stability of the spin-coating of the second photoresist layer 90. The second photoresist layer 90 covers the pixel region 3. The area of the second photoresist layer 90 is larger than the area of the first type etched hole 80.
[0080] Please see Figure 1 , Figure 6 and Figure 10As shown, in one embodiment of the present invention, in step S5, a second photoresist layer 90 is used to protect the protective layer 40 covered by the second photoresist layer 90, thereby protecting the first type trench 60 of the pixel region 3, so that the second etching avoids the first type trench 60 of the pixel region 3. During the second etching process, the protective layer 40 and the substrate 10 outside the area covered by the second photoresist layer 90 are etched away using plasma gas and highly corrosive chemicals. Specifically, by adjusting the etching selectivity ratio of the protective layer 40 and the substrate 10, during the second etching process, the substrate 10 is etched completely before the protective layer 40 is fully etched, and the second type trench 70 is formed within the first type trench 60, thereby forming a protective layer 40 of first thickness and a protective layer 40 of second thickness. The protective layer 40 of first thickness is located within the logic region 2, and the protective layer 40 of second thickness is located within the pixel region 3. The first thickness is less than the second thickness. Specifically, the etch selectivity ratio of the protective layer 40 and the substrate 10 is adjusted to, for example, 1:2 to 1:8, and for example, set to 1:4. When the etch selectivity ratio of the protective layer 40 and the substrate 10 is set, by forming a protective layer 40 of a first thickness in the second etching, the pad nitride layer 30 located under the coverage of the protective layer 40 is protected, so that the surface of the pad nitride layer 30 is not affected by the second etching. The protective layer 40 of the first thickness covers the logic region 2 and is the retained portion of the protective layer 40 that undergoes the second etching, while the protective layer 40 of the second thickness is located within the coverage area of the second photoresist layer 90 and is protected by the second photoresist layer 90 and does not participate in the second etching.
[0081] Please see Figure 1 , Figure 10 and Figure 11As shown, in one embodiment of the present invention, after the second etching is completed, the photoresist is dissolved and etched using an organic solvent or a photoresist remover to fill the second photoresist layer 90 and the photoresist filling the pixel region 3. In other embodiments, the photoresist filling the second photoresist layer 90 and the pixel region 3 can also be removed by ashing with an oxygen plasma gas. The depth of the first type trench 60 formed after the first etching is, for example, 1000 to 2000 angstroms, and the aspect ratio is, for example, 1:10 to 1:4. After the second etching, the depth of the first type trench 60 is greater, and the aspect ratio is smaller, to form the second type trench 70. Under the same etching conditions, the depth of the second type trench 70 formed by the second etching is equal to the depth of the first type trench 60. The depth of the second type trench 70 is, for example, twice that of the first type trench 60, and the width of the second type trench 70 is equal to the width of the first type trench 60 under the protection of the protective layer 40. The depth of the second type trench 70 is, for example, 2000–4000 angstroms, and the aspect ratio of the second type trench 70 is, for example, 1:20–1:8. After the second etching, the second type trench 70 and the first type trench 60 are obtained. The aperture of the first type etched hole 80 remains unchanged. The sidewall gradient of the second type trench 70 is greater than that of the first type trench 60, while the first type trench 60 within the pixel region 3 remains unchanged under the protection of the second photoresist layer 90. The sidewall gradient represents the degree of inclination of the trench walls of the first type trench 60 and the second type trench 70 relative to the surface of the substrate 10. Both the first and second etching processes employ, for example, a dry etching method using plasma gas to improve the trench forming accuracy.
[0082] Please see Figure 1 and Figure 12As shown, in one embodiment of the present invention, in step S6, the pad oxide layer 20 and the protective layer 40 are etched a third time using an etchant to remove the protective layer 40 and radially pull back the pad oxide layer 20 according to the first type of etch hole 80. The etchant can be diluted hydrofluoric acid, and the concentration of the diluted hydrofluoric acid is, for example, 1:100. Under etching with diluted hydrofluoric acid at a concentration of, for example, 1:100, the material of the protective layer 40 is, for example, tetraethyl orthosilicate, and the etching rate of the protective layer 40 can reach, for example, 2.86 Å / s. Under etching with diluted hydrofluoric acid at a concentration of, for example, 1:100, if the material of the pad nitride layer 30 is silicon nitride, the etching rate of the material of the pad nitride layer 30 can reach, for example, 0.014 Å / s. Therefore, during the third etching process, the protective layer 40 and the pad oxide layer 20 are etched using diluted hydrofluoric acid at a concentration of, for example, 1:100, and the etching thickness of the pad nitride layer 30 is negligible when the protective layer 40 is completely removed. Because the etching rate of diluted hydrofluoric acid on the protective layer 40 and the pad oxide layer 20 has a selective ratio, and the contact area between the pad oxide layer 20 and the diluted hydrofluoric acid is small, the pad oxide layer 20 is partially etched after the protective layer 40 is removed. Specifically, the pad oxide layer 20 located on both sides of the first type trench 60 and the second type trench 70 is etched away. The hole walls of the first type etched holes 80 located on the pad oxide layer 20 are etched and widened, forming second type etched holes 801 within the first type etched holes 80. The selective etching rate ratio of diluted hydrofluoric acid on the protective layer 40 and the pad oxide layer 20 is, for example, 5:1 to 15:1.
[0083] Please see Figure 1 and Figure 13 As shown, in one embodiment of the present invention, in step S7, after forming the second type etched hole 801 on the pad oxide layer 20, the second type trench 70 and the first type trench 60 are cleaned with plasma water and then dried to remove contaminants such as water vapor and hydrofluoric acid residue from the second type trench 70, the first type trench 60, the first type etched hole 80, the second type etched hole 801, and the surface of the pad nitride layer 30. Then, the pad nitride layer 30 is etched a fourth time using an etching solution. The etching solution can be phosphoric acid. Phosphoric acid reacts with the silicon nitride of the pad nitride layer 30, while the reaction with the pad oxide layer 20 and the substrate 10 is negligible. Therefore, during the fourth etching process, the pad nitride layer 30 is etched with phosphoric acid, thereby forming a third type etched hole 802 within the second type etched hole 801. In the third etching process, the etching amount of the oxide layer 20 forming the second type of etched hole 801 is equal to the etching amount of the nitride layer 30 forming the third type of etched hole 802 in the fourth etching process. After the fourth etching is completed, steps 4 are formed on both sides of the first type of trench 60 and the second type of trench 70.
[0084] Please see Figure 14and Figure 15 As shown, in one embodiment of the present invention, in step S8, after the fourth etching is completed, the second type trench 70, the first type trench 60, and the third type etched hole 802 are cleaned with plasma water, and the surface of the pad nitride layer 30 is cleaned to remove process residues such as residual etching solution and water vapor. After drying, the substrate 10 is placed in a high-temperature environment, and an oxidizing atmosphere is introduced into the second type trench 70 and the first type trench 60 to oxidize the surface of the substrate 10 to form a pad oxide layer 100. The pad oxide layer 100 is connected to the pad oxide layer 20 to prevent oxygen molecules from diffusing into the active region. The thickness of the pad oxide layer 100 is less than or equal to the thickness of the pad oxide layer 20. The pad oxide layer 100 formed by introducing the oxidizing atmosphere is attached to the surface of the substrate 10. Specifically, the pad oxide layer 100 is attached to the trench walls of the second type trench 70, the trench walls of the first type trench 60, and inside the third type etched hole 802, and is on the surface of the substrate 10. In other embodiments, silicon oxide can also be deposited into the second type trench 70, the first type trench 60, and the surface of the substrate 10 by chemical vapor deposition to form a pad oxide layer 100. The thickness of the pad oxide layer 100 is less than or equal to the thickness of the pad oxide layer 20. The pad oxide layer 100 is attached to the trench walls of the second type trench 70, the trench walls of the first type trench 60, and the wall of the third type etched hole 802.
[0085] Please see Figure 1 , Figure 15 and Figure 16 As shown, in one embodiment of the present invention, after the pad oxide layer 100 is deposited, high aspect ratio filling can be performed directly. In other embodiments of the present invention, in step S8, after the pad oxide layer 100 is formed, silicon nitride can be deposited onto the pad oxide layer 100 by chemical vapor deposition to form a pad nitride layer 110. The thickness of the pad nitride layer 110 is less than the thickness of the pad oxide layer 20, and the pad nitride layer 110 is attached to the surface of the pad oxide layer 100. After the pad nitride layer 110 is formed, high aspect ratio filling is performed to avoid the formation of voids in the second type trench 70 and the first type trench 60 during filling.
[0086] Please see Figure 1 , Figure 17 and Figure 18 , Figure 19 and Figure 20As shown, in one embodiment of the present invention, in step S8, filling material is injected into the third type etched hole 802, the second type trench 70, and the first type trench 60 to form a filling portion 120. The filling portion 120 in the logic region 2 is made of a material with a relatively large grinding ratio to silicon nitride, such as silicon oxide. Multiple filling operations can be performed on the second type trench 70 and the first type trench 60 using a high aspect ratio process. The first filling depth can be, for example, 1 / 5 to 3 / 5 of the trench depth of the first type trench 60. The second filling depth can fill the remaining content of the first type trench 60. The third filling can fill the remaining content of the second type trench 70, thereby avoiding voids in the filling of the second type trench 70 and the first type trench 60. After completing the filling of the second type trench 70 and the first type trench 60, material is filled into the third type etched hole 802 to form a protrusion 5 in the logic region 2 and the pixel region 3, wherein the protrusion 5 is located on the surface of the substrate 10. In other embodiments of the present invention, the filling in the logic region 2 and the pixel region 3 can also be formed by a tetraethyl orthosilicate deposition process or by spin coating. The material of the filling portion 120 can be silicon dioxide.
[0087] Please see Figure 1 , Figure 19 and Figure 20 As shown, in one embodiment of the present invention, in step S9, both the third and fourth etching processes utilize wet etching to improve the surface flatness of the pad nitride layer 30 during etching, and to improve the polishing flatness accuracy of the protrusion 5 by using the pad nitride layer 30 as a barrier layer. After the filling portion 120 is deposited, the surface of the filling portion 120 is flattened to be flush with the surface of the pad nitride layer 30 by, for example, chemical mechanical polishing, thereby making the surfaces of the protrusions 5 in the logic region 2 and the pixel region 3 flush. Since the degree of etching participation is the same at all points on the surface of the pad nitride layer 30 during the third and fourth etching processes, the properties of the surface of the pad nitride layer 30 can always be kept the same at all points. Therefore, the heights of the protrusions 5 in the logic region 2 and the pixel region 3 obtained by using the pad nitride layer 30 as a barrier are equal, thereby making the top surfaces of the protrusions 5 in the logic region 2 and the protrusions 5 in the pixel region 3 flush. Therefore, the height of the protrusion 5 is less than or equal to the sum of the thicknesses of the pad oxide layer 20 and the pad nitride layer 30, and the height of the protrusion 5 is, for example, 900 to 2000 angstroms.
[0088] Please see Figure 1 , Figure 21 and Figure 22As shown, in step S9, the pad nitride layer 30 and the pad oxide layer 20 are sequentially removed using an etching solution to obtain a semiconductor structure 1. Specifically, the pad nitride layer 30 is removed by thermal phosphoric acid etching. In one embodiment of the invention, a pad nitride layer 110 is provided, and in step S9, the pad nitride layer 110 on the side of the protrusion 5 is removed together. Then, the pad oxide layer 20 and the pad oxide layer 100 located on the side of the protrusion 5 are removed by diluted hydrofluoric acid etching. Wherein, when the pad oxide layer 100 is formed in step S8, the formed semiconductor structure 1 is as follows... Figure 21 As shown. Within the coverage area of the protrusion 5, a pad oxide layer 100 is attached to the substrate 10. When the pad oxide layer 100 and the pad nitride layer 110 are formed in step S8, the formed semiconductor structure 1 is as follows. Figure 22 As shown. Within the coverage area of the protrusion 5, a pad oxide layer 100 is connected to the substrate 10, and a pad nitride layer 110 is provided on the surface of the pad oxide layer 100 to facilitate control of the depth and amount of subsequent particle implantation.
[0089] Please see Figures 2-22 As shown, according to the semiconductor structure manufacturing method of the present invention, the present invention also provides a semiconductor structure 1. In one embodiment of the present invention, the semiconductor structure 1 includes a substrate 10, a second type trench 70 and a first type trench 60 disposed on the substrate 10. The substrate 10 includes a logic region 2 and a pixel region 3. The second type trench 70 is disposed in the logic region 2, and the first type trench 60 is disposed in the pixel region 3. A pad oxide layer 100 is grown on the trench walls of the second type trench 70 and the trench walls of the first type trench 60. A filling portion 120 is disposed in the second type trench 70 and the first type trench 60, and the filling portion 120 includes a protrusion 5 connected to the surface of the substrate 10. The protrusion 5 in the logic region 2 and the protrusion 5 in the pixel region 3 have the same height and flush surfaces. In other embodiments of the present invention, a pad nitride layer 110 is connected to the surface of the pad oxide layer 100.
[0090] Please see 2- Figure 22 As shown, in one embodiment of the present invention, the depth of the second type trench 70 is, for example, twice the depth of the first type trench 60, and the depth of the second type trench 70 is, for example, 2000 to 4000 angstroms, while the depth of the first type trench 60 is, for example, 1000 to 2000 angstroms. The width-to-depth ratio of the second type trench 70 is, for example, 1:20 to 1:8, while the width-to-depth ratio of the first type trench 60 is, for example, 1:10 to 1:4. The width of the protrusion 5 is greater than the width of the second type trench 70, and the width of the protrusion 5 is greater than the width of the first type trench 60.
[0091] Please see 2- Figure 24As shown, in one embodiment of the present invention, the pad oxide layer 100 includes a first pad 1001, which is disposed on the substrate 10 and connected to the protrusion 5. The sidewalls of the first pad 1001 and the sidewalls of the protrusion 5 are located in the same plane. In other embodiments of the present invention, the pad oxide layer 100 includes a first pad 1001, which is disposed on the substrate 10 and connected to the protrusion 5. The pad nitride layer 110 includes a second pad 1101, which is disposed on the first pad 1001 and connected to the protrusion 5. The first pad 1001, the second pad 1101, and the sidewalls of the protrusion 5 are located in the same plane.
[0092] Please see Figures 1-24 As shown, in one embodiment of the present invention, the height of the protrusion 5 is less than or equal to the sum of the thicknesses of the pad oxide layer 20 and the pad nitride layer 30 during the manufacturing process, and the height of the protrusion 5 is, for example, 900 to 2000 angstroms.
[0093] Please see Figures 1-24 As shown, this invention provides a method for manufacturing a semiconductor structure 1 to obtain a semiconductor structure 1 in which the heights of the protrusions 5 in the logic region 2 and the pixel region 3 are equal and the top surfaces of the protrusions 5 are flush, thereby avoiding polysilicon residue in the logic region 2 and the pixel region 3 during subsequent processes. Furthermore, the method for manufacturing a semiconductor structure 1 provided by this invention can obtain deep trenches in the logic region 2 and shallow trenches in the pixel region 3 within the same process, avoiding polysilicon over-etching in the logic region 2. Therefore, this invention provides a more stable, effective semiconductor structure 1 that is beneficial for ion implantation in subsequent processes. Applying the semiconductor structure 1 provided by this invention in the manufacture of image sensors can reduce the risk of short circuits and improve the conductivity stability of the image sensor. The image sensor can be a charge-coupled device, a complementary metal-oxide-semiconductor (CMOS) device, or a contact image sensor.
[0094] In the description of this specification, the references to terms such as "this embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0095] The embodiments of the present invention disclosed above are merely illustrative of the invention. These embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, At least the following steps are included: A substrate is provided, wherein the substrate includes a logic region and a pixel region; A pad oxide layer and a pad nitride layer are formed on the substrate; A protective layer is formed on the nitrided pad layer; On the logic region and the pixel region, the protective layer, the pad nitride layer, and the pad oxide layer are etched to form a first type of etch hole, and the substrate is etched further within the first type of etch hole to form a first type of trench on the logic region and the pixel region; The first type of trench on the logic region is etched again to form the second type of trench; Remove the protective layer; as well as The pad oxide layer and the pad nitride layer on both sides of the first type trench and the second type trench are etched back to form steps on both sides of the first type trench and the second type trench; In this process, after forming the second type of trench, the pad oxide layer on both sides of the first type of etch hole is first etched, the second type of etch hole is formed in the first type of etch hole, and the protective layer is etched away. The pad oxide layer and the protective layer are etched with an etching solution to remove the protective layer and the pad oxide layer is etched back radially according to the first type of etch hole. Next, the pad nitride layer is etched with phosphoric acid to form a third type of etched hole in the second type of etched hole. The etching amount of the pad oxide layer to form the second type of etched hole is equal to the etching amount of the pad nitride layer to form the third type of etched hole. After the pad nitride layer is etched, steps are formed on both sides of the first type of trench and the second type of trench. Fill the first type of trench and the second type of trench until the filling material is above the pad nitride layer; Polish the filler material flat until the filler material is flush with the surface of the pad nitride layer, wherein the surfaces of the filler material in the logic area and the pixel area are flush.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After the steps are formed, the method for manufacturing the semiconductor structure further includes: Material is filled into the first type of trench, the second type of trench, and the step to form a trench isolation structure.
3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method for forming the first type of trench includes: A first photoresist layer is formed on the protective layer; and Using the first photoresist layer as a mask, the protective layer, the pad nitride layer, and the pad oxide layer are etched to form a first type of etched hole.
4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method for forming the first type of trench includes: The substrate is etched within the first type of etch hole to form the first type of trench.
5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method for forming the second type of trench includes: A second photoresist layer is formed, and the second photoresist layer is located within the first type of trench in the pixel area and on the protective layer; and The first type of trench and the protective layer on the logic region are etched to form the second type of trench.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, When forming the second type of trench, the etching selectivity ratio of the protective layer and the substrate is 1:2 to 1:
8.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method for removing the protective layer and etching the pad oxide layer includes: The protective layer and the pad oxide layer near the trench are etched to form a second type of etched hole.
8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, When the protective layer is removed and the pad oxide layer is etched, the etch selectivity ratio of the protective layer and the pad oxide layer is 5:1 to 15:
1.
9. A method for manufacturing a semiconductor structure according to claim 1, characterized in that, The etching solution used to etch the nitrided layer of the pad is phosphoric acid.
10. A semiconductor structure, based on a method for manufacturing the semiconductor structure as claimed in claim 1, characterized in that, It includes at least: A substrate having a logic region and a pixel region disposed thereon; An oxide layer is disposed on the substrate; A nitrided layer is disposed on the oxide layer of the pad; A first type of trench is disposed within the pixel area; A second type of trench is disposed within the logic area, wherein the aspect ratio of the second type of trench is smaller than that of the first type of trench; and Steps are provided on the substrate and located on both sides of the first type of trench and the second type of trench.