A field-limiting ring termination structure and fabrication method for a power semiconductor device

Abstract

This invention provides a field-limiting ring termination structure and fabrication method for a power semiconductor device. The termination structure includes a cell region and a termination region. A main junction region is disposed on the side of the cell region furthest from the substrate and is located on the surface of an epitaxial layer. The termination region includes several field-limiting rings and a stop ring. The stop ring is disposed at the edge of the termination region furthest from the main junction region. The several field-limiting rings are sequentially arranged between the main junction region and the stop ring, and are spaced apart from the surface of the termination region. A field oxide layer is covered on the surface of the termination region corresponding to the field-limiting rings. A floating field plate is disposed on the surface of the field oxide layer. The floating field plate includes an overlapping region corresponding to the field-limiting rings and an extension region corresponding to the region between adjacent field-limiting rings. The extension region is used to attract holes. The field-limiting ring termination structure for the power semiconductor device provided by this invention can achieve more ideal breakdown voltage stability.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor, and particularly relates to a field limiting ring terminal structure of a power semiconductor device and a preparation method. BACKGROUND

[0002] Power semiconductor device product types include IGBT (insulated gate bipolar transistor), FRD (fast recovery diode), VDMOS (vertical double diffusion metal oxide semiconductor) and other high-voltage and high-current devices. Large current requires a large-area cell region, and high voltage requires a field limiting ring with a weak curvature radius.

[0003] A common terminal structure of a conventional high-voltage power device is a field limiting ring design, that is, a plurality of floating field rings are arranged outside the cell region well. However, the conventional field limiting ring terminal structure still has the problem of poor voltage stability, and one of the main reasons is that the conventional field limiting ring terminal structure is designed on the surface of the device and directly contacts the terminal field oxide SiO2, which is easily affected by surface charges and interface trap charges. Another field limiting ring design is to implant the floating field ring in the terminal body by high energy so as to be far away from the field oxide SiO2. However, the charges inside the field oxide SiO2 still exist, and therefore, a more optimized terminal structure is needed, that is, the electric field peak value appears in the body, and the negative effects caused by the movement of the field oxide charges are effectively reduced, so as to achieve more ideal voltage stability. SUMMARY

[0004] The technical problem to be solved by the application is to provide a field limiting ring terminal structure of a power semiconductor device and a preparation method, and to solve the problem of poor voltage stability of a conventional power semiconductor device.

[0005] To solve the above technical problem, the application is implemented as follows. The application provides a field limiting ring terminal structure of a power semiconductor device, which comprises a cell region and a terminal region formed outside the cell region. The terminal region and the cell region comprise a common substrate and an epitaxial layer extending along one side of the substrate. In the cell region, a main junction region is arranged away from the substrate, and the main junction region is arranged on the surface of the epitaxial layer. The terminal region comprises a plurality of field limiting rings and a cutoff ring. The cutoff ring is arranged at the edge of the terminal region away from the main junction region. The plurality of field limiting rings are arranged between the main junction region and the cutoff ring in sequence, and the plurality of field limiting rings are arranged away from the surface of the terminal region. The surface of the terminal region is covered with a field oxide layer in the region corresponding to the plurality of field limiting rings. A floating field plate is arranged on the surface of the field oxide layer. The floating field plate comprises an overlapping region corresponding to the field limiting ring and an extension region corresponding to the region between adjacent field limiting rings. The extension region is used for attracting holes.

[0006] The main junction region is arranged away from the substrate, and the main junction region is arranged on the surface of the epitaxial layer. The terminal region comprises a plurality of field limiting rings and a cutoff ring. The cutoff ring is arranged at the edge of the terminal region away from the main junction region. The plurality of field limiting rings are arranged between the main junction region and the cutoff ring in sequence, and the plurality of field limiting rings are arranged away from the surface of the terminal region. The surface of the terminal region is covered with a field oxide layer in the region corresponding to the plurality of field limiting rings. A floating field plate is arranged on the surface of the field oxide layer. The floating field plate comprises an overlapping region corresponding to the field limiting ring and an extension region corresponding to the region between adjacent field limiting rings. The extension region is used for attracting holes.

[0007] Further, the number of the floating field plates is one, and the floating field plate comprises extension regions arranged in sequence with an overlap region arranged between adjacent extension regions, the overlap region covering a plurality of the field limiting rings.

[0008] Further, each of the floating field plates corresponds to one of the field limiting rings, and each group of the floating field plates comprises an overlap region and extension regions on both sides of the overlap region, the overlap region covering the corresponding field limiting ring.

[0009] Further, each of the floating field plates corresponds to one of the field limiting rings, and each group of the floating field plates comprises an overlap region and extension regions on one side of the overlap region, the overlap region partially overlapping the corresponding field limiting ring.

[0010] Further, the overlap region partially overlaps the corresponding field limiting ring, comprising:

[0011] the overlap region of each group of the floating field plates overlaps a left side region of the corresponding field limiting ring, and the extension regions extend to the main junction region;

[0012] or, the overlap region of each group of the floating field plates overlaps a right side region of the corresponding field limiting ring, and the extension regions extend to the termination ring.

[0013] Further, the substrate is an N-type substrate, a Pbody is doped in the main junction region corresponding to the N-type substrate, and an N+ type termination ring is provided in the termination ring corresponding to the N-type substrate.

[0014] Further, the substrate is a P-type substrate, an Nbody is doped in the main junction region corresponding to the P-type substrate, and a P+ type termination ring is provided in the termination ring corresponding to the P-type substrate.

[0015] Further, a chip scribe lane is provided on the outside of the termination ring, and the main junction region and the termination ring are respectively connected with metal field plates.

[0016] The second aspect of the present application provides a preparation method of a field limiting ring terminal structure of a power semiconductor device, for preparing the field limiting ring terminal structure as described above, the preparation method comprising:

[0017] providing a substrate, growing an epitaxial layer on one side of the substrate, and dividing the whole formed by the substrate and the epitaxial layer into a cell region and a terminal region;

[0018] corresponding to the cell region, photoetching and implantation of the main junction region on the epitaxial layer, photoetching and implantation of the field limiting ring and the cutoff ring on the epitaxial layer corresponding to the terminal region; wherein the field limiting ring is arranged spaced apart from the surface of the epitaxial layer, and the field limiting ring is arranged between the main junction region and the cutoff ring;

[0019] corresponding to the generated position of the field limiting ring, generating a field oxide layer on the surface of the epitaxial layer;

[0020] generating a floating field plate on the surface of the field oxide layer; wherein the floating field plate includes an overlapping area corresponding to the field limiting ring, and an extended area corresponding to the area between adjacent field limiting rings, and the extended area is used for attracting holes.

[0021] Further, the preparation method further comprises:

[0022] connecting the main junction region and the cutoff ring to the metal field plate respectively through a via connection process.

[0023] Compared with the prior art, the field limiting ring terminal structure and the preparation method of the power semiconductor device provided by the application have the beneficial effects that:

[0024] (1) The field limiting ring is arranged spaced apart from the surface of the epitaxial layer, and the field limiting ring is transferred from the surface of the device to the body of the device, so that the electric field can be moved from the surface to the body, thereby avoiding the influence of surface charges and realizing the stability of voltage and the reliability of the ideal insulated gate field effect transistor.

[0025] (2) The floating field plate is prepared on the surface of the field oxide layer, and the floating field plate is an equipotential body, which can attract and fix movable charges in the field oxide layer on one hand, and can attract holes below the extended area of the floating field plate beyond the field limiting ring on the other hand, so as to achieve the purpose of assisting the field limiting ring to deplete and extend the depletion region. Ultimately, the floating field plate can stabilize the charges and assist the field limiting ring to deplete, thereby realizing the ideal voltage stability. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a structural schematic diagram of the field limiting ring terminal structure of the power semiconductor device in the related art;

[0027] Figure 2 is a schematic diagram of the field limiting ring terminal structure of the power semiconductor device provided in the first embodiment of the application;

[0028] Figure 3 - Figure 6 is a schematic diagram of the corresponding relationship between the floating field plate and the field limiting ring provided in the first embodiment of the application;

[0029] Figure 7This is a flowchart of the fabrication method of the field-limiting ring termination structure of the power semiconductor device in the second embodiment of the present invention;

[0030] Figure 8 - Figure 14 This is a schematic diagram of the fabrication process of the field limiting ring terminal structure of the power semiconductor device in the second embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0032] It should be understood that the specific embodiments described herein are merely used in the description of the present invention. It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0033] In related technologies, the field-limiting loop termination structure of conventional N-type high-voltage power devices is as follows: Figure 1 As shown, the substrate is an N-Sub substrate, the epitaxial layer is an N-Epi layer, and the left side represents the cell region. P-body structures are formed by etching and implantation within the cell region. The P-body structures in the cell region are connected to the metal field plate (Metal) through vias. The PN junction formed by the P-body structures and the N-Epi epitaxial layer in the cell region is similar to a parallel planar junction, and its longitudinal breakdown voltage can approach the theoretical maximum value. The lateral PN junctions between the P-body structures and the N-Epi epitaxial layer are cylindrical and spherical junctions, with breakdown voltages much lower than those of parallel planar junctions. Devices are often affected by junction curvature effects, causing electric fields to accumulate near the junction, making the device highly susceptible to breakdown. Therefore, termination structures are needed to mitigate the impact of junction curvature effects on the breakdown voltage of power devices.

[0034] Example 1

[0035] like Figure 2 The schematic diagram of the field-limiting loop termination structure shown illustrates that, in the first embodiment of the present invention, a field-limiting loop termination structure for a power semiconductor device is provided, comprising: a cell region and a termination region surrounding the cell region. The cell region of the power semiconductor device is composed of multiple repeating units. In the depletion state, the electric field distribution in the breakdown layer of the cell region is uniform everywhere; therefore, breakdown due to electric field concentration will not occur in the cell region.

[0036] The application provides a field limiting ring terminal structure of a power semiconductor device, which realizes more ideal voltage stability by adding a field limiting ring and a floating field plate to assist depletion.

[0037] Specifically, the terminal region and the cell region include a common substrate and an epitaxial layer extending along one side of the substrate; wherein, as one of the embodiments of the application, the substrate is a substrate N-Sub of a first conductive type, and the epitaxial layer formed is an epitaxial layer N-Epi of the first conductive type.

[0038] In the cell region, the epitaxial layer N-Epi is provided with a main junction region of a second conductive type away from one side of the substrate N-Sub, and a P-type dopant is implanted in the main junction region to form a Pbody, and the main junction region Pbody is arranged on the surface of the epitaxial layer N-Epi.

[0039] In the terminal region, the epitaxial layer N-Epi is provided with a plurality of groups of field limiting rings R of the second conductive type away from one side of the substrate N-Sub, and a P-type dopant is implanted in the field limiting rings R to form Pring, and the plurality of groups of field limiting rings R are arranged away from the surface of the epitaxial layer N-Epi, that is, the field limiting rings R are away from the surface of the epitaxial layer N-Epi by a certain distance. Through the implementation of the scheme, the field limiting rings R are transferred from the surface of the device to the body of the device, so that the electric field is moved from the surface to the body, thereby avoiding the influence of surface charges.

[0040] In addition, a field oxide layer FOX of silicon dioxide material is arranged on the surface of the epitaxial layer N-Epi corresponding to the field limiting rings R, the field oxide layer FOX shields interface charges, improves electric field distribution, ensures breakdown voltage, and improves reliability.

[0041] Further, a floating field plate poly is arranged on the surface of the field oxide layer FOX, the floating field plate poly includes an overlapping area corresponding to the field limiting rings R and an extension area corresponding to the area between adjacent field limiting rings R, and the extension area is used for attracting holes. The floating field plate poly is an equipotential body, which can attract and fix movable charges in the field oxide layer on one hand, and can assist the field limiting rings R in depletion on the other hand. Since the cutoff ring N+ area is high voltage and the cell main junction region Pbody area is low voltage, the area of the floating field plate poly beyond the field limiting rings R will attract holes below the poly, and the holes are P-type semiconductors, which can assist the field limiting rings R in depletion and extend the depletion region, so as to finally realize the effect of stabilizing charges and assisting the field limiting rings in depletion.

[0042] In some embodiments, the number of floating field plates Poly is one, and the whole floating field plate Poly covers the underlying field limiting rings R, so as to form the effect that the floating field plate Poly covers both the field limiting rings and the area between adjacent field limiting rings. The area corresponding to the field limiting ring R is defined as the overlapping area, and the area between adjacent field limiting rings R is defined as the extended area. In this case, the floating field plate Poly includes extended areas arranged in sequence, and the overlapping areas are arranged between adjacent extended areas. The extended areas will attract holes underneath. For details, refer to the setting structure of the floating field plate shown in Figure 3

[0043] In some embodiments, the number of floating field plates Poly is several, and each floating field plate Poly corresponds to one field limiting ring. In this embodiment, several small floating field plates Poly are arranged, and each group of small floating field plates Poly corresponds to one field limiting ring. Similar to the previous embodiment, each group of small floating field plates Poly completely covers one field limiting ring. That is, each group of floating field plates Poly includes an overlapping area and extended areas on both sides of the overlapping area. The overlapping area is relatively coincident with the corresponding field limiting ring, and the extended areas on both sides relatively exceed the width of the field limiting ring. For details, refer to the setting structure of the floating field plate shown in Figure 4

[0044] In some embodiments, the number of floating field plates Poly is also several, and each floating field plate Poly corresponds to one field limiting ring. In this case, each group of floating field plates Poly includes an overlapping area and an extended area on one side of the overlapping area. In the setting process of the floating field plates Poly, the overlapping area on the floating field plate Poly partially overlaps the corresponding field limiting ring. In a specific embodiment, the overlapping area of the floating field plate Poly overlaps the left area of the corresponding field limiting ring R, and the extended area extends to the main junction region Pbody. Alternatively, the overlapping area of each group of floating field plates Poly overlaps the right area of the corresponding field limiting ring R, and the extended area extends to the cutoff ring N+. For details, refer to the setting structure of the floating field plate shown in Figure 5 Figure 6

[0045] ​​​​In summary, the above provides four setting modes of the floating field plate Poly. According to the voltage stabilizing effect, the overlapping area of the floating field plate Poly and the right area of the corresponding field limiting ring R, and the voltage stabilizing effect of the extended area extending to the cutoff ring N+ is better than that of the other three modes. Among them, according to different voltage withstand levels and different distances between field limiting rings, the distance xn (xn includes x1, x2, x3, …) of the extended area of the floating field plate Poly relative to the field limiting ring R exceeding the field limiting ring R is 1-10 μm, and the length of the overlapping coverage of the field limiting ring R is sn (sn includes s1, s2, s3, …), and the value of sn does not exceed the width of the field limiting ring R.

[0046] In some embodiments, Pring is implanted in each field limiting ring R. It should be noted that the outermost of the power semiconductor device is also provided with a cutoff ring N+ of the first conductive type, and each field limiting ring R is arranged between the main junction region Pbody and the cutoff ring N+ in sequence, and the main junction region Pbody and the cutoff ring N+ are connected with a metal field plate Metal through a hole, and a scribe lane is arranged outside the cutoff ring N+.

[0047] The distance of each group of field limiting rings R from the surface of the epitaxial layer N-Epi is defined as h1, the height of each group of field limiting rings R is h2, the distance between the main junction region Pbody and the substrate N-Sub is h3, the distance between the main junction region Pbody and the cutoff ring N+ is d1, the distance between the field limiting ring R1 and the main junction region Pbody is n1 (wherein the field limiting ring R1 is the field limiting ring adjacent to the main junction region Pbody, and the field limiting rings are numbered in order from near to far from the main junction region Pbody as R1, R2, …, Rn), the distance between each group of field limiting rings R is nx, and the width of each group of field limiting rings R is Lx; the above parameters have the following relationships:

[0048] The number of field limiting rings R corresponding to different voltage withstands is also different, and the higher the voltage withstand, the more the number of field limiting rings. According to different voltage withstands 50v-1500v, the number of field limiting rings can be 1-10 groups.

[0049] h1: Each group of field limiting rings R is implanted by high-energy energy once, so the distance h1 of each group of field limiting rings R from the surface of N-Epi is consistent, and the size of h1 can be between 0.5um and 5um.

[0050] h2: The height h2 of each group of field limiting rings R is consistent, and the size of h2 can be between 0.5um and 4um.

[0051] h3: The distance h3 of the main junction region Pbody from the substrate N-Sub, and the size of h3 is related to the voltage withstand of the power device, and the higher the voltage withstand, the greater the value of h3, and the size of h3 can be selected in the range of 5um-120um.

[0052] d1: the distance between the main junction region Pbody and the cutoff ring N+ is d1, the distance d1 is related to the voltage resistance of the power device, the higher the voltage resistance, the longer the d1, and the size of d1 can be between 10um-200um.

[0053] nx: the distance between the field limiting ring R1 and the Pbody is n1, the distance between each group of field limiting rings R is n2, n3 and nx (corresponding to more groups of field limiting rings), the sizes of n1, n2, n3 and nx can be the same or different, and the distance between each group of field limiting rings R can be set to 5um-20um.

[0054] Lx: the width of each field limiting ring R is L1, L2, L3 and Lx (corresponding to more groups of field limiting rings), the sizes of L1, L2, L3 and Lx can be the same or different, and the width of each group of field limiting rings R can be set to 2um-10um.

[0055] It should be noted that in the preparation of the power semiconductor, the substrate type can generally be divided into N-type substrate and P-type substrate, and in the above example, the substrate is an N-type substrate, the main junction region corresponding to the N-type substrate is doped to form a Pbody, and the cutoff ring corresponding to the N-type substrate is N+; It should be understood that the substrate type can also be a P-type substrate, the main junction region corresponding to the P-type substrate is doped to form an Nbody, and the cutoff ring corresponding to the P-type substrate is P+.

[0056] By the field limiting ring terminal structure of the power semiconductor device of the present application, the field limiting ring is transferred from the device surface to the device body, which can move the electric field from the surface to the body, thereby avoiding the influence of surface charges and realizing stable voltage, especially realizing more ideal reliability of the insulated gate field effect transistor; and a floating field plate is prepared on the surface of the field oxide layer, which is an equipotential body, which can attract and fix movable charges in the field oxide layer on one hand, and can attract holes below the extension area of the floating field plate beyond the field limiting ring on the other hand, thereby achieving the purpose of assisting the field limiting ring to deplete, and extending the depletion region. Finally, the effect of stable charge and assisting the field limiting ring to deplete is realized, and more ideal voltage stability is realized.

[0057] Embodiment 2

[0058] The second embodiment of the present application provides a preparation method for preparing the field limiting ring terminal structure as described in the first embodiment, as shown in Figure 3 The flow chart of the preparation method is shown, which comprises the following steps:

[0059] Step 701, providing a substrate and growing an epitaxial layer on one side of the substrate, and dividing the whole formed by the substrate and the epitaxial layer into a cell region and a terminal region.

[0060] The substrate material can be N-type material or P-type material. According to the type of the substrate material, an epitaxial layer is grown on the substrate material. Taking the substrate material N-Sub as an example, the substrate material N-Sub and the epitaxial layer N-Epi can be doped with a certain concentration of dopant. The thickness of the substrate N-Sub can be 6 μm to 60 μm. The thickness of the epitaxial layer N-Epi can be set according to different voltage resistance. Generally, the optional thickness of the epitaxial layer N-Epi can be 7 μm to 120 μm. The method for growing the epitaxial layer N-Epi includes sputtering deposition and other methods.

[0061] In step 702, the photolithography and implantation of the main junction region are performed on the epitaxial layer corresponding to the cell region. The photolithography and implantation of the field limiting ring and the termination ring are performed on the epitaxial layer corresponding to the termination region.

[0062] First of all, it should be noted that the order of the photolithography and implantation of the main junction region Pbody, the termination ring N+ and the field limiting ring R is not limited. The completed field limiting ring termination structure is arranged between the main junction region Pbody and the termination ring N+ with the field limiting ring R spaced from the surface of the epitaxial layer N-Epi.

[0063] When the photolithography and implantation of the main junction region Pbody are performed, the Pbody implantation region: by implanting Al ions, a Pbody with a suitable impurity concentration distribution is formed. Generally, after the implantation of the Pbody, a Pbody high-temperature push well is required. The temperature can be 1050°C to 1250°C, and the time can be 100 minutes to 700 minutes.

[0064] The photolithography and implantation of the termination ring N+ are performed. The N+ termination ring is formed by implanting nitrogen ions at high temperature. A scribe groove is further arranged outside the termination ring. The surface of the scribe groove can be further covered with photoresist.

[0065] The photolithography and implantation of the field limiting ring R are performed. The corresponding dopant Pring is implanted into the substrate material. It is worth noting that the implantation angle of the dopant Pring is 0°, so that the implantation can be deeper relative to the surface of the epitaxial layer N-Epi. After implantation, a push well is performed or the entire device is placed in a high-temperature environment. Inert gas is introduced for annealing to complete the preparation of the field limiting ring R.

[0066] In step 703, a field oxide layer is generated on the surface of the epitaxial layer corresponding to the position where the field limiting ring is generated.

[0067] The field oxide layer FOX is generated before the formation of the field limiting ring R or after the formation of the field limiting ring R. The field oxide layer FOX is generated by high-temperature water vapor oxidation, and the thickness of the field oxide layer FOX is 0.8 μm to 2 μm. After the field oxide layer FOX is generated, AA photolithography and AA etching are performed on the field oxide layer FOX. In addition, the field oxide layer FOX can also be generated by a LOCOS process containing silicon nitride SiN.

[0068] Specifically, if the field oxide layer FOX is generated before the formation of the field limiting ring R, it can be understood that the field limiting ring R is implemented in the middle and later stages of the entire process, so that the influence of the heat process of other steps on the concentration distribution of the dopant Pring can be avoided. However, a very high implantation energy of 1 MeV to 5 MeV is required when the dopant Pring is implanted and needs to penetrate the field oxide layer FOX. If the field oxide layer FOX is generated after the formation of the field limiting ring R, it can be understood that the field limiting ring R is implemented in the middle and early stages of the entire process. At this time, the implantation of the dopant Pring in the field limiting ring can also be implemented by using a lower energy of 300 Kev to 4 MeV.

[0069] In step 704, a floating field plate is generated on the surface of the field oxide layer.

[0070] The floating field plate includes an overlapping region corresponding to the field limiting ring and an extension region corresponding to a region between adjacent field limiting rings, and the extension region is used to attract holes.

[0071] In some embodiments, the number of floating field plates Poly is one, and one floating field plate Poly is used to cover the field limiting ring R located below, so as to form the effect that the floating field plate Poly can cover both the field limiting ring and the region between adjacent field limiting rings. The region corresponding to the field limiting ring R is defined as an overlapping region, and the region between adjacent field limiting rings is defined as an extension region. At this time, the floating field plate Poly includes extension regions arranged in sequence, and the overlapping regions are arranged between adjacent extension regions. The extension regions attract holes below.

[0072] In some embodiments, the number of floating field plates Poly is several, and the several floating field plates Poly one-to-one correspond to the several field limiting rings. In this embodiment, a plurality of small floating field plates Poly are arranged, and each group of small floating field plates Poly corresponds to one field limiting ring. Similar to the previous embodiment, each group of small floating field plates Poly completely covers one field limiting ring. That is, each group of floating field plates Poly includes an overlapping region and extension regions located on both sides of the overlapping region. The overlapping region is relatively coincident with the corresponding field limiting ring, and the extension regions on both sides relatively exceed the width of the field limiting ring.

[0073] In some embodiments, the number of floating field plates Poly is also several, and each of the several floating field plates Poly corresponds to one of the several field limiting rings. In this case, each group of floating field plates Poly includes an overlapping region and an extended region on one side of the overlapping region. During the setting of the floating field plates Poly, the overlapping region of the floating field plates Poly partially overlaps with the corresponding field limiting ring. In a specific embodiment, the overlapping region of the floating field plates Poly overlaps with the left side region of the corresponding field limiting ring, and the extended region extends to the main junction region; or, the overlapping region of each group of floating field plates Poly overlaps with the right side region of the corresponding field limiting ring, and the extended region extends to the termination ring.

[0074] As a preferred implementation in this embodiment, the overlapping region of each group of floating field plates Poly overlaps with the right side region of the corresponding field limiting ring, and the extended region extends to the termination ring. The thickness of the floating field plates Poly is usually between 0.2 um and 2.0 um.

[0075] Step 705: connecting the main junction region and the termination ring to the metal field plate through a via connection process.

[0076] The following describes a method for preparing a field limiting ring termination structure of a power device. In this embodiment, the substrate is an N-type material, and the floating field plates Poly are set in a manner that the overlapping region of the floating field plates Poly overlaps with the right side region of the corresponding field limiting ring, and the extended region extends to the termination ring. In one of the embodiments of this embodiment, the method specifically includes the following steps:

[0077] First, an N-type Epi is grown on an N-type heavily doped Sub material to form a substrate N-Sub and an epitaxial layer N-Epi. The thickness of the substrate N-Sub is 10 um, the thickness of the epitaxial layer N-Epi is 100 um, and the doping concentration of the substrate N-Sub and the epitaxial layer N-Epi is 1×10E13 cm －3 ~ 1×10E15 cm －3 Then, a field oxide layer FOX with a thickness of 1.2 um is grown through high-temperature water vapor oxidation. Next, AA lithography and AA etching are performed, and the morphology after etching is as shown in Figure 8 .

[0078] Subsequently, main junction region lithography and Pbody implantation are performed, and Pbody high-temperature push well is performed after Pbody implantation. The temperature of the high-temperature push well is 1100°C, and the time is 500 minutes. Then, N+ lithography and N+ implantation are performed. Finally, a structure as shown in Figure 9 is formed.

[0079] Next, field ring R lithography and implantation are performed. Since there is a field oxide layer FOX as a barrier, Pring implantation needs to use high-energy implantation. As one of the embodiments of the present application, element P-type material boron ions are implanted into the epitaxial layer N-Epi at an angle of 0° and an implantation energy of 3 MeV. After implantation, a push-out is performed to obtain the structure as shown in FIG. 2. Figure 10 It should be noted that the field ring R formed by lithography and implantation is at a certain distance from the surface of the epitaxial layer N-Epi.

[0080] Then, gate oxide and floating field plate Poly deposition, lithography and etching are performed. The thickness of the gate oxide is relatively thin, usually between 0.05 um and 0.2 um, and the thickness of the Poly deposition is usually between 1.0 um. The Poly of this step can be used as a terminal field plate and a gate electrode Gate Poly, to obtain the structure as shown in FIG. 3. Figure 11

[0081] Finally, the hole and metallization processes in the back-end are performed to finally obtain the structure as shown in FIG. 4. Figure 1

[0082] In another embodiment of the present application, the preparation method specifically includes the following steps:

[0083] First, an N-type Epi is grown on an N-type heavily doped Sub material. The thickness of the substrate N-Sub is 10 um, the thickness of the epitaxial layer N-Epi is 100 um, and the doping concentration of the substrate N-Sub and the epitaxial layer N-Epi is 1 x 10E13 cm －3 ~ 1 x 10E15 cm －3 . Then, field ring R lithography and dopant Pring implantation are performed. Since the dopant Pring needs to be implanted into the substrate N-Sub, high-energy implantation is needed when the dopant Pring is implanted, the implantation energy is 1 MeV, the implanted element is P-type material boron ions, and the implantation angle is 0°. After implantation, a push-out is performed to obtain the structure as shown in FIG. 5. Figure 12 Similarly, the field ring R formed is at a certain distance from the epitaxial layer N-Epi.

[0084] Then, a 1.2 um field oxide layer FOX is grown by high-temperature water vapor oxidation. Next, AA lithography and AA etching are performed, and the etched profile is as shown in FIG. 6. Figure 13

[0085] Subsequently, as in the previous embodiment, main junction area lithography and Pbody implantation are performed. After Pbody implantation is completed, Pbody high-temperature push-out is performed, and the high-temperature push-out temperature can be between 1100°C, and the time is 500 minutes. Then, N+ lithography and N+ implantation are performed to form a cutoff ring N+, to finally form the structure as shown in FIG. 7. Figure 10 ​​​​

[0086] Next, gate oxide and floating field plate Poly deposition, lithography and etching are performed. The thickness of the gate oxide is relatively thin, usually between 0.05um and 0.2um, and the thickness of the Poly deposition is usually between 1.0um. The Poly of this step can be used as the terminal field plate and the Gate Poly, and the structure shown in Figure 11 is obtained.

[0087] Finally, the hole and metallization process of the later stage is performed, and the same structure shown in Figure 1 is obtained.

[0088] In other embodiments of the present embodiment, the preparation method specifically comprises the following steps:

[0089] First, N-type Epi is grown on the N-type heavily doped Sub material, the thickness of the substrate N-Sub is 10um, the thickness of the epitaxial layer N-Epi is 100um, and the doping concentration of the substrate N-Sub and the epitaxial layer N-Epi is 1x10E13cm －3 ~ 1x10E15cm －3 . Then, lithography and implantation of the dopant Pring of the field limiting ring R are performed. Since the implantation is performed in the substrate N-Sub, high-energy implantation is required when the dopant Pring is implanted, the implantation energy is 1Mev, the implantation element is P-type material boron ion, the implantation angle is 0°, and after implantation, the push well is performed, and the structure shown in Figure 12 is obtained. Similarly, the field limiting ring R formed has a certain distance from the epitaxial layer N-Epi.

[0090] Then, 1.2um of field oxide layer FOX is grown by high-temperature water vapor oxidation. Next, AA lithography and AA etching are performed, and the topography after etching is shown in Figure 13 .

[0091] Next, gate oxide and floating field plate Poly deposition, lithography and etching are performed. The thickness of the gate oxide is relatively thin, usually between 0.05um and 0.2um, and the thickness of the Poly deposition is usually between 1.0um. The Poly of this step can be used as the terminal field plate and the Gate Poly, and the structure shown in Figure 14 is obtained.

[0092] Subsequently, as in the previous embodiment, the main junction region is subjected to lithography and Pbody implantation. After the Pbody implantation is completed, the Pbody high-temperature push well is performed, and the temperature of the high-temperature push well can be between 1100°C, and the time is 500 minutes. Then, N+ lithography and N+ implantation are performed to form the cutoff ring N+, and finally the structure shown in Figure 11 is formed.

[0093] Finally, a back-end via and metallization process is performed to obtain the same structure as shown in Figure 1

[0094] In summary, the present application prepares a field limiting ring terminal structure of a power semiconductor device, which moves the field limiting ring from the surface of the device to the body of the device, so as to move the electric field from the surface to the body, thereby avoiding the influence of surface charges and realizing stable voltage, especially realizing more ideal reliability of an insulated gate field effect transistor. A floating field plate is prepared on the surface of the field oxide layer, which is an equipotential body, and can attract and fix movable charges in the field oxide layer on one hand, and can attract holes below the extension area of the field limiting ring on the other hand, so as to achieve the purpose of assisting the field limiting ring to be depleted, and extend the depletion region. Finally, the effect of both stable charges and assisting the field limiting ring to be depleted is realized, and more ideal voltage stability is achieved.

[0095] The above merely provides the preferred embodiment of the present application, but should not be used to limit the present application, and any modification, equivalent replacement and improvement within the spirit and principle of the present application should be included in the protection scope of the present application.​

Claims

1. A field-limiting ring termination structure for a power semiconductor device, characterized by, The application relates to a field limiting ring terminal structure, comprising: a cell region and a terminal region formed at the periphery of the cell region, the terminal region and the cell region comprising a common substrate and an epitaxial layer extending along one side of the substrate; wherein, a main junction region is arranged at the side of the cell region away from the substrate, and the main junction region is arranged on the surface of the epitaxial layer; the terminal region comprises a plurality of field limiting rings and a cutoff ring, the cutoff ring is arranged at the edge of the terminal region away from the main junction region, the plurality of field limiting rings are arranged between the main junction region and the cutoff ring in sequence, and the plurality of field limiting rings are arranged away from the surface of the terminal region; the surface of the terminal region is covered with a field oxide layer in the regions corresponding to the plurality of field limiting rings, and a floating field plate is arranged on the surface of the field oxide layer, the floating field plate comprises overlapping regions corresponding to the field limiting rings and extension regions corresponding to the regions between adjacent field limiting rings, and the extension regions are used for attracting holes; the overlapping regions of the floating field plate overlap with the right side regions of the corresponding field limiting rings; the plurality of floating field plates one-to-one correspond to the plurality of field limiting rings, and each group of floating field plates comprises overlapping regions and extension regions located at one side of the overlapping regions, the overlapping regions partially overlap with the corresponding field limiting rings; the overlapping regions of each group of floating field plates overlap with the right side regions of the corresponding field limiting rings, and the extension regions extend to the cutoff ring.

2. The field-limiting ring termination structure of claim 1, wherein The substrate is an N-type substrate, the doping of the main junction region corresponding to the N-type substrate forms a Pbody, and the cutoff ring corresponding to the N-type substrate is an N+ type cutoff ring.

3. The field-limiting ring termination structure of claim 1, wherein The substrate is a P-type substrate, the doping of the main junction region corresponding to the P-type substrate forms an Nbody, and the cutoff ring corresponding to the P-type substrate is a P+ type cutoff ring.

4. The field-limiting ring termination structure of claim 1, wherein A chip scribe lane is arranged at the outside of the cutoff ring, and the main junction region and the cutoff ring are respectively connected with metal field plates.

5. A method for fabricating a field-limiting ring termination structure for a power semiconductor device, characterized in that, A preparation method for preparing the field limiting ring terminal structure as claimed in any one of claims 1-4, the preparation method comprising: providing a substrate and growing an epitaxial layer on one side of the substrate, and dividing the whole formed by the substrate and the epitaxial layer into a cell region and a terminal region; performing photolithography and implantation of a main junction region on the epitaxial layer corresponding to the cell region, and performing photolithography and implantation of field limiting rings and a cutoff ring on the epitaxial layer corresponding to the terminal region; wherein the field limiting rings are arranged away from the surface of the epitaxial layer, and the field limiting rings are arranged between the main junction region and the cutoff ring; generating a field oxide layer on the surface of the epitaxial layer corresponding to the generated positions of the field limiting rings; generating a floating field plate on the surface of the field oxide layer; wherein the floating field plate comprises overlapping regions corresponding to the field limiting rings and extension regions corresponding to the regions between adjacent field limiting rings, and the extension regions are used for attracting holes; and the overlapping regions of the floating field plate overlap with the right side regions of the corresponding field limiting rings.

6. The preparation method according to claim 5, characterized in that, The preparation method further comprises: connecting the main junction region and the cutoff ring to metal field plates respectively through a via connection process.

Images