Power semiconductor device thermal resistance monitoring method and system based on gate leakage current

Abstract

The invention discloses a power semiconductor device thermal resistance monitoring method and system based on grid leakage current. The system comprises a voltage source, a current source, a thermocouple and a grid leakage current monitoring module. The voltage source is used for providing voltage excitation for the power semiconductor device to be tested; the current source is used for applying current excitation to the to-be-tested power semiconductor device, so that the to-be-tested power semiconductor device reaches a thermal stable state; the thermocouple is used for extracting the shell temperature of the to-be-tested power semiconductor device in a thermal stable state and further obtaining the thermal resistance value of the to-be-tested power semiconductor device by combining the power loss and the temperature rise data; and the grid leakage current monitoring module is used for evaluating the junction temperature of the power semiconductor device to be measured based on the grid leakage current. According to the monitoring method, direct junction temperature extraction is completed based on grid leakage current, thermal resistance is measured and calculated in combination with current excitation, shell temperature collection and power loss data, and integrated acquisition of thermal characteristic parameters is achieved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device measurement technology, and specifically to a method and system for monitoring the thermal resistance of power semiconductor devices based on gate leakage current. Background Technology

[0002] Power semiconductor devices, as the core of modern power electronic systems, are rapidly developing towards high frequency, high voltage, and high power density. The internal power loss and thermal performance of power semiconductor devices are crucial to their reliability, efficiency, and lifespan. Accurate monitoring of junction temperature is essential for assessing device health and predicting remaining lifetime. In recent years, thermal resistance monitoring methods have gradually become a research hotspot, with the gate leakage current method receiving widespread attention due to its high sensitivity and potential for online monitoring.

[0003] Existing methods for monitoring thermal resistance and junction temperature all have significant limitations: physical contact thermometry, as an indirect measurement method, cannot accurately reflect the junction temperature inside the chip, and the installation of the sensor itself can disrupt the thermal field distribution of the device, introducing measurement errors; it is an invasive measurement method. While optical thermometry can visually display the temperature distribution, it requires the device chip to be exposed, limiting its use to offline analysis, and the equipment is expensive, making online monitoring of packaged devices impossible. Thermal resistance model prediction methods simulate the junction temperature distribution using algorithms such as the finite element method when power loss and the thermal resistance network are known. Although this method is non-invasive, its accuracy is low due to the time-varying nature of the thermal resistance network parameters. These limitations make it difficult to perform true online monitoring under continuous system operation, resulting in significant constraints on practicality, convenience, and accuracy.

[0004] Therefore, existing technologies require a non-invasive, interference-free, and highly accurate method for monitoring thermal resistance and junction temperature during normal operation of power devices. In-depth research into the mapping relationship between gate leakage current and junction temperature, and the establishment of a robust thermal resistance inversion model, are of significant value in promoting the practical application of this technology and improving the reliability management level of power devices. Summary of the Invention

[0005] This invention provides a method and system for monitoring the thermal resistance of power semiconductor devices based on gate leakage current. The method is non-invasive, highly accurate, and multi-parameter linkage, and is suitable for thermal characteristic evaluation and reliability analysis of power semiconductor devices.

[0006] The technical solution adopted in this invention is as follows: A power semiconductor device thermal resistance monitoring system based on gate leakage current, the system comprising: Voltage source, current source, thermocouple, and gate leakage current monitoring module; The power semiconductor device under test is connected to a voltage source, a current source, a thermocouple, and a gate leakage current monitoring module, respectively. A voltage source is used to provide voltage excitation to the power semiconductor device under test. A current source is used to apply current excitation to the power semiconductor device under test so that the power semiconductor device under test can reach a thermally stable state. Thermocouples are used to extract the case temperature of the power semiconductor device under test in a thermally stable state, and then combine the power loss and temperature rise data to obtain the thermal resistance value of the power semiconductor device under test. The gate leakage current monitoring module evaluates the junction temperature of the power semiconductor device under test based on the gate leakage current.

[0007] The gate leakage current monitoring module includes: The first-stage amplification unit, the second-stage amplification unit, and the third-stage amplification unit are connected in sequence, wherein: The first-stage amplification unit is used to convert the gate leakage current into a voltage signal and simultaneously perform preliminary amplification of the signal amplitude. The second-stage amplification unit is used to extract the differential-mode voltage signal converted by the first-stage amplification unit and further amplify the extracted differential-mode voltage signal. The third-stage amplification unit further amplifies the differential-mode voltage signal extracted by the second-stage amplification unit according to the amplitude requirements of the signal extraction.

[0008] Meanwhile, to suppress the influence of noise on the gate leakage current monitoring results, active low-pass filters are connected to the output terminals of the first-stage amplification unit, the second-stage amplification unit, and the third-stage amplification unit. The active low-pass filters are used to process the effective signals of each stage, and finally the gate leakage current signal of the device is obtained.

[0009] The primary amplification unit includes: operational amplifier OP1, operational amplifier OP2, and resistors. R 1. Sampling resistor R 2; The positive terminal of voltage source U1 is connected to the non-inverting input terminal of operational amplifier OP1, and the positive terminal of voltage source U1 is connected to the GND terminal. Resistor connected to the inverting input of operational amplifier OP1 R 1. One end, resistor R 1. The other end is connected to the output of operational amplifier OP1 and the non-inverting input of operational amplifier OP2, respectively. The inverting input of operational amplifier OP2 is connected to sampling resistors. R 2. One end, the gate of a power semiconductor device; sampling resistor R 2. Connect the other end to the output of operational amplifier OP2.

[0010] The first-stage amplification unit is connected to a first-stage SK filter, and the first-stage SK filter includes: a resistor. R 3. Resistance R4. Operational amplifier OP3, capacitor C1, capacitor C2; Resistor connected to the output of operational amplifier OP2 R 3. One end, resistor R 3. The other end is connected to one end of capacitor C1 and the resistor respectively. R 4 at one end, The other end of capacitor C1 is connected to the inverting input and output terminals of operational amplifier OP3, respectively, and resistor... R 4. The other end is connected to the non-inverting input terminal of operational amplifier OP3 and one end of capacitor C2, respectively. The other end of capacitor C2 is connected to the sampling resistor. R 2. Connect one end to GND1.

[0011] The secondary amplification unit includes: operational amplifiers OP4, OP5, and OP6, and resistors. R 5~Resistors R 11 ; Connect GND1 to the non-inverting input of operational amplifier OP4. Connect resistors to the output of operational amplifier OP4. R 5. One end, resistor R 8 at one end; resistance R 8. The other end is connected to a resistor. R 10 One end is the inverting input of operational amplifier OP6. Resistors are connected to the inverting input of operational amplifier OP4. R 5. The other end, resistor R 6. One end; resistance R 6. The other end is connected to the inverting input of operational amplifier OP5 and the resistor, respectively. R 7. The non-inverting input terminal of operational amplifier OP5 is connected to the output terminal of operational amplifier OP3; Resistors are connected to the output terminals of operational amplifier OP5. R 7. The other end, resistor R 9. One end; resistance R 9. The other end is connected to the non-inverting input of operational amplifier OP6 and the resistor, respectively. R 11 One end; resistor R 11 The other end is connected to GND1.

[0012] The secondary amplification unit is connected to a secondary SK filter, which includes: an operational amplifier OP7 and a resistor. R 12 ,resistance R 13 Capacitor C3, capacitor C4; Resistor connected to the output of operational amplifier OP6 R 12 One end, resistor R 12 The other end is connected to one end of capacitor C3 and the resistor, respectively. R 13 One end; The other end of capacitor C3 is connected to the output terminal of operational amplifier OP7 and the inverting input terminal of operational amplifier OP7, respectively. resistance R 13 The other end is connected to one end of capacitor C4 and the non-inverting input of operational amplifier OP7, respectively; The other end of capacitor C4 is connected to GND1.

[0013] The three-stage amplification unit includes: an operational amplifier OP8, and resistors. R 14 ,resistance R 15 ; The output of operational amplifier OP7 is connected to the non-inverting input of operational amplifier OP8, and the inverting input of operational amplifier OP8 is connected to the source of the power semiconductor device and a resistor, respectively. R 15 One end, resistor R 15 The other end is connected to GND1. Drain connection resistor of power semiconductor devices R 14 One end, resistor R 14 The other end is connected to GND1.

[0014] The three-stage amplification unit is connected to a three-stage SK filter, which includes: an operational amplifier OP9, a resistor... R 16 ,resistance R 17 Capacitor C5, capacitor C6; resistance R 14 One end is connected to a resistor R 16 One end, resistor R 16 The other end is connected to one end of capacitor C5 and the resistor respectively. R 17 One end; The other end of capacitor C5 is connected to the output terminal and the inverting input terminal of operational amplifier OP9, respectively; resistance R 17The other end is connected to the non-inverting input terminal of operational amplifier OP9 and one end of capacitor C6, respectively. The other end of capacitor C6 is connected to GND1.

[0015] A method for monitoring the thermal resistance of power semiconductor devices based on gate leakage current is proposed. A first-stage, second-stage, and third-stage amplification unit amplifies and monitors the gate leakage current generated under excitation, thereby extracting the current. The monitoring system, relying on the extracted current data and a pre-calibrated gate leakage current-temperature characteristic curve, evaluates the junction temperature of the power semiconductor device under test at the corresponding current state. The junction temperature of the power semiconductor device in thermal steady state is extracted from the gate leakage current using the characteristic curve of the gate leakage current characteristic parameter versus junction temperature. The case temperature of the power semiconductor device under test is extracted using a thermocouple, and the power consumed by the power semiconductor device is then considered. P According to the formula R th = ( T J -T C ) / P Evaluate the thermal resistance of the power semiconductor device under test.

[0016] A method for monitoring the thermal resistance of power semiconductor devices based on gate leakage current is proposed. Since the gate leakage current of a power semiconductor device exhibits a positive temperature characteristic relationship with its junction temperature under a given gate-source voltage, the corresponding junction temperature can be evaluated by assessing the gate leakage current during the device's operation. To monitor the thermal resistance of the power semiconductor device, a current source is used to inject power into the power terminal of the device. After the device reaches thermal stability, the power loss is extracted. Meanwhile, the thermocouple extracts the case temperature of the power semiconductor device under test when the device is thermally stable. By extracting junction temperature based on gate leakage current, the case temperature and power loss of power semiconductor devices can be obtained, thereby enabling the monitoring of the thermal resistance of power semiconductor devices.

[0017] This invention provides a method and system for monitoring the thermal resistance of power semiconductor devices based on gate leakage current, with the following technical advantages: 1) Achieve integrated monitoring of junction temperature and thermal resistance: The junction temperature is directly extracted based on the gate leakage current, and the thermal resistance is calculated by combining current excitation, case temperature acquisition and power loss data, so as to achieve integrated acquisition of thermal characteristic parameters.

[0018] 2) Improved monitoring accuracy and reliability: The three-stage amplification unit solves the problem of acquiring minute gate leakage current, and the constructed filter effectively suppresses high-frequency noise interference, providing stable data for junction temperature assessment; through multi-parameter calibration of junction temperature, case temperature, and power, the error of monitoring a single parameter is reduced, improving the reliability of thermal resistance calculation.

[0019] 3) Simple circuit and easy to integrate: The required detection system consists of an operational amplifier and resistors, which has a simple structure and low operational complexity.

[0020] 4) High versatility: The thermal resistance monitoring method for power semiconductor devices based on gate leakage current is applicable to a variety of power switching devices and has high versatility. Attached Figure Description

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a block diagram of the thermal resistance monitoring system for the device under test of the present invention.

[0022] Figure 2 The schematic diagrams are of the first-stage amplifier circuit and the first-stage SK filter of the device under test in this invention.

[0023] Figure 3 The schematic diagrams are of the two-stage amplifier circuit and the two-stage SK filter of the device under test in this invention.

[0024] Figure 4 The schematic diagrams are of the three-stage amplifier circuit and the three-stage SK filter of the device under test in this invention.

[0025] Figure 5 This is a schematic diagram of the gate leakage current monitoring circuit in the LTspice simulation.

[0026] Figure 6 The circuit simulation results are for a voltage source outputting +5V voltage.

[0027] Figure 7 The curves show the characteristics of GaN gate leakage current and junction temperature when the gate-source voltage is +5V and the gate leakage current is amplified by 300 times.

[0028] Figure 8(a) is a schematic diagram of the working principle of the device under test of the present invention; Figure 8(b) is a flowchart of the monitoring method of the present invention. Detailed Implementation

[0029] A method and system for monitoring the thermal resistance of power semiconductor devices based on gate leakage current is presented. The monitoring system comprises a voltage source, a first-stage amplification unit, a second-stage amplification unit, a third-stage amplification unit, a thermocouple, and a current source. Specifically: the voltage source provides voltage excitation to the device under test (DUT); the amplification unit amplifies and monitors the gate leakage current generated under excitation, thereby extracting the current; the monitoring system, based on the extracted current data and a pre-calibrated gate leakage current-temperature characteristic curve, evaluates the junction temperature of the DUT under the corresponding current state; the current source applies current excitation to the DUT to bring it to a thermally stable state; and the thermocouple extracts the case temperature of the DUT under thermal stability, and then combines this with power loss and temperature rise data to obtain the thermal resistance value of the DUT. This method uses the gate leakage current of the power semiconductor device as a thermistor characteristic. Under multiple known temperature environments, the same gate voltage is applied to the power semiconductor device under test to extract the gate leakage current; a functional relationship model between the gate leakage current characteristic parameter and temperature is established, which is then used to invert the junction temperature of the power semiconductor device. This method is non-invasive, high-precision, and multi-parameter linked, making it suitable for the thermal characteristic evaluation and reliability analysis of power semiconductor devices.

[0030] like Figure 1 The diagram shows a block diagram of a power semiconductor device thermal resistance monitoring system according to the present invention. It includes a voltage source, a first-stage amplification unit, a second-stage amplification unit, a third-stage amplification unit, a thermocouple, and a current source.

[0031] The working principle of the gate leakage current monitoring circuit of this invention is as follows: Figures 2-4 As shown.

[0032] 1) When voltage source U1 is connected to operational amplifier OP1, since the gate leakage current is very small, the first-stage amplification unit usually uses a high input impedance amplifier to avoid sampling resistance. R 2. The impact on the monitoring circuit, converting the weak current signal into a voltage signal. Due to the virtual short of the operational amplifier, the same voltage is generated at the inverting input of operational amplifier OP2, resulting in gate leakage current at the inverting input of operational amplifier OP2. I GSS sampling resistor R The current on 2 is for power semiconductor devices. I GSS Sampling resistor R 2. Voltage across the terminals U S and I GSS The relationship is as shown in equation (1): ; The high-frequency noise in the amplified signal is filtered out by the first-stage SK filter, thereby ensuring the purity and reliability of the signal amplification process.

[0033] 2) The sampling resistor of the second-stage amplification unit is collected. R The voltage of 2 is differentially amplified. The second-stage amplifier unit circuit mainly consists of two stages of differential amplifier circuits, used to suppress common-mode signals and extract differential-mode signals. Among them, operational amplifiers OP4 and OP5 are in-phase differential input, thus giving the instrumentation amplifier circuit better common-mode rejection capability than a simple differential amplifier circuit. Figure 3 The gain of the circuit is given by equation (2): ; Secondary amplification unit acquisition U S Differential amplification is performed to output a voltage that reflects the magnitude of the gate current. U , U and I GSS The relationship is as shown in equation (3): ; In the two-stage amplification unit, the two-stage SK filter, as an operational amplifier-based active filter structure, features high input impedance, low output impedance, and signal amplification capability, improving the signal-to-noise ratio and acting as a buffer. In practical designs, the SK filter is embedded in the signal path for frequency conditioning, enhancing the stability and signal quality of the amplifier circuit.

[0034] 3) The output of the second-stage amplifier unit is connected to the non-inverting input of operational amplifier OP8. When the output of the second-stage amplifier unit... U At that time, due to the virtual short, the same voltage is generated at the inverting input terminal of operational amplifier OP8. The inverting input terminal of operational amplifier OP8 and the resistor... R 15 Connection, in R 15 A current is generated on the resistor, and at the same time, the output voltage of the operational amplifier OP8 turns on the power semiconductor device. R 14 With resistance R 15 In series, the current flowing through them is the same, and the monitoring resistor is... R 14 voltage on U out The size can be determined. I GSS Size, U out and I GSS The relationship is as shown in equation (4): ; Among them, the three-stage SK filter removes high-frequency noise from the amplified signal, ensuring the purity and reliability of the signal amplification process.

[0035] Simulation example: In this embodiment, a power semiconductor device gate current monitoring circuit model was built using LTspice, as follows: Figure 5 As shown. In the simulation circuit, resistors are used. R 1. To simulate the gate resistance of the GaN device under test, adjust the resistance. R A resistance value generates microampere-level and nanoampere-level currents, and in the simulation, the voltage source outputs a +5V voltage.

[0036] Simulation output waveform as follows Figure 6 As shown, when the voltage source outputs +5V, the gate current amplifier circuit in the three-stage amplifier unit is turned on, and the resistor... R 11 The voltage on it is 500mV.

[0037] When GaN devices were tested at a gate-source voltage of +5V, the relationship between their gate leakage current and junction temperature exhibited a positive temperature characteristic, meaning the gate leakage current increased with increasing junction temperature. Figure 7 As shown.

[0038] The monitoring system extracts data through an amplification circuit. I GSS ,according to I GSS With junction temperature T J The characteristic curves of the GaN device under test (DUT) are used to evaluate its junction temperature. A current source is applied to the DUT to induce a thermally stable state. The current at the thermally stable state of the DUT is then extracted. I 0. The monitoring system combines the extracted data... I 0 and the drain-source voltage of the GaN device under test U DS Through the electric power formula P=U DS I 0, the power loss of the device under test is calculated. The case temperature of the GaN device under test under thermal stability is extracted using a thermocouple. T C Furthermore, by combining the power loss and temperature rise data as shown in equation (5), the thermistor parameters of the power semiconductor device can be obtained.

[0039] .

Claims

1. A power semiconductor device thermal resistance monitoring system based on gate leakage current, characterized in that... The system includes: Voltage source, current source, thermocouple, and gate leakage current monitoring module; The power semiconductor device under test is connected to a voltage source, a current source, a thermocouple, and a gate leakage current monitoring module, respectively. A voltage source is used to provide voltage excitation to the power semiconductor device under test. A current source is used to apply current excitation to the power semiconductor device under test. Thermocouples are used to extract the case temperature of a power semiconductor device under thermal stability. The gate leakage current monitoring module evaluates the junction temperature of the power semiconductor device under test based on the gate leakage current.

2. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 1, characterized in that: The gate leakage current monitoring module includes: The first-stage amplification unit, the second-stage amplification unit, and the third-stage amplification unit are connected in sequence, wherein: The first-stage amplification unit is used to convert the gate leakage current into a voltage signal and simultaneously perform preliminary amplification of the signal amplitude. The second-stage amplification unit is used to extract the differential-mode voltage signal converted by the first-stage amplification unit and further amplify the extracted differential-mode voltage signal. The third-stage amplification unit further amplifies the differential-mode voltage signal extracted by the second-stage amplification unit according to the amplitude requirements of the signal extraction.

3. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 2, characterized in that: To suppress the influence of noise on the gate leakage current monitoring results, active low-pass filters are connected to the output terminals of the first-stage, second-stage, and third-stage amplification units. The active low-pass filters are used to process the effective signals of each stage to finally obtain the gate leakage current signal of the device.

4. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 3, characterized in that: The primary amplification unit includes: operational amplifier OP1, operational amplifier OP2, and resistors. R 1. Sampling resistor R 2; The positive terminal of voltage source U1 is connected to the non-inverting input terminal of operational amplifier OP1, and the positive terminal of voltage source U1 is connected to the GND terminal. Resistor connected to the inverting input of operational amplifier OP1 R 1. One end, resistor R 1. The other end is connected to the output of operational amplifier OP1 and the non-inverting input of operational amplifier OP2, respectively. The inverting input of operational amplifier OP2 is connected to sampling resistors. R 2. One end, the gate of a power semiconductor device; sampling resistor R 2. Connect the other end to the output of operational amplifier OP2.

5. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 4, characterized in that: The first-stage amplification unit is connected to a first-stage SK filter, and the first-stage SK filter includes: a resistor. R 3. Resistance R 4. Operational amplifier OP3, capacitor C1, capacitor C2; Resistor connected to the output of operational amplifier OP2 R 3. One end, resistor R 3. The other end is connected to one end of capacitor C1 and the resistor respectively. R 4 at one end, The other end of capacitor C1 is connected to the inverting input and output terminals of operational amplifier OP3, respectively, and resistor... R 4. The other end is connected to the non-inverting input terminal of operational amplifier OP3 and one end of capacitor C2, respectively. The other end of capacitor C2 is connected to the sampling resistor. R 2. Connect one end to GND1.

6. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 5, characterized in that: The secondary amplification unit includes: operational amplifiers OP4, OP5, and OP6, and resistors. R 5~Resistors R 11 ; Connect GND1 to the non-inverting input of operational amplifier OP4. Connect resistors to the output of operational amplifier OP4. R 5. One end, resistor R 8 at one end; resistance R 8. The other end is connected to a resistor. R 10 One end is the inverting input of operational amplifier OP6. Resistors are connected to the inverting input of operational amplifier OP4. R 5. The other end, resistor R 6. One end; resistance R 6. The other end is connected to the inverting input of operational amplifier OP5 and the resistor, respectively. R 7. The non-inverting input terminal of operational amplifier OP5 is connected to the output terminal of operational amplifier OP3; Resistors are connected to the output terminals of operational amplifier OP5. R 7. The other end, resistor R 9. One end; resistance R 9. The other end is connected to the non-inverting input of operational amplifier OP6 and the resistor, respectively. R 11 One end; resistor R 11 The other end is connected to GND1.

7. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 6, characterized in that: The secondary amplification unit is connected to a secondary SK filter, which includes: an operational amplifier OP7 and a resistor. R 12 ,resistance R 13 Capacitor C3, capacitor C4; Resistor connected to the output of operational amplifier OP6 R 12 One end, resistor R 12 The other end is connected to one end of capacitor C3 and the resistor respectively. R 13 One end; The other end of capacitor C3 is connected to the output terminal of operational amplifier OP7 and the inverting input terminal of operational amplifier OP7, respectively. resistance R 13 The other end is connected to one end of capacitor C4 and the non-inverting input of operational amplifier OP7, respectively; The other end of capacitor C4 is connected to GND1.

8. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 7, characterized in that: The three-stage amplification unit includes: operational amplifier OP8, resistors... R 14 ,resistance R 15 ; The output of operational amplifier OP7 is connected to the non-inverting input of operational amplifier OP8, and the inverting input of operational amplifier OP8 is connected to the source of the power semiconductor device and a resistor, respectively. R 15 One end, resistor R 15 The other end is connected to GND1. Drain connection resistor of power semiconductor devices R 14 One end, resistor R 14 The other end is connected to GND1.

9. The power semiconductor device thermal resistance monitoring system based on gate leakage current according to claim 7, characterized in that: The three-stage amplification unit is connected to a three-stage SK filter, which includes: an operational amplifier OP9, a resistor... R 16 ,resistance R 17 Capacitor C5, capacitor C6; resistance R 14 One end is connected to a resistor R 16 One end, resistor R 16 The other end is connected to one end of capacitor C5 and the resistor respectively. R 17 One end; The other end of capacitor C5 is connected to the output terminal and the inverting input terminal of operational amplifier OP9, respectively; resistance R 17 The other end is connected to the non-inverting input terminal of operational amplifier OP9 and one end of capacitor C6, respectively. The other end of capacitor C6 is connected to GND1.

10. A method for monitoring the thermal resistance of a power semiconductor device using a thermal resistance monitoring system as described in any one of claims 1 to 9, characterized in that: The first-stage, second-stage, and third-stage amplification units amplify and monitor the gate leakage current generated under excitation, thereby extracting the current. Based on the extracted current data and combined with the pre-calibrated gate leakage current-temperature characteristic curve, the monitoring system completes the evaluation of the junction temperature of the power semiconductor device under test under the corresponding current state. By analyzing the characteristic curves of gate leakage current versus junction temperature, the junction temperature of the power semiconductor device in thermal steady state is extracted from the gate leakage current. The case temperature of the power semiconductor device under test is extracted using a thermocouple. Based on the power consumed by the power semiconductor device... P According to the formula R th = ( T J -T C ) / P Evaluate the thermal resistance of the power semiconductor device under test.

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